sys/arm/lpc/lpc_ohci.c

   1 /*-
   2  * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  */
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/stdint.h>
  31 #include <sys/stddef.h>
  32 #include <sys/param.h>
  33 #include <sys/queue.h>
  34 #include <sys/types.h>
  35 #include <sys/systm.h>
  36 #include <sys/kernel.h>
  37 #include <sys/bus.h>
  38 #include <sys/module.h>
  39 #include <sys/lock.h>
  40 #include <sys/mutex.h>
  41 #include <sys/condvar.h>
  42 #include <sys/sysctl.h>
  43 #include <sys/rman.h>
  44 #include <sys/sx.h>
  45 #include <sys/unistd.h>
  46 #include <sys/callout.h>
  47 #include <sys/malloc.h>
  48 #include <sys/priv.h>
  49
  50 #include <sys/kdb.h>
  51
  52 #include <dev/ofw/ofw_bus.h>
  53 #include <dev/ofw/ofw_bus_subr.h>
  54
  55 #include <dev/usb/usb.h>
  56 #include <dev/usb/usbdi.h>
  57
  58 #include <dev/usb/usb_core.h>
  59 #include <dev/usb/usb_busdma.h>
  60 #include <dev/usb/usb_process.h>
  61 #include <dev/usb/usb_util.h>
  62
  63 #include <dev/usb/usb_controller.h>
  64 #include <dev/usb/usb_bus.h>
  65 #include <dev/usb/controller/ohci.h>
  66 #include <dev/usb/controller/ohcireg.h>
  67
  68 #include <arm/lpc/lpcreg.h>
  69 #include <arm/lpc/lpcvar.h>
  70
  71 #define I2C_START_BIT           (1 << 8)
  72 #define I2C_STOP_BIT            (1 << 9)
  73 #define I2C_READ                0x01
  74 #define I2C_WRITE               0x00
  75 #define DUMMY_BYTE              0x55
  76
  77 #define lpc_otg_read_4(_sc, _reg)                                       \
  78     bus_space_read_4(_sc->sc_io_tag, _sc->sc_io_hdl, _reg)
  79 #define lpc_otg_write_4(_sc, _reg, _value)                              \
  80     bus_space_write_4(_sc->sc_io_tag, _sc->sc_io_hdl, _reg, _value)
  81 #define lpc_otg_wait_write_4(_sc, _wreg, _sreg, _value)                 \
  82     do {                                                                \
  83         lpc_otg_write_4(_sc, _wreg, _value);                            \
  84         while ((lpc_otg_read_4(_sc, _sreg) & _value) != _value);        \
  85     } while (0);
  86
  87 static int lpc_ohci_probe(device_t dev);
  88 static int lpc_ohci_attach(device_t dev);
  89 static int lpc_ohci_detach(device_t dev);
  90
  91 static void lpc_otg_i2c_reset(struct ohci_softc *);
  92
  93 static int lpc_isp3101_read(struct ohci_softc *, int);
  94 static void lpc_isp3101_write(struct ohci_softc *, int, int);
  95 static void lpc_isp3101_clear(struct ohci_softc *, int, int);
  96 static void lpc_isp3101_configure(device_t dev, struct ohci_softc *);
  97
  98 static int
  99 lpc_ohci_probe(device_t dev)
 100 {
 101
 102         if (!ofw_bus_status_okay(dev))
 103                 return (ENXIO);
 104
 105         if (!ofw_bus_is_compatible(dev, "lpc,usb-ohci"))
 106                 return (ENXIO);
 107
 108         device_set_desc(dev, "LPC32x0 USB OHCI controller");
 109         return (BUS_PROBE_DEFAULT);
 110 }
 111
 112 static int
 113 lpc_ohci_attach(device_t dev)
 114 {
 115         struct ohci_softc *sc = device_get_softc(dev);
 116         int err;
 117         int rid;
 118         int i = 0;
 119         uint32_t usbctrl;
 120         uint32_t otgstatus;
 121
 122         sc->sc_bus.parent = dev;
 123         sc->sc_bus.devices = sc->sc_devices;
 124         sc->sc_bus.devices_max = OHCI_MAX_DEVICES;
 125
 126         if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev),
 127             &ohci_iterate_hw_softc))
 128                 return (ENOMEM);
 129
 130         rid = 0;
 131         sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
 132         if (!sc->sc_io_res) {
 133                 device_printf(dev, "cannot map OHCI register space\n");
 134                 goto fail;
 135         }
 136
 137         sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
 138         sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
 139         sc->sc_io_size = rman_get_size(sc->sc_io_res);
 140
 141         rid = 0;
 142         sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
 143         if (sc->sc_irq_res == NULL) {
 144                 device_printf(dev, "cannot allocate interrupt\n");
 145                 goto fail;
 146         }
 147
 148         sc->sc_bus.bdev = device_add_child(dev, "usbus", -1);
 149         if (!(sc->sc_bus.bdev))
 150                 goto fail;
 151
 152         device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
 153         strlcpy(sc->sc_vendor, "NXP", sizeof(sc->sc_vendor));
 154
 155         err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
 156             NULL, (void *)ohci_interrupt, sc, &sc->sc_intr_hdl);
 157         if (err) {
 158                 sc->sc_intr_hdl = NULL;
 159                 goto fail;
 160         }
 161
 162         usbctrl = lpc_pwr_read(dev, LPC_CLKPWR_USB_CTRL);
 163         usbctrl |= LPC_CLKPWR_USB_CTRL_SLAVE_HCLK | LPC_CLKPWR_USB_CTRL_BUSKEEPER;
 164         lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl);
 165
 166         /* Enable OTG I2C clock */
 167         lpc_otg_wait_write_4(sc, LPC_OTG_CLOCK_CTRL,
 168             LPC_OTG_CLOCK_STATUS, LPC_OTG_CLOCK_CTRL_I2C_EN);
 169
 170         /* Reset OTG I2C bus */
 171         lpc_otg_i2c_reset(sc);
 172
 173         lpc_isp3101_configure(dev, sc);
 174
 175         /* Configure PLL */
 176         usbctrl &= ~(LPC_CLKPWR_USB_CTRL_CLK_EN1 | LPC_CLKPWR_USB_CTRL_CLK_EN2);
 177         lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl);
 178
 179         usbctrl |= LPC_CLKPWR_USB_CTRL_CLK_EN1;
 180         lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl);
 181
 182         usbctrl |= LPC_CLKPWR_USB_CTRL_FDBKDIV(192-1);
 183         usbctrl |= LPC_CLKPWR_USB_CTRL_POSTDIV(1);
 184         usbctrl |= LPC_CLKPWR_USB_CTRL_PLL_PDOWN;
 185
 186         lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl);
 187         do {
 188                 usbctrl = lpc_pwr_read(dev, LPC_CLKPWR_USB_CTRL);
 189                 if (i++ > 100000) {
 190                         device_printf(dev, "USB OTG PLL doesn't lock!\n");
 191                         goto fail;
 192                 }
 193         } while ((usbctrl & LPC_CLKPWR_USB_CTRL_PLL_LOCK) == 0);
 194
 195         usbctrl |= LPC_CLKPWR_USB_CTRL_CLK_EN2;
 196         usbctrl |= LPC_CLKPWR_USB_CTRL_HOST_NEED_CLK_EN;
 197         lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl);
 198         lpc_otg_wait_write_4(sc, LPC_OTG_CLOCK_CTRL, LPC_OTG_CLOCK_STATUS,
 199             (LPC_OTG_CLOCK_CTRL_AHB_EN | LPC_OTG_CLOCK_CTRL_OTG_EN |
 200             LPC_OTG_CLOCK_CTRL_I2C_EN | LPC_OTG_CLOCK_CTRL_HOST_EN));
 201
 202         otgstatus = lpc_otg_read_4(sc, LPC_OTG_STATUS);
 203         lpc_otg_write_4(sc, LPC_OTG_STATUS, otgstatus |
 204             LPC_OTG_STATUS_HOST_EN);
 205
 206         lpc_isp3101_write(sc, LPC_ISP3101_OTG_CONTROL_1,
 207             LPC_ISP3101_OTG1_VBUS_DRV);
 208
 209         err = ohci_init(sc);
 210         if (err)
 211                 goto fail;
 212
 213         err = device_probe_and_attach(sc->sc_bus.bdev);
 214         if (err)
 215                 goto fail;
 216
 217         return (0);
 218
 219 fail:
 220         if (sc->sc_intr_hdl)
 221                 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl);
 222         if (sc->sc_irq_res)
 223                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
 224         if (sc->sc_io_res)
 225                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_io_res);
 226
 227         return (ENXIO);
 228 }
 229
 230 static int
 231 lpc_isp3101_read(struct ohci_softc *sc, int reg)
 232 {
 233         int status;
 234         int i = 0;
 235
 236         lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX,
 237             (LPC_ISP3101_I2C_ADDR << 1) | I2C_START_BIT);
 238         lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, reg);
 239         lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, (LPC_ISP3101_I2C_ADDR << 1) |
 240             I2C_START_BIT | I2C_READ);
 241         lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, I2C_STOP_BIT | DUMMY_BYTE);
 242
 243         do {
 244                 status = lpc_otg_read_4(sc, LPC_OTG_I2C_STATUS);
 245                 i++;
 246         } while ((status & LPC_OTG_I2C_STATUS_TDI) == 0 || i < 100000);
 247
 248         lpc_otg_write_4(sc, LPC_OTG_I2C_STATUS, LPC_OTG_I2C_STATUS_TDI);
 249
 250         return (lpc_otg_read_4(sc, LPC_OTG_I2C_TXRX) & 0xff);
 251 }
 252
 253 static void
 254 lpc_otg_i2c_reset(struct ohci_softc *sc)
 255 {
 256         int ctrl;
 257         int i = 0;
 258
 259         lpc_otg_write_4(sc, LPC_OTG_I2C_CLKHI, 0x3f);
 260         lpc_otg_write_4(sc, LPC_OTG_I2C_CLKLO, 0x3f);
 261
 262         ctrl = lpc_otg_read_4(sc, LPC_OTG_I2C_CTRL);
 263         lpc_otg_write_4(sc, LPC_OTG_I2C_CTRL, ctrl | LPC_OTG_I2C_CTRL_SRST);
 264
 265         do {
 266                 ctrl = lpc_otg_read_4(sc, LPC_OTG_I2C_CTRL);
 267                 i++;
 268         } while (ctrl & LPC_OTG_I2C_CTRL_SRST);
 269 }
 270
 271 static void
 272 lpc_isp3101_write(struct ohci_softc *sc, int reg, int value)
 273 {
 274         int status;
 275         int i = 0;
 276
 277         bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_TXRX,
 278             (LPC_ISP3101_I2C_ADDR << 1) | I2C_START_BIT);
 279         bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_TXRX,
 280             (reg | I2C_WRITE));
 281         bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_TXRX,
 282             (value | I2C_STOP_BIT));
 283
 284         do {
 285                 status = bus_space_read_4(sc->sc_io_tag, sc->sc_io_hdl,
 286                     LPC_OTG_I2C_STATUS);
 287                 i++;
 288         } while ((status & LPC_OTG_I2C_STATUS_TDI) == 0 || i < 100000);
 289
 290         bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_STATUS,
 291             LPC_OTG_I2C_STATUS_TDI);
 292 }
 293
 294 static __inline void
 295 lpc_isp3101_clear(struct ohci_softc *sc, int reg, int value)
 296 {
 297         lpc_isp3101_write(sc, (reg | LPC_ISP3101_REG_CLEAR_ADDR), value);
 298 }
 299
 300 static void
 301 lpc_isp3101_configure(device_t dev, struct ohci_softc *sc)
 302 {
 303         lpc_isp3101_clear(sc, LPC_ISP3101_MODE_CONTROL_1, LPC_ISP3101_MC1_UART_EN);
 304         lpc_isp3101_clear(sc, LPC_ISP3101_MODE_CONTROL_1, ~LPC_ISP3101_MC1_SPEED_REG);
 305         lpc_isp3101_write(sc, LPC_ISP3101_MODE_CONTROL_1, LPC_ISP3101_MC1_SPEED_REG);
 306         lpc_isp3101_clear(sc, LPC_ISP3101_MODE_CONTROL_2, ~0);
 307         lpc_isp3101_write(sc, LPC_ISP3101_MODE_CONTROL_2,
 308             (LPC_ISP3101_MC2_BI_DI | LPC_ISP3101_MC2_PSW_EN
 309             | LPC_ISP3101_MC2_SPD_SUSP_CTRL));
 310
 311         lpc_isp3101_clear(sc, LPC_ISP3101_OTG_CONTROL_1, ~0);
 312         lpc_isp3101_write(sc, LPC_ISP3101_MODE_CONTROL_1, LPC_ISP3101_MC1_DAT_SE0);
 313         lpc_isp3101_write(sc, LPC_ISP3101_OTG_CONTROL_1,
 314             (LPC_ISP3101_OTG1_DM_PULLDOWN | LPC_ISP3101_OTG1_DP_PULLDOWN));
 315
 316         lpc_isp3101_clear(sc, LPC_ISP3101_OTG_CONTROL_1,
 317             (LPC_ISP3101_OTG1_DM_PULLUP | LPC_ISP3101_OTG1_DP_PULLUP));
 318
 319         lpc_isp3101_clear(sc, LPC_ISP3101_OTG_INTR_LATCH, ~0);
 320         lpc_isp3101_clear(sc, LPC_ISP3101_OTG_INTR_FALLING, ~0);
 321         lpc_isp3101_clear(sc, LPC_ISP3101_OTG_INTR_RISING, ~0);
 322
 323         device_printf(dev,
 324             "ISP3101 PHY <vendor:0x%04x, product:0x%04x, version:0x%04x>\n",
 325             (lpc_isp3101_read(sc, 0x00) | (lpc_isp3101_read(sc, 0x01) << 8)),
 326             (lpc_isp3101_read(sc, 0x03) | (lpc_isp3101_read(sc, 0x04) << 8)),
 327             (lpc_isp3101_read(sc, 0x14) | (lpc_isp3101_read(sc, 0x15) << 8)));
 328 }
 329
 330 static int
 331 lpc_ohci_detach(device_t dev)
 332 {
 333         return (0);
 334 }
 335
 336
 337 static device_method_t lpc_ohci_methods[] = {
 338         /* Device interface */
 339         DEVMETHOD(device_probe,         lpc_ohci_probe),
 340         DEVMETHOD(device_attach,        lpc_ohci_attach),
 341         DEVMETHOD(device_detach,        lpc_ohci_detach),
 342         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 343
 344         /* Bus interface */
 345         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 346         { 0, 0 }
 347 };
 348
 349 static driver_t lpc_ohci_driver = {
 350         "ohci",
 351         lpc_ohci_methods,
 352         sizeof(struct ohci_softc),
 353 };
 354
 355 static devclass_t lpc_ohci_devclass;
 356
 357 DRIVER_MODULE(ohci, simplebus, lpc_ohci_driver, lpc_ohci_devclass, 0, 0);
 358 MODULE_DEPEND(ohci, usb, 1, 1, 1);