2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate)
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
44 #include <dev/gpio/gpiobusvar.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
49 #include "syscon_if.h"
51 struct a37x0_gpio_softc {
56 struct syscon *syscon;
63 /* North Bridge / South Bridge. */
64 #define A37X0_NB_GPIO 1
65 #define A37X0_SB_GPIO 2
67 #define A37X0_GPIO_WRITE(_sc, _off, _val) \
68 SYSCON_WRITE_4((_sc)->syscon, (_off), (_val))
69 #define A37X0_GPIO_READ(_sc, _off) \
70 SYSCON_READ_4((_sc)->syscon, (_off))
72 #define A37X0_GPIO_BIT(_p) (1U << ((_p) % 32))
73 #define A37X0_GPIO_OUT_EN(_p) (0x0 + ((_p) / 32) * 4)
74 #define A37X0_GPIO_LATCH(_p) (0x8 + ((_p) / 32) * 4)
75 #define A37X0_GPIO_INPUT(_p) (0x10 + ((_p) / 32) * 4)
76 #define A37X0_GPIO_OUTPUT(_p) (0x18 + ((_p) / 32) * 4)
77 #define A37X0_GPIO_SEL 0x30
79 static struct ofw_compat_data compat_data[] = {
80 { "marvell,armada3710-nb-pinctrl", A37X0_NB_GPIO },
81 { "marvell,armada3710-sb-pinctrl", A37X0_SB_GPIO },
86 a37x0_gpio_get_node(device_t bus, device_t dev)
89 return (ofw_bus_get_node(bus));
93 a37x0_gpio_get_bus(device_t dev)
95 struct a37x0_gpio_softc *sc;
97 sc = device_get_softc(dev);
99 return (sc->sc_busdev);
103 a37x0_gpio_pin_max(device_t dev, int *maxpin)
105 struct a37x0_gpio_softc *sc;
107 sc = device_get_softc(dev);
108 *maxpin = sc->sc_npins - 1;
114 a37x0_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
116 struct a37x0_gpio_softc *sc;
118 sc = device_get_softc(dev);
119 if (pin >= sc->sc_npins)
121 snprintf(name, GPIOMAXNAME, "pin %d", pin);
127 a37x0_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
129 struct a37x0_gpio_softc *sc;
131 sc = device_get_softc(dev);
132 if (pin >= sc->sc_npins)
134 *caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
140 a37x0_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
142 struct a37x0_gpio_softc *sc;
145 sc = device_get_softc(dev);
146 if (pin >= sc->sc_npins)
148 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
149 if ((reg & A37X0_GPIO_BIT(pin)) != 0)
150 *flags = GPIO_PIN_OUTPUT;
152 *flags = GPIO_PIN_INPUT;
158 a37x0_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
160 struct a37x0_gpio_softc *sc;
163 sc = device_get_softc(dev);
164 if (pin >= sc->sc_npins)
167 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
168 if (flags & GPIO_PIN_OUTPUT)
169 reg |= A37X0_GPIO_BIT(pin);
171 reg &= ~A37X0_GPIO_BIT(pin);
172 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUT_EN(pin), reg);
178 a37x0_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
180 struct a37x0_gpio_softc *sc;
183 sc = device_get_softc(dev);
184 if (pin >= sc->sc_npins)
187 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
188 if ((reg & A37X0_GPIO_BIT(pin)) != 0)
189 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));
191 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_INPUT(pin));
192 *val = ((reg & A37X0_GPIO_BIT(pin)) != 0) ? 1 : 0;
198 a37x0_gpio_pin_set(device_t dev, uint32_t pin, unsigned int val)
200 struct a37x0_gpio_softc *sc;
203 sc = device_get_softc(dev);
204 if (pin >= sc->sc_npins)
207 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));
209 reg |= A37X0_GPIO_BIT(pin);
211 reg &= ~A37X0_GPIO_BIT(pin);
212 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg);
218 a37x0_gpio_pin_toggle(device_t dev, uint32_t pin)
220 struct a37x0_gpio_softc *sc;
223 sc = device_get_softc(dev);
224 if (pin >= sc->sc_npins)
227 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
228 if ((reg & A37X0_GPIO_BIT(pin)) == 0)
230 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));
231 reg ^= A37X0_GPIO_BIT(pin);
232 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg);
238 a37x0_gpio_probe(device_t dev)
241 struct a37x0_gpio_softc *sc;
243 if (!OF_hasprop(ofw_bus_get_node(dev), "gpio-controller"))
246 sc = device_get_softc(dev);
247 sc->sc_type = ofw_bus_search_compatible(
248 device_get_parent(dev), compat_data)->ocd_data;
249 switch (sc->sc_type) {
251 sc->sc_max_pins = 36;
252 desc = "Armada 37x0 North Bridge GPIO Controller";
255 sc->sc_max_pins = 30;
256 desc = "Armada 37x0 South Bridge GPIO Controller";
261 device_set_desc(dev, desc);
263 return (BUS_PROBE_DEFAULT);
267 a37x0_gpio_attach(device_t dev)
271 struct a37x0_gpio_softc *sc;
273 sc = device_get_softc(dev);
275 err = syscon_get_handle_default(dev, &sc->syscon);
277 device_printf(dev, "Cannot get syscon handle from parent\n");
281 /* Read and verify the "gpio-ranges" property. */
282 ncells = OF_getencprop_alloc(ofw_bus_get_node(dev), "gpio-ranges",
286 if (ncells != sizeof(*ranges) * 4 || ranges[1] != 0 || ranges[2] != 0) {
287 OF_prop_free(ranges);
290 sc->sc_npins = ranges[3];
291 OF_prop_free(ranges);
293 /* Check the number of pins in the DTS vs HW capabilities. */
294 if (sc->sc_npins > sc->sc_max_pins)
297 sc->sc_busdev = gpiobus_attach_bus(dev);
298 if (sc->sc_busdev == NULL)
305 a37x0_gpio_detach(device_t dev)
311 static device_method_t a37x0_gpio_methods[] = {
312 /* Device interface */
313 DEVMETHOD(device_probe, a37x0_gpio_probe),
314 DEVMETHOD(device_attach, a37x0_gpio_attach),
315 DEVMETHOD(device_detach, a37x0_gpio_detach),
318 DEVMETHOD(gpio_get_bus, a37x0_gpio_get_bus),
319 DEVMETHOD(gpio_pin_max, a37x0_gpio_pin_max),
320 DEVMETHOD(gpio_pin_getname, a37x0_gpio_pin_getname),
321 DEVMETHOD(gpio_pin_getcaps, a37x0_gpio_pin_getcaps),
322 DEVMETHOD(gpio_pin_getflags, a37x0_gpio_pin_getflags),
323 DEVMETHOD(gpio_pin_setflags, a37x0_gpio_pin_setflags),
324 DEVMETHOD(gpio_pin_get, a37x0_gpio_pin_get),
325 DEVMETHOD(gpio_pin_set, a37x0_gpio_pin_set),
326 DEVMETHOD(gpio_pin_toggle, a37x0_gpio_pin_toggle),
328 /* ofw_bus interface */
329 DEVMETHOD(ofw_bus_get_node, a37x0_gpio_get_node),
334 static devclass_t a37x0_gpio_devclass;
335 static driver_t a37x0_gpio_driver = {
338 sizeof(struct a37x0_gpio_softc),
341 EARLY_DRIVER_MODULE(a37x0_gpio, simple_mfd, a37x0_gpio_driver,
342 a37x0_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST);