2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate)
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
44 #include <dev/gpio/gpiobusvar.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
49 #include "syscon_if.h"
51 struct a37x0_gpio_softc {
56 struct syscon *syscon;
63 /* North Bridge / South Bridge. */
64 #define A37X0_NB_GPIO 1
65 #define A37X0_SB_GPIO 2
67 #define A37X0_GPIO_WRITE(_sc, _off, _val) \
68 SYSCON_WRITE_4((_sc)->syscon, (_off), (_val))
69 #define A37X0_GPIO_READ(_sc, _off) \
70 SYSCON_READ_4((_sc)->syscon, (_off))
72 #define A37X0_GPIO_BIT(_p) (1U << ((_p) % 32))
73 #define A37X0_GPIO_OUT_EN(_p) (0x0 + ((_p) / 32) * 4)
74 #define A37X0_GPIO_LATCH(_p) (0x8 + ((_p) / 32) * 4)
75 #define A37X0_GPIO_INPUT(_p) (0x10 + ((_p) / 32) * 4)
76 #define A37X0_GPIO_OUTPUT(_p) (0x18 + ((_p) / 32) * 4)
77 #define A37X0_GPIO_SEL 0x30
80 static struct ofw_compat_data compat_data[] = {
81 { "marvell,armada3710-nb-pinctrl", A37X0_NB_GPIO },
82 { "marvell,armada3710-sb-pinctrl", A37X0_SB_GPIO },
87 a37x0_gpio_get_node(device_t bus, device_t dev)
90 return (ofw_bus_get_node(bus));
94 a37x0_gpio_get_bus(device_t dev)
96 struct a37x0_gpio_softc *sc;
98 sc = device_get_softc(dev);
100 return (sc->sc_busdev);
104 a37x0_gpio_pin_max(device_t dev, int *maxpin)
106 struct a37x0_gpio_softc *sc;
108 sc = device_get_softc(dev);
109 *maxpin = sc->sc_npins - 1;
115 a37x0_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
117 struct a37x0_gpio_softc *sc;
119 sc = device_get_softc(dev);
120 if (pin >= sc->sc_npins)
122 snprintf(name, GPIOMAXNAME, "pin %d", pin);
128 a37x0_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
130 struct a37x0_gpio_softc *sc;
132 sc = device_get_softc(dev);
133 if (pin >= sc->sc_npins)
135 *caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
141 a37x0_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
143 struct a37x0_gpio_softc *sc;
146 sc = device_get_softc(dev);
147 if (pin >= sc->sc_npins)
149 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
150 if ((reg & A37X0_GPIO_BIT(pin)) != 0)
151 *flags = GPIO_PIN_OUTPUT;
153 *flags = GPIO_PIN_INPUT;
159 a37x0_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
161 struct a37x0_gpio_softc *sc;
164 sc = device_get_softc(dev);
165 if (pin >= sc->sc_npins)
168 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
169 if (flags & GPIO_PIN_OUTPUT)
170 reg |= A37X0_GPIO_BIT(pin);
172 reg &= ~A37X0_GPIO_BIT(pin);
173 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUT_EN(pin), reg);
179 a37x0_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
181 struct a37x0_gpio_softc *sc;
184 sc = device_get_softc(dev);
185 if (pin >= sc->sc_npins)
188 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
189 if ((reg & A37X0_GPIO_BIT(pin)) != 0)
190 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));
192 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_INPUT(pin));
193 *val = ((reg & A37X0_GPIO_BIT(pin)) != 0) ? 1 : 0;
199 a37x0_gpio_pin_set(device_t dev, uint32_t pin, unsigned int val)
201 struct a37x0_gpio_softc *sc;
204 sc = device_get_softc(dev);
205 if (pin >= sc->sc_npins)
208 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));
210 reg |= A37X0_GPIO_BIT(pin);
212 reg &= ~A37X0_GPIO_BIT(pin);
213 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg);
219 a37x0_gpio_pin_toggle(device_t dev, uint32_t pin)
221 struct a37x0_gpio_softc *sc;
224 sc = device_get_softc(dev);
225 if (pin >= sc->sc_npins)
228 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
229 if ((reg & A37X0_GPIO_BIT(pin)) == 0)
231 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));
232 reg ^= A37X0_GPIO_BIT(pin);
233 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg);
239 a37x0_gpio_probe(device_t dev)
242 struct a37x0_gpio_softc *sc;
244 if (!OF_hasprop(ofw_bus_get_node(dev), "gpio-controller"))
247 sc = device_get_softc(dev);
248 sc->sc_type = ofw_bus_search_compatible(
249 device_get_parent(dev), compat_data)->ocd_data;
250 switch (sc->sc_type) {
252 sc->sc_max_pins = 36;
253 desc = "Armada 37x0 North Bridge GPIO Controller";
256 sc->sc_max_pins = 30;
257 desc = "Armada 37x0 South Bridge GPIO Controller";
262 device_set_desc(dev, desc);
264 return (BUS_PROBE_DEFAULT);
268 a37x0_gpio_attach(device_t dev)
272 struct a37x0_gpio_softc *sc;
274 sc = device_get_softc(dev);
276 err = syscon_get_handle_default(dev, &sc->syscon);
278 device_printf(dev, "Cannot get syscon handle from parent\n");
282 /* Read and verify the "gpio-ranges" property. */
283 ncells = OF_getencprop_alloc(ofw_bus_get_node(dev), "gpio-ranges",
287 if (ncells != sizeof(*ranges) * 4 || ranges[1] != 0 || ranges[2] != 0) {
288 OF_prop_free(ranges);
291 sc->sc_npins = ranges[3];
292 OF_prop_free(ranges);
294 /* Check the number of pins in the DTS vs HW capabilities. */
295 if (sc->sc_npins > sc->sc_max_pins)
298 sc->sc_busdev = gpiobus_attach_bus(dev);
299 if (sc->sc_busdev == NULL)
306 a37x0_gpio_detach(device_t dev)
312 static device_method_t a37x0_gpio_methods[] = {
313 /* Device interface */
314 DEVMETHOD(device_probe, a37x0_gpio_probe),
315 DEVMETHOD(device_attach, a37x0_gpio_attach),
316 DEVMETHOD(device_detach, a37x0_gpio_detach),
319 DEVMETHOD(gpio_get_bus, a37x0_gpio_get_bus),
320 DEVMETHOD(gpio_pin_max, a37x0_gpio_pin_max),
321 DEVMETHOD(gpio_pin_getname, a37x0_gpio_pin_getname),
322 DEVMETHOD(gpio_pin_getcaps, a37x0_gpio_pin_getcaps),
323 DEVMETHOD(gpio_pin_getflags, a37x0_gpio_pin_getflags),
324 DEVMETHOD(gpio_pin_setflags, a37x0_gpio_pin_setflags),
325 DEVMETHOD(gpio_pin_get, a37x0_gpio_pin_get),
326 DEVMETHOD(gpio_pin_set, a37x0_gpio_pin_set),
327 DEVMETHOD(gpio_pin_toggle, a37x0_gpio_pin_toggle),
329 /* ofw_bus interface */
330 DEVMETHOD(ofw_bus_get_node, a37x0_gpio_get_node),
335 static devclass_t a37x0_gpio_devclass;
336 static driver_t a37x0_gpio_driver = {
339 sizeof(struct a37x0_gpio_softc),
342 EARLY_DRIVER_MODULE(a37x0_gpio, simple_mfd, a37x0_gpio_driver,
343 a37x0_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST);