sys/arm/mv/armada/wdt.c

   1 /*-
   2  * Copyright (c) 2006 Benno Rice.
   3  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
   4  * All rights reserved.
   5  *
   6  * Adapted to Marvell SoC by Semihalf.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/kernel.h>
  38 #include <sys/module.h>
  39 #include <sys/malloc.h>
  40 #include <sys/rman.h>
  41 #include <sys/kdb.h>
  42 #include <sys/timeet.h>
  43 #include <sys/timetc.h>
  44 #include <sys/watchdog.h>
  45 #include <machine/bus.h>
  46 #include <machine/cpu.h>
  47
  48 #include <arm/mv/mvreg.h>
  49 #include <arm/mv/mvvar.h>
  50
  51 #include <dev/ofw/ofw_bus.h>
  52 #include <dev/ofw/ofw_bus_subr.h>
  53
  54 #define INITIAL_TIMECOUNTER     (0xffffffff)
  55 #define MAX_WATCHDOG_TICKS      (0xffffffff)
  56 #define WD_RST_OUT_EN           0x00000002
  57
  58 #define MV_CLOCK_SRC_ARMV7      25000000        /* Timers' 25MHz mode */
  59
  60 struct mv_wdt_config {
  61         enum soc_family wdt_soc;
  62         uint32_t wdt_timer;
  63         void (*wdt_enable)(void);
  64         void (*wdt_disable)(void);
  65         unsigned int wdt_clock_src;
  66 };
  67
  68 static void mv_wdt_enable_armv5(void);
  69 static void mv_wdt_enable_armada_38x(void);
  70 static void mv_wdt_enable_armada_xp(void);
  71
  72 static void mv_wdt_disable_armv5(void);
  73 static void mv_wdt_disable_armada_38x(void);
  74 static void mv_wdt_disable_armada_xp(void);
  75
  76 static struct mv_wdt_config mv_wdt_armada_38x_config = {
  77         .wdt_soc = MV_SOC_ARMADA_38X,
  78         .wdt_timer = 4,
  79         .wdt_enable = &mv_wdt_enable_armada_38x,
  80         .wdt_disable = &mv_wdt_disable_armada_38x,
  81         .wdt_clock_src = MV_CLOCK_SRC_ARMV7,
  82 };
  83
  84 static struct mv_wdt_config mv_wdt_armada_xp_config = {
  85         .wdt_soc = MV_SOC_ARMADA_XP,
  86         .wdt_timer = 2,
  87         .wdt_enable = &mv_wdt_enable_armada_xp,
  88         .wdt_disable = &mv_wdt_disable_armada_xp,
  89         .wdt_clock_src = MV_CLOCK_SRC_ARMV7,
  90 };
  91
  92 static struct mv_wdt_config mv_wdt_armv5_config = {
  93         .wdt_soc = MV_SOC_ARMV5,
  94         .wdt_timer = 2,
  95         .wdt_enable = &mv_wdt_enable_armv5,
  96         .wdt_disable = &mv_wdt_disable_armv5,
  97         .wdt_clock_src = 0,
  98 };
  99
 100 struct mv_wdt_softc {
 101         struct resource *       wdt_res;
 102         struct mtx              wdt_mtx;
 103         struct mv_wdt_config *  wdt_config;
 104 };
 105
 106 static struct resource_spec mv_wdt_spec[] = {
 107         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
 108         { -1, 0 }
 109 };
 110
 111 static struct ofw_compat_data mv_wdt_compat[] = {
 112         {"marvell,armada-380-wdt",      (uintptr_t)&mv_wdt_armada_38x_config},
 113         {"marvell,armada-xp-wdt",       (uintptr_t)&mv_wdt_armada_xp_config},
 114         {"marvell,orion-wdt",           (uintptr_t)&mv_wdt_armv5_config},
 115         {NULL,                          (uintptr_t)NULL}
 116 };
 117
 118 static struct mv_wdt_softc *wdt_softc = NULL;
 119 int timers_initialized = 0;
 120
 121 static int mv_wdt_probe(device_t);
 122 static int mv_wdt_attach(device_t);
 123
 124 static uint32_t mv_get_timer_control(void);
 125 static void mv_set_timer_control(uint32_t);
 126 static void mv_set_timer(uint32_t, uint32_t);
 127
 128 static void mv_watchdog_event(void *, unsigned int, int *);
 129
 130 static device_method_t mv_wdt_methods[] = {
 131         DEVMETHOD(device_probe, mv_wdt_probe),
 132         DEVMETHOD(device_attach, mv_wdt_attach),
 133
 134         { 0, 0 }
 135 };
 136
 137 static driver_t mv_wdt_driver = {
 138         "wdt",
 139         mv_wdt_methods,
 140         sizeof(struct mv_wdt_softc),
 141 };
 142
 143 static devclass_t mv_wdt_devclass;
 144
 145 DRIVER_MODULE(wdt, simplebus, mv_wdt_driver, mv_wdt_devclass, 0, 0);
 146 static int
 147 mv_wdt_probe(device_t dev)
 148 {
 149
 150         if (!ofw_bus_status_okay(dev))
 151                 return (ENXIO);
 152
 153         if (!ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data)
 154                 return (ENXIO);
 155
 156         device_set_desc(dev, "Marvell Watchdog Timer");
 157         return (0);
 158 }
 159
 160 static int
 161 mv_wdt_attach(device_t dev)
 162 {
 163         struct mv_wdt_softc *sc;
 164         int error;
 165
 166         if (wdt_softc != NULL)
 167                 return (ENXIO);
 168
 169         sc = device_get_softc(dev);
 170         wdt_softc = sc;
 171
 172         error = bus_alloc_resources(dev, mv_wdt_spec, &sc->wdt_res);
 173         if (error) {
 174                 device_printf(dev, "could not allocate resources\n");
 175                 return (ENXIO);
 176         }
 177
 178         mtx_init(&sc->wdt_mtx, "watchdog", NULL, MTX_DEF);
 179
 180         sc->wdt_config = (struct mv_wdt_config *)
 181            ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data;
 182
 183         if (sc->wdt_config->wdt_clock_src == 0)
 184                 sc->wdt_config->wdt_clock_src = get_tclk();
 185
 186         if (wdt_softc->wdt_config->wdt_disable != NULL)
 187                 wdt_softc->wdt_config->wdt_disable();
 188         EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
 189
 190         return (0);
 191 }
 192
 193 static __inline uint32_t
 194 mv_get_timer_control(void)
 195 {
 196
 197         return (bus_read_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL));
 198 }
 199
 200 static __inline void
 201 mv_set_timer_control(uint32_t val)
 202 {
 203
 204         bus_write_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL, val);
 205 }
 206
 207 static __inline void
 208 mv_set_timer(uint32_t timer, uint32_t val)
 209 {
 210
 211         bus_write_4(wdt_softc->wdt_res, CPU_TIMER0 + timer * 0x8, val);
 212 }
 213 static void
 214 mv_wdt_enable_armv5(void)
 215 {
 216         uint32_t val, irq_cause, irq_mask;
 217
 218         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 219         irq_cause &= IRQ_TIMER_WD_CLR;
 220         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 221
 222         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 223         irq_mask |= IRQ_TIMER_WD_MASK;
 224         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 225
 226         val = read_cpu_ctrl(RSTOUTn_MASK);
 227         val |= WD_RST_OUT_EN;
 228         write_cpu_ctrl(RSTOUTn_MASK, val);
 229
 230         val = mv_get_timer_control();
 231         val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
 232         mv_set_timer_control(val);
 233 }
 234
 235 static inline void
 236 mv_wdt_enable_armada_38x_xp_helper()
 237 {
 238         uint32_t val, irq_cause;
 239
 240         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 241         irq_cause &= IRQ_TIMER_WD_CLR;
 242         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 243
 244         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
 245         val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
 246         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 247
 248         val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
 249         val &= ~RSTOUTn_MASK_WD;
 250         write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
 251 }
 252
 253 static void
 254 mv_wdt_enable_armada_38x(void)
 255 {
 256         uint32_t val, irq_cause;
 257
 258         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 259         irq_cause &= IRQ_TIMER_WD_CLR;
 260         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 261
 262         mv_wdt_enable_armada_38x_xp_helper();
 263
 264         val = mv_get_timer_control();
 265         val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN;
 266         mv_set_timer_control(val);
 267 }
 268
 269 static void
 270 mv_wdt_enable_armada_xp(void)
 271 {
 272         uint32_t val, irq_cause;
 273         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP);
 274         irq_cause &= IRQ_TIMER_WD_CLR_ARMADAXP;
 275         write_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP, irq_cause);
 276
 277         mv_wdt_enable_armada_38x_xp_helper();
 278
 279         val = mv_get_timer_control();
 280         val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
 281         mv_set_timer_control(val);
 282 }
 283
 284 static void
 285 mv_wdt_disable_armv5(void)
 286 {
 287         uint32_t val, irq_cause, irq_mask;
 288
 289         val = mv_get_timer_control();
 290         val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
 291         mv_set_timer_control(val);
 292
 293         val = read_cpu_ctrl(RSTOUTn_MASK);
 294         val &= ~WD_RST_OUT_EN;
 295         write_cpu_ctrl(RSTOUTn_MASK, val);
 296
 297         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 298         irq_mask &= ~(IRQ_TIMER_WD_MASK);
 299         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 300
 301         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 302         irq_cause &= IRQ_TIMER_WD_CLR;
 303         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 304 }
 305
 306 static __inline void
 307 mv_wdt_disable_armada_38x_xp_helper(void)
 308 {
 309         uint32_t val;
 310
 311         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
 312         val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
 313         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 314
 315         val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
 316         val |= RSTOUTn_MASK_WD;
 317         write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
 318 }
 319
 320 static void
 321 mv_wdt_disable_armada_38x(void)
 322 {
 323         uint32_t val;
 324
 325         val = mv_get_timer_control();
 326         val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
 327         mv_set_timer_control(val);
 328
 329         mv_wdt_disable_armada_38x_xp_helper();
 330 }
 331
 332 static void
 333 mv_wdt_disable_armada_xp(void)
 334 {
 335         uint32_t val;
 336
 337         val = mv_get_timer_control();
 338         val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
 339         mv_set_timer_control(val);
 340
 341         mv_wdt_disable_armada_38x_xp_helper();
 342 }
 343
 344 /*
 345  * Watchdog event handler.
 346  */
 347 static void
 348 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
 349 {
 350         struct mv_wdt_softc *sc;
 351         uint64_t ns;
 352         uint64_t ticks;
 353
 354         sc = arg;
 355         mtx_lock(&sc->wdt_mtx);
 356         if (cmd == 0) {
 357                 if (wdt_softc->wdt_config->wdt_disable != NULL)
 358                         wdt_softc->wdt_config->wdt_disable();
 359         } else {
 360                 /*
 361                  * Watchdog timeout is in nanosecs, calculation according to
 362                  * watchdog(9)
 363                  */
 364                 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
 365                 ticks = (uint64_t)(ns * sc->wdt_config->wdt_clock_src) / 1000000000;
 366                 if (ticks > MAX_WATCHDOG_TICKS) {
 367                         if (wdt_softc->wdt_config->wdt_disable != NULL)
 368                                 wdt_softc->wdt_config->wdt_disable();
 369                 }
 370                 else {
 371                         mv_set_timer(wdt_softc->wdt_config->wdt_timer, ticks);
 372                         if (wdt_softc->wdt_config->wdt_enable != NULL)
 373                                 wdt_softc->wdt_config->wdt_enable();
 374                         *error = 0;
 375                 }
 376         }
 377         mtx_unlock(&sc->wdt_mtx);
 378 }