2 * Copyright (c) 2015 Semihalf.
3 * Copyright (c) 2015 Stormshield.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/sysctl.h>
33 #include <sys/systm.h>
36 #include <machine/fdt.h>
38 #include <arm/mv/mvwin.h>
39 #include <arm/mv/mvreg.h>
40 #include <arm/mv/mvvar.h>
42 int armada38x_open_bootrom_win(void);
43 int armada38x_scu_enable(void);
44 int armada38x_win_set_iosync_barrier(void);
45 int armada38x_mbus_optimization(void);
46 static uint64_t get_sar_value_armada38x(void);
48 static int hw_clockrate;
49 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
50 &hw_clockrate, 0, "CPU instruction clock rate");
53 get_sar_value_armada38x(void)
55 uint32_t sar_low, sar_high;
58 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
59 SAMPLE_AT_RESET_ARMADA38X);
60 return (((uint64_t)sar_high << 32) | sar_low);
64 get_tclk_armada38x(void)
69 * On Armada38x TCLK can be configured to 250 MHz or 200 MHz.
70 * Current setting is read from Sample At Reset register.
72 sar = (uint32_t)get_sar_value_armada38x();
73 sar = (sar & TCLK_MASK_ARMADA38X) >> TCLK_SHIFT_ARMADA38X;
81 get_cpu_freq_armada38x(void)
85 static const uint32_t cpu_frequencies[] = {
93 sar = (uint32_t)get_sar_value_armada38x();
94 sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT;
95 if (sar >= nitems(cpu_frequencies))
98 hw_clockrate = cpu_frequencies[sar];
100 return (hw_clockrate * 1000 * 1000);
104 armada38x_win_set_iosync_barrier(void)
106 bus_space_handle_t vaddr_iowind;
109 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE,
110 MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind);
114 /* Set Sync Barrier flags for all Mbus internal units */
115 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, MV_SYNC_BARRIER_CTRL,
116 MV_SYNC_BARRIER_CTRL_ALL);
118 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0,
119 MV_CPU_SUBSYS_REGS_LEN, BUS_SPACE_BARRIER_WRITE);
120 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN);
126 armada38x_open_bootrom_win(void)
128 bus_space_handle_t vaddr_iowind;
132 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE,
133 MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind);
137 val = (MV_BOOTROM_WIN_SIZE & IO_WIN_SIZE_MASK) << IO_WIN_SIZE_SHIFT;
138 val |= (MBUS_BOOTROM_ATTR & IO_WIN_ATTR_MASK) << IO_WIN_ATTR_SHIFT;
139 val |= (MBUS_BOOTROM_TGT_ID & IO_WIN_TGT_MASK) << IO_WIN_TGT_SHIFT;
140 /* Enable window and Sync Barrier */
141 val |= (0x1 & IO_WIN_SYNC_MASK) << IO_WIN_SYNC_SHIFT;
142 val |= (0x1 & IO_WIN_ENA_MASK) << IO_WIN_ENA_SHIFT;
144 /* Configure IO Window Control Register */
145 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_CTRL_OFFSET,
147 /* Configure IO Window Base Register */
148 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_BASE_OFFSET,
149 MV_BOOTROM_MEM_ADDR);
151 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_CPU_SUBSYS_REGS_LEN,
152 BUS_SPACE_BARRIER_WRITE);
153 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN);
159 armada38x_mbus_optimization(void)
161 bus_space_handle_t vaddr_iowind;
164 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_CTRL_BASE,
165 MV_MBUS_CTRL_REGS_LEN, 0, &vaddr_iowind);
170 * MBUS Units Priority Control Register - Prioritize XOR,
171 * PCIe and GbEs (ID=4,6,3,7,8) DRAM access
172 * GbE is High and others are Medium.
174 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0, 0x19180);
177 * Fabric Units Priority Control Register -
178 * Prioritize CPUs requests.
180 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x4, 0x3000A);
183 * MBUS Units Prefetch Control Register -
184 * Pre-fetch enable for all IO masters.
186 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x8, 0xFFFF);
189 * Fabric Units Prefetch Control Register -
190 * Enable the CPUs Instruction and Data prefetch.
192 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0xc, 0x303);
194 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_MBUS_CTRL_REGS_LEN,
195 BUS_SPACE_BARRIER_WRITE);
197 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_MBUS_CTRL_REGS_LEN);
203 armada38x_scu_enable(void)
205 bus_space_handle_t vaddr_scu;
209 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE,
210 MV_SCU_REGS_LEN, 0, &vaddr_scu);
215 val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CTRL);
216 if (!(val & MV_SCU_ENABLE)) {
217 /* Enable SCU Speculative linefills to L2 */
218 val |= MV_SCU_SL_L2_ENABLE;
220 bus_space_write_4(fdtbus_bs_tag, vaddr_scu, 0,
221 val | MV_SCU_ENABLE);
224 bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN);