2 * Copyright (c) 2015 Semihalf.
3 * Copyright (c) 2015 Stormshield.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
35 #include <machine/smp.h>
36 #include <machine/fdt.h>
37 #include <machine/intr.h>
38 #include <machine/platformvar.h>
40 #include <dev/ofw/ofw_bus.h>
41 #include <dev/ofw/ofw_bus_subr.h>
43 #include <arm/mv/mvreg.h>
47 static int cpu_reset_deassert(void);
48 void mv_a38x_platform_mp_setmaxid(platform_t plate);
49 void mv_a38x_platform_mp_start_ap(platform_t plate);
52 cpu_reset_deassert(void)
54 bus_space_handle_t vaddr;
58 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_CPU_RESET_BASE,
59 MV_CPU_RESET_REGS_LEN, 0, &vaddr);
63 /* CPU1 is held at reset by default - clear assert bit to release it */
64 reg = bus_space_read_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1));
65 reg &= ~CPU_RESET_ASSERT;
67 bus_space_write_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1), reg);
69 bus_space_unmap(fdtbus_bs_tag, vaddr, MV_CPU_RESET_REGS_LEN);
75 platform_cnt_cpus(void)
77 bus_space_handle_t vaddr_scu;
78 phandle_t cpus_node, child;
80 int fdt_cpu_count = 0;
81 int reg_cpu_count = 0;
85 cpus_node = OF_finddevice("/cpus");
86 if (cpus_node == -1) {
87 /* Default is one core */
92 /* Get number of 'cpu' nodes from FDT */
93 for (child = OF_child(cpus_node); child != 0; child = OF_peer(child)) {
94 /* Check if child is a CPU */
95 memset(device_type, 0, sizeof(device_type));
96 rv = OF_getprop(child, "device_type", device_type,
97 sizeof(device_type) - 1);
100 if (strcmp(device_type, "cpu") != 0)
106 /* Get number of CPU cores from SCU register to cross-check with FDT */
107 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE,
108 MV_SCU_REGS_LEN, 0, &vaddr_scu);
110 /* Default is one core */
115 val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CONFIG);
116 bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN);
117 reg_cpu_count = (val & SCU_CFG_REG_NCPU_MASK) + 1;
119 /* Set mp_ncpus to number of cpus in FDT unless SOC contains only one */
120 mp_ncpus = min(reg_cpu_count, fdt_cpu_count);
121 /* mp_ncpus must be at least 1 */
122 mp_ncpus = max(1, mp_ncpus);
128 mv_a38x_platform_mp_setmaxid(platform_t plate)
131 /* Armada38x family supports maximum 2 cores */
132 mp_ncpus = platform_cnt_cpus();
133 mp_maxid = mp_ncpus - 1;
137 mv_a38x_platform_mp_start_ap(platform_t plate)
141 /* Write secondary entry address to PMSU register */
142 rv = pmsu_boot_secondary_cpu();
146 /* Release CPU1 from reset */
147 cpu_reset_deassert();