2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Semihalf.
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8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
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14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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28 * From: FreeBSD: src/sys/arm/mv/kirkwood/sheevaplug.c,v 1.2 2010/06/13 13:28:53
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <machine/bus.h>
39 #include <machine/armreg.h>
41 #include <arm/mv/mvwin.h>
42 #include <arm/mv/mvreg.h>
43 #include <arm/mv/mvvar.h>
45 #include <dev/ofw/openfirm.h>
47 #include <machine/fdt.h>
49 #define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) | \
51 #define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) | \
54 static uint32_t count_l2clk(void);
55 void armadaxp_l2_init(void);
56 void armadaxp_init_coher_fabric(void);
57 int platform_get_ncpus(void);
58 static uint64_t get_sar_value_armadaxp(void);
60 #define ARMADAXP_L2_BASE (MV_BASE + 0x8000)
61 #define ARMADAXP_L2_CTRL 0x100
62 #define L2_ENABLE (1 << 0)
63 #define ARMADAXP_L2_AUX_CTRL 0x104
64 #define L2_WBWT_MODE_MASK (3 << 0)
65 #define L2_WBWT_MODE_PAGE 0
66 #define L2_WBWT_MODE_WB 1
67 #define L2_WBWT_MODE_WT 2
68 #define L2_REP_STRAT_MASK (3 << 27)
69 #define L2_REP_STRAT_LSFR (1 << 27)
70 #define L2_REP_STRAT_SEMIPLRU (3 << 27)
72 #define ARMADAXP_L2_CNTR_CTRL 0x200
73 #define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc)
74 #define ARMADAXP_L2_CNTR2_VAL_LOW (0x208 + (x) * 0xc)
75 #define ARMADAXP_L2_CNTR2_VAL_HI (0x20c + (x) * 0xc)
77 #define ARMADAXP_L2_INT_CAUSE 0x220
79 #define ARMADAXP_L2_SYNC_BARRIER 0x700
80 #define ARMADAXP_L2_INV_WAY 0x778
81 #define ARMADAXP_L2_CLEAN_WAY 0x7BC
82 #define ARMADAXP_L2_FLUSH_PHYS 0x7F0
83 #define ARMADAXP_L2_FLUSH_WAY 0x7FC
85 #define MV_COHERENCY_FABRIC_BASE (MV_MBUS_BRIDGE_BASE + 0x200)
86 #define COHER_FABRIC_CTRL 0x00
87 #define COHER_FABRIC_CONF 0x04
88 #define COHER_FABRIC_CFU 0x28
89 #define COHER_FABRIC_CIB_CTRL 0x80
91 struct vco_freq_ratio {
92 uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */
93 uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */
94 uint8_t vco_hcl; /* VCO to HCLK(DDR controller) clock ratio */
95 uint8_t vco_ddr; /* VCO to DR(DDR memory) clock ratio */
98 static struct vco_freq_ratio freq_conf_table[] = {
99 /*00*/ { 1, 1, 4, 2 },
100 /*01*/ { 1, 2, 2, 2 },
101 /*02*/ { 2, 2, 6, 3 },
102 /*03*/ { 2, 2, 3, 3 },
103 /*04*/ { 1, 2, 3, 3 },
104 /*05*/ { 1, 2, 4, 2 },
105 /*06*/ { 1, 1, 2, 2 },
106 /*07*/ { 2, 3, 6, 6 },
107 /*08*/ { 2, 3, 5, 5 },
108 /*09*/ { 1, 2, 6, 3 },
109 /*10*/ { 2, 4, 10, 5 },
110 /*11*/ { 1, 3, 6, 6 },
111 /*12*/ { 1, 2, 5, 5 },
112 /*13*/ { 1, 3, 6, 3 },
113 /*14*/ { 1, 2, 5, 5 },
114 /*15*/ { 2, 2, 5, 5 },
115 /*16*/ { 1, 1, 3, 3 },
116 /*17*/ { 2, 5, 10, 10 },
117 /*18*/ { 1, 3, 8, 4 },
118 /*19*/ { 1, 1, 2, 1 },
119 /*20*/ { 2, 3, 6, 3 },
120 /*21*/ { 1, 2, 8, 4 },
121 /*22*/ { 2, 5, 10, 5 }
124 static uint16_t cpu_clock_table[] = {
125 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600,
129 get_sar_value_armadaxp(void)
131 uint32_t sar_low, sar_high;
133 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
135 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
137 return (((uint64_t)sar_high << 32) | sar_low);
141 get_tclk_armadaxp(void)
145 cputype = cpu_ident();
146 cputype &= CPU_ID_CPU_MASK;
148 if (cputype == CPU_ID_MV88SV584X_V7)
149 return (TCLK_250MHZ);
151 return (TCLK_200MHZ);
155 get_cpu_freq_armadaxp(void)
165 uint32_t freq_vco, freq_l2clk;
166 uint8_t sar_cpu_freq, sar_fab_freq, array_size;
168 /* Get value of the SAR register and process it */
169 sar_reg = get_sar_value_armadaxp();
170 sar_cpu_freq = CPU_FREQ_FIELD(sar_reg);
171 sar_fab_freq = FAB_FREQ_FIELD(sar_reg);
173 /* Check if CPU frequency field has correct value */
174 array_size = nitems(cpu_clock_table);
175 if (sar_cpu_freq >= array_size)
176 panic("Reserved value in cpu frequency configuration field: "
179 /* Check if fabric frequency field has correct value */
180 array_size = nitems(freq_conf_table);
181 if (sar_fab_freq >= array_size)
182 panic("Reserved value in fabric frequency configuration field: "
185 /* Get CPU clock frequency */
186 freq_vco = cpu_clock_table[sar_cpu_freq] *
187 freq_conf_table[sar_fab_freq].vco_cpu;
189 /* Get L2CLK clock frequency */
190 freq_l2clk = freq_vco / freq_conf_table[sar_fab_freq].vco_l2c;
192 /* Round L2CLK value to integer MHz */
193 if (((freq_vco % freq_conf_table[sar_fab_freq].vco_l2c) * 10 /
194 freq_conf_table[sar_fab_freq].vco_l2c) >= 5)
197 return (freq_l2clk * 1000000);
203 static uint32_t l2clk_freq = 0;
205 /* If get_l2clk is called first time get L2CLK value from register */
207 l2clk_freq = count_l2clk();
213 read_coher_fabric(uint32_t reg)
216 return (bus_space_read_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg));
220 write_coher_fabric(uint32_t reg, uint32_t val)
223 bus_space_write_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg, val);
227 platform_get_ncpus(void)
232 return ((read_coher_fabric(COHER_FABRIC_CONF) & 0xf) + 1);
237 armadaxp_init_coher_fabric(void)
239 uint32_t val, cpus, mask;
241 cpus = platform_get_ncpus();
242 mask = (1 << cpus) - 1;
243 val = read_coher_fabric(COHER_FABRIC_CTRL);
245 write_coher_fabric(COHER_FABRIC_CTRL, val);
247 val = read_coher_fabric(COHER_FABRIC_CONF);
250 write_coher_fabric(COHER_FABRIC_CONF, val);
253 #define ALL_WAYS 0xffffffff
255 /* L2 cache configuration registers */
257 read_l2_cache(uint32_t reg)
260 return (bus_space_read_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg));
264 write_l2_cache(uint32_t reg, uint32_t val)
267 bus_space_write_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg, val);
271 armadaxp_l2_idcache_inv_all(void)
273 write_l2_cache(ARMADAXP_L2_INV_WAY, ALL_WAYS);
277 armadaxp_l2_init(void)
282 reg = read_l2_cache(ARMADAXP_L2_AUX_CTRL);
283 reg &= ~(L2_WBWT_MODE_MASK);
284 reg &= ~(L2_REP_STRAT_MASK);
285 reg |= L2_REP_STRAT_SEMIPLRU;
286 reg |= L2_WBWT_MODE_WT;
287 write_l2_cache(ARMADAXP_L2_AUX_CTRL, reg);
289 /* Invalidate l2 cache */
290 armadaxp_l2_idcache_inv_all();
292 /* Clear pending L2 interrupts */
293 write_l2_cache(ARMADAXP_L2_INT_CAUSE, 0x1ff);
295 /* Enable l2 cache */
296 reg = read_l2_cache(ARMADAXP_L2_CTRL);
297 write_l2_cache(ARMADAXP_L2_CTRL, reg | L2_ENABLE);
301 * Configure and enable counter
303 write_l2_cache(ARMADAXP_L2_CNTR_CONF(0), 0xf0000 | (4 << 2));
304 write_l2_cache(ARMADAXP_L2_CNTR_CONF(1), 0xf0000 | (2 << 2));
305 write_l2_cache(ARMADAXP_L2_CNTR_CTRL, 0x303);
308 * Enable Cache maintenance operation propagation in coherency fabric
309 * Change point of coherency and point of unification to DRAM.
311 reg = read_coher_fabric(COHER_FABRIC_CFU);
312 reg |= (1 << 17) | (1 << 18);
313 write_coher_fabric(COHER_FABRIC_CFU, reg);
315 /* Coherent IO Bridge initialization */
316 reg = read_coher_fabric(COHER_FABRIC_CIB_CTRL);
319 write_coher_fabric(COHER_FABRIC_CIB_CTRL, reg);