2 * Copyright (c) 2011 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
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12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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26 * From: FreeBSD: src/sys/arm/mv/kirkwood/sheevaplug.c,v 1.2 2010/06/13 13:28:53
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <machine/bus.h>
37 #include <machine/armreg.h>
39 #include <arm/mv/mvwin.h>
40 #include <arm/mv/mvreg.h>
41 #include <arm/mv/mvvar.h>
43 #include <dev/ofw/openfirm.h>
45 #include <machine/fdt.h>
47 #define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) | \
49 #define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) | \
52 static uint32_t count_l2clk(void);
53 void armadaxp_l2_init(void);
54 void armadaxp_init_coher_fabric(void);
55 int platform_get_ncpus(void);
57 #define ARMADAXP_L2_BASE (MV_BASE + 0x8000)
58 #define ARMADAXP_L2_CTRL 0x100
59 #define L2_ENABLE (1 << 0)
60 #define ARMADAXP_L2_AUX_CTRL 0x104
61 #define L2_WBWT_MODE_MASK (3 << 0)
62 #define L2_WBWT_MODE_PAGE 0
63 #define L2_WBWT_MODE_WB 1
64 #define L2_WBWT_MODE_WT 2
65 #define L2_REP_STRAT_MASK (3 << 27)
66 #define L2_REP_STRAT_LSFR (1 << 27)
67 #define L2_REP_STRAT_SEMIPLRU (3 << 27)
69 #define ARMADAXP_L2_CNTR_CTRL 0x200
70 #define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc)
71 #define ARMADAXP_L2_CNTR2_VAL_LOW (0x208 + (x) * 0xc)
72 #define ARMADAXP_L2_CNTR2_VAL_HI (0x20c + (x) * 0xc)
74 #define ARMADAXP_L2_INT_CAUSE 0x220
76 #define ARMADAXP_L2_SYNC_BARRIER 0x700
77 #define ARMADAXP_L2_INV_WAY 0x778
78 #define ARMADAXP_L2_CLEAN_WAY 0x7BC
79 #define ARMADAXP_L2_FLUSH_PHYS 0x7F0
80 #define ARMADAXP_L2_FLUSH_WAY 0x7FC
82 #define MV_COHERENCY_FABRIC_BASE (MV_MBUS_BRIDGE_BASE + 0x200)
83 #define COHER_FABRIC_CTRL 0x00
84 #define COHER_FABRIC_CONF 0x04
85 #define COHER_FABRIC_CFU 0x28
86 #define COHER_FABRIC_CIB_CTRL 0x80
88 struct vco_freq_ratio {
89 uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */
90 uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */
91 uint8_t vco_hcl; /* VCO to HCLK(DDR controller) clock ratio */
92 uint8_t vco_ddr; /* VCO to DR(DDR memory) clock ratio */
95 static struct vco_freq_ratio freq_conf_table[] = {
96 /*00*/ { 1, 1, 4, 2 },
97 /*01*/ { 1, 2, 2, 2 },
98 /*02*/ { 2, 2, 6, 3 },
99 /*03*/ { 2, 2, 3, 3 },
100 /*04*/ { 1, 2, 3, 3 },
101 /*05*/ { 1, 2, 4, 2 },
102 /*06*/ { 1, 1, 2, 2 },
103 /*07*/ { 2, 3, 6, 6 },
104 /*08*/ { 2, 3, 5, 5 },
105 /*09*/ { 1, 2, 6, 3 },
106 /*10*/ { 2, 4, 10, 5 },
107 /*11*/ { 1, 3, 6, 6 },
108 /*12*/ { 1, 2, 5, 5 },
109 /*13*/ { 1, 3, 6, 3 },
110 /*14*/ { 1, 2, 5, 5 },
111 /*15*/ { 2, 2, 5, 5 },
112 /*16*/ { 1, 1, 3, 3 },
113 /*17*/ { 2, 5, 10, 10 },
114 /*18*/ { 1, 3, 8, 4 },
115 /*19*/ { 1, 1, 2, 1 },
116 /*20*/ { 2, 3, 6, 3 },
117 /*21*/ { 1, 2, 8, 4 },
118 /*22*/ { 2, 5, 10, 5 }
121 static uint16_t cpu_clock_table[] = {
122 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600,
130 cputype = cpu_ident();
131 cputype &= CPU_ID_CPU_MASK;
133 if (cputype == CPU_ID_MV88SV584X_V7)
134 return (TCLK_250MHZ);
136 return (TCLK_200MHZ);
150 uint32_t freq_vco, freq_l2clk;
151 uint8_t sar_cpu_freq, sar_fab_freq, array_size;
153 /* Get value of the SAR register and process it */
154 sar_reg = get_sar_value();
155 sar_cpu_freq = CPU_FREQ_FIELD(sar_reg);
156 sar_fab_freq = FAB_FREQ_FIELD(sar_reg);
158 /* Check if CPU frequency field has correct value */
159 array_size = nitems(cpu_clock_table);
160 if (sar_cpu_freq >= array_size)
161 panic("Reserved value in cpu frequency configuration field: "
164 /* Check if fabric frequency field has correct value */
165 array_size = nitems(freq_conf_table);
166 if (sar_fab_freq >= array_size)
167 panic("Reserved value in fabric frequency configuration field: "
170 /* Get CPU clock frequency */
171 freq_vco = cpu_clock_table[sar_cpu_freq] *
172 freq_conf_table[sar_fab_freq].vco_cpu;
174 /* Get L2CLK clock frequency */
175 freq_l2clk = freq_vco / freq_conf_table[sar_fab_freq].vco_l2c;
177 /* Round L2CLK value to integer MHz */
178 if (((freq_vco % freq_conf_table[sar_fab_freq].vco_l2c) * 10 /
179 freq_conf_table[sar_fab_freq].vco_l2c) >= 5)
182 return (freq_l2clk * 1000000);
188 static uint32_t l2clk_freq = 0;
190 /* If get_l2clk is called first time get L2CLK value from register */
192 l2clk_freq = count_l2clk();
198 read_coher_fabric(uint32_t reg)
201 return (bus_space_read_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg));
205 write_coher_fabric(uint32_t reg, uint32_t val)
208 bus_space_write_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg, val);
212 platform_get_ncpus(void)
217 return ((read_coher_fabric(COHER_FABRIC_CONF) & 0xf) + 1);
222 armadaxp_init_coher_fabric(void)
224 uint32_t val, cpus, mask;
226 cpus = platform_get_ncpus();
227 mask = (1 << cpus) - 1;
228 val = read_coher_fabric(COHER_FABRIC_CTRL);
230 write_coher_fabric(COHER_FABRIC_CTRL, val);
232 val = read_coher_fabric(COHER_FABRIC_CONF);
235 write_coher_fabric(COHER_FABRIC_CONF, val);
238 #define ALL_WAYS 0xffffffff
240 /* L2 cache configuration registers */
242 read_l2_cache(uint32_t reg)
245 return (bus_space_read_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg));
249 write_l2_cache(uint32_t reg, uint32_t val)
252 bus_space_write_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg, val);
256 armadaxp_l2_idcache_inv_all(void)
258 write_l2_cache(ARMADAXP_L2_INV_WAY, ALL_WAYS);
262 armadaxp_l2_init(void)
267 reg = read_l2_cache(ARMADAXP_L2_AUX_CTRL);
268 reg &= ~(L2_WBWT_MODE_MASK);
269 reg &= ~(L2_REP_STRAT_MASK);
270 reg |= L2_REP_STRAT_SEMIPLRU;
271 reg |= L2_WBWT_MODE_WT;
272 write_l2_cache(ARMADAXP_L2_AUX_CTRL, reg);
274 /* Invalidate l2 cache */
275 armadaxp_l2_idcache_inv_all();
277 /* Clear pending L2 interrupts */
278 write_l2_cache(ARMADAXP_L2_INT_CAUSE, 0x1ff);
280 /* Enable l2 cache */
281 reg = read_l2_cache(ARMADAXP_L2_CTRL);
282 write_l2_cache(ARMADAXP_L2_CTRL, reg | L2_ENABLE);
286 * Configure and enable counter
288 write_l2_cache(ARMADAXP_L2_CNTR_CONF(0), 0xf0000 | (4 << 2));
289 write_l2_cache(ARMADAXP_L2_CNTR_CONF(1), 0xf0000 | (2 << 2));
290 write_l2_cache(ARMADAXP_L2_CNTR_CTRL, 0x303);
293 * Enable Cache maintenance operation propagation in coherency fabric
294 * Change point of coherency and point of unification to DRAM.
296 reg = read_coher_fabric(COHER_FABRIC_CFU);
297 reg |= (1 << 17) | (1 << 18);
298 write_coher_fabric(COHER_FABRIC_CFU, reg);
300 /* Coherent IO Bridge initialization */
301 reg = read_coher_fabric(COHER_FABRIC_CIB_CTRL);
304 write_coher_fabric(COHER_FABRIC_CIB_CTRL, reg);