sys/arm/mv/armadaxp/armadaxp_mp.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2011 Semihalf.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #include <sys/param.h>
  32 #include <sys/systm.h>
  33 #include <sys/bus.h>
  34 #include <sys/lock.h>
  35 #include <sys/mutex.h>
  36 #include <sys/smp.h>
  37
  38 #include <vm/vm.h>
  39 #include <vm/vm_kern.h>
  40 #include <vm/vm_extern.h>
  41 #include <vm/pmap.h>
  42
  43 #include <dev/fdt/fdt_common.h>
  44
  45 #include <machine/cpu.h>
  46 #include <machine/smp.h>
  47 #include <machine/fdt.h>
  48 #include <machine/armreg.h>
  49
  50 #include <arm/mv/mvwin.h>
  51
  52 #define MV_AXP_CPU_DIVCLK_BASE          (MV_BASE + 0x18700)
  53 #define CPU_DIVCLK_CTRL0                0x00
  54 #define CPU_DIVCLK_CTRL2_RATIO_FULL0    0x08
  55 #define CPU_DIVCLK_CTRL2_RATIO_FULL1    0x0c
  56 #define CPU_DIVCLK_MASK(x)              (~(0xff << (8 * (x))))
  57
  58 #define CPU_PMU(x)                      (MV_BASE + 0x22100 + (0x100 * (x)))
  59 #define CPU_PMU_BOOT                    0x24
  60
  61 #define MP                              (MV_BASE + 0x20800)
  62 #define MP_SW_RESET(x)                  ((x) * 8)
  63
  64 #define CPU_RESUME_CONTROL              (0x20988)
  65
  66 void armadaxp_init_coher_fabric(void);
  67 int platform_get_ncpus(void);
  68
  69 /* Coherency Fabric registers */
  70 static uint32_t
  71 read_cpu_clkdiv(uint32_t reg)
  72 {
  73
  74         return (bus_space_read_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg));
  75 }
  76
  77 static void
  78 write_cpu_clkdiv(uint32_t reg, uint32_t val)
  79 {
  80
  81         bus_space_write_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg, val);
  82 }
  83
  84 void
  85 platform_mp_setmaxid(void)
  86 {
  87
  88         mp_ncpus = platform_get_ncpus();
  89         mp_maxid = mp_ncpus - 1;
  90 }
  91
  92 void mptramp(void);
  93 void mptramp_end(void);
  94 extern vm_offset_t mptramp_pmu_boot;
  95
  96 void
  97 platform_mp_start_ap(void)
  98 {
  99         uint32_t reg, *src, *dst, cpu_num, div_val, cputype;
 100         vm_offset_t pmu_boot_off;
 101         /*
 102          * Initialization procedure depends on core revision,
 103          * in this step CHIP ID is checked to choose proper procedure
 104          */
 105         cputype = cpu_ident();
 106         cputype &= CPU_ID_CPU_MASK;
 107
 108         /*
 109          * Set the PA of CPU0 Boot Address Redirect register used in
 110          * mptramp according to the actual SoC registers' base address.
 111          */
 112         pmu_boot_off = (CPU_PMU(0) - MV_BASE) + CPU_PMU_BOOT;
 113         mptramp_pmu_boot = fdt_immr_pa + pmu_boot_off;
 114         dst = pmap_mapdev(0xffff0000, PAGE_SIZE);
 115         for (src = (uint32_t *)mptramp; src < (uint32_t *)mptramp_end;
 116             src++, dst++) {
 117                 *dst = *src;
 118         }
 119         pmap_unmapdev((vm_offset_t)dst, PAGE_SIZE);
 120         if (cputype == CPU_ID_MV88SV584X_V7) {
 121                 /* Core rev A0 */
 122                 div_val = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
 123                 div_val &= 0x3f;
 124
 125                 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) {
 126                         reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
 127                         reg &= CPU_DIVCLK_MASK(cpu_num);
 128                         reg |= div_val << (cpu_num * 8);
 129                         write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);
 130                 }
 131         } else {
 132                 /* Core rev Z1 */
 133                 div_val = 0x01;
 134
 135                 if (mp_ncpus > 1) {
 136                         reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0);
 137                         reg &= CPU_DIVCLK_MASK(3);
 138                         reg |= div_val << 24;
 139                         write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg);
 140                 }
 141
 142                 for (cpu_num = 2; cpu_num < mp_ncpus; cpu_num++ ) {
 143                         reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
 144                         reg &= CPU_DIVCLK_MASK(cpu_num);
 145                         reg |= div_val << (cpu_num * 8);
 146                         write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);
 147                 }
 148         }
 149
 150         reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);
 151         reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21;
 152         write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
 153         reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);
 154         reg |= 0x01000000;
 155         write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
 156
 157         DELAY(100);
 158         reg &= ~(0xf << 21);
 159         write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
 160         DELAY(100);
 161
 162         bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0);
 163
 164         for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
 165                 bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT,
 166                     pmap_kextract((vm_offset_t)mpentry));
 167
 168         dcache_wbinv_poc_all();
 169
 170         for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
 171                 bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0);
 172
 173         /* XXX: Temporary workaround for hangup after releasing AP's */
 174         wmb();
 175         DELAY(10);
 176
 177         armadaxp_init_coher_fabric();
 178 }