2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 Benno Rice.
5 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
6 * Copyright (c) 2017 Semihalf.
9 * Adapted and extended for Marvell SoCs by Semihalf.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/interrupt.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/mutex.h>
47 #include <sys/queue.h>
48 #include <sys/timetc.h>
49 #include <sys/callout.h>
51 #include <machine/bus.h>
52 #include <machine/intr.h>
54 #include <dev/gpio/gpiobusvar.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
58 #include <arm/mv/mvvar.h>
59 #include <arm/mv/mvreg.h>
64 #define GPIO_MAX_INTR_COUNT 8
65 #define GPIO_PINS_PER_REG 32
66 #define GPIO_GENERIC_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
67 GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \
68 GPIO_PIN_TRISTATE | GPIO_PIN_PULLUP | \
69 GPIO_PIN_PULLDOWN | GPIO_PIN_INVIN | \
72 #define DEBOUNCE_CHECK_MS 1
73 #define DEBOUNCE_LO_HI_MS 2
74 #define DEBOUNCE_HI_LO_MS 2
75 #define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS)
77 struct mv_gpio_softc {
80 struct resource * mem_res;
82 struct resource * irq_res[GPIO_MAX_INTR_COUNT];
83 int irq_rid[GPIO_MAX_INTR_COUNT];
84 struct intr_event * gpio_events[MV_GPIO_MAX_NPINS];
85 void *ih_cookie[GPIO_MAX_INTR_COUNT];
87 bus_space_handle_t bsh;
90 uint8_t pin_num; /* number of GPIO pins */
91 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */
92 struct gpio_pin gpio_setup[MV_GPIO_MAX_NPINS];
94 /* Used for debouncing. */
95 uint32_t debounced_state_lo;
96 uint32_t debounced_state_hi;
97 struct callout **debounce_callouts;
98 int *debounce_counters;
101 struct mv_gpio_pindev {
106 static int mv_gpio_probe(device_t);
107 static int mv_gpio_attach(device_t);
108 static int mv_gpio_intr(device_t, void *);
110 static void mv_gpio_double_edge_init(device_t, int);
112 static int mv_gpio_debounce_setup(device_t, int);
113 static int mv_gpio_debounce_prepare(device_t, int);
114 static int mv_gpio_debounce_init(device_t, int);
115 static void mv_gpio_debounce_start(device_t, int);
116 static void mv_gpio_debounce(void *);
117 static void mv_gpio_debounced_state_set(device_t, int, uint8_t);
118 static uint32_t mv_gpio_debounced_state_get(device_t, int);
120 static void mv_gpio_exec_intr_handlers(device_t, uint32_t, int);
121 static void mv_gpio_intr_handler(device_t, int);
122 static uint32_t mv_gpio_reg_read(device_t, uint32_t);
123 static void mv_gpio_reg_write(device_t, uint32_t, uint32_t);
124 static void mv_gpio_reg_set(device_t, uint32_t, uint32_t);
125 static void mv_gpio_reg_clear(device_t, uint32_t, uint32_t);
127 static void mv_gpio_blink(device_t, uint32_t, uint8_t);
128 static void mv_gpio_polarity(device_t, uint32_t, uint8_t, uint8_t);
129 static void mv_gpio_level(device_t, uint32_t, uint8_t);
130 static void mv_gpio_edge(device_t, uint32_t, uint8_t);
131 static void mv_gpio_out_en(device_t, uint32_t, uint8_t);
132 static void mv_gpio_int_ack(struct mv_gpio_pindev *);
133 static void mv_gpio_value_set(device_t, uint32_t, uint8_t);
134 static uint32_t mv_gpio_value_get(device_t, uint32_t, uint8_t);
136 static void mv_gpio_intr_mask(struct mv_gpio_pindev *);
137 static void mv_gpio_intr_unmask(struct mv_gpio_pindev *);
139 void mv_gpio_finish_intrhandler(struct mv_gpio_pindev *);
140 int mv_gpio_setup_intrhandler(device_t, const char *,
141 driver_filter_t *, void (*)(void *), void *,
143 int mv_gpio_configure(device_t, uint32_t, uint32_t, uint32_t);
144 void mv_gpio_out(device_t, uint32_t, uint8_t, uint8_t);
145 uint8_t mv_gpio_in(device_t, uint32_t);
150 static device_t mv_gpio_get_bus(device_t);
151 static int mv_gpio_pin_max(device_t, int *);
152 static int mv_gpio_pin_getcaps(device_t, uint32_t, uint32_t *);
153 static int mv_gpio_pin_getflags(device_t, uint32_t, uint32_t *);
154 static int mv_gpio_pin_getname(device_t, uint32_t, char *);
155 static int mv_gpio_pin_setflags(device_t, uint32_t, uint32_t);
156 static int mv_gpio_pin_set(device_t, uint32_t, unsigned int);
157 static int mv_gpio_pin_get(device_t, uint32_t, unsigned int *);
158 static int mv_gpio_pin_toggle(device_t, uint32_t);
159 static int mv_gpio_map_gpios(device_t, phandle_t, phandle_t,
160 int, pcell_t *, uint32_t *, uint32_t *);
162 #define MV_GPIO_LOCK() mtx_lock_spin(&sc->mutex)
163 #define MV_GPIO_UNLOCK() mtx_unlock_spin(&sc->mutex)
164 #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&sc->mutex, MA_OWNED)
166 static device_method_t mv_gpio_methods[] = {
167 DEVMETHOD(device_probe, mv_gpio_probe),
168 DEVMETHOD(device_attach, mv_gpio_attach),
171 DEVMETHOD(gpio_get_bus, mv_gpio_get_bus),
172 DEVMETHOD(gpio_pin_max, mv_gpio_pin_max),
173 DEVMETHOD(gpio_pin_getname, mv_gpio_pin_getname),
174 DEVMETHOD(gpio_pin_getflags, mv_gpio_pin_getflags),
175 DEVMETHOD(gpio_pin_getcaps, mv_gpio_pin_getcaps),
176 DEVMETHOD(gpio_pin_setflags, mv_gpio_pin_setflags),
177 DEVMETHOD(gpio_pin_get, mv_gpio_pin_get),
178 DEVMETHOD(gpio_pin_set, mv_gpio_pin_set),
179 DEVMETHOD(gpio_pin_toggle, mv_gpio_pin_toggle),
180 DEVMETHOD(gpio_map_gpios, mv_gpio_map_gpios),
185 static driver_t mv_gpio_driver = {
188 sizeof(struct mv_gpio_softc),
191 static devclass_t mv_gpio_devclass;
193 EARLY_DRIVER_MODULE(mv_gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0,
194 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST);
196 struct ofw_compat_data compat_data[] = {
198 { "marvell,orion-gpio", 1 },
203 mv_gpio_probe(device_t dev)
205 if (!ofw_bus_status_okay(dev))
208 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
211 device_set_desc(dev, "Marvell Integrated GPIO Controller");
216 mv_gpio_setup_interrupts(struct mv_gpio_softc *sc, phandle_t node)
222 /* Find root interrupt controller */
223 iparent = ofw_bus_find_iparent(node);
225 device_printf(sc->dev, "No interrupt-parrent found. "
229 /* While at parent - store interrupt cells prop */
230 if (OF_searchencprop(OF_node_from_xref(iparent),
231 "#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) {
232 device_printf(sc->dev, "DTB: Missing #interrupt-cells "
233 "property in interrupt parent node\n");
238 size = OF_getproplen(node, "interrupts");
240 size = size / sizeof(pcell_t);
241 size = size / irq_cells;
243 device_printf(sc->dev, "%d IRQs available\n", sc->irq_num);
245 device_printf(sc->dev, "ERROR: no interrupts entry found!\n");
249 for (i = 0; i < sc->irq_num; i++) {
251 sc->irq_res[i] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
252 &sc->irq_rid[i], RF_ACTIVE);
253 if (!sc->irq_res[i]) {
254 mtx_destroy(&sc->mutex);
255 device_printf(sc->dev,
256 "could not allocate gpio%d interrupt\n", i+1);
261 device_printf(sc->dev, "Disable interrupts (offset = %x + EDGE(0x18)\n", sc->offset);
262 /* Disable all interrupts */
263 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_EDGE_MASK, 0);
264 device_printf(sc->dev, "Disable interrupts (offset = %x + LEV(0x1C))\n", sc->offset);
265 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_LEV_MASK, 0);
267 for (i = 0; i < sc->irq_num; i++) {
268 device_printf(sc->dev, "Setup intr %d\n", i);
269 if (bus_setup_intr(sc->dev, sc->irq_res[i],
271 (driver_filter_t *)mv_gpio_intr, NULL,
272 sc, &sc->ih_cookie[i]) != 0) {
273 mtx_destroy(&sc->mutex);
274 bus_release_resource(sc->dev, SYS_RES_IRQ,
275 sc->irq_rid[i], sc->irq_res[i]);
276 device_printf(sc->dev, "could not set up intr %d\n", i);
281 /* Clear interrupt status. */
282 device_printf(sc->dev, "Clear int status (offset = %x)\n", sc->offset);
283 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_CAUSE, 0);
285 sc->debounce_callouts = (struct callout **)malloc(sc->pin_num *
286 sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO);
287 if (sc->debounce_callouts == NULL)
290 sc->debounce_counters = (int *)malloc(sc->pin_num * sizeof(int),
292 if (sc->debounce_counters == NULL)
299 mv_gpio_attach(device_t dev)
302 struct mv_gpio_softc *sc;
306 sc = (struct mv_gpio_softc *)device_get_softc(dev);
310 node = ofw_bus_get_node(dev);
313 if (OF_getencprop(node, "pin-count", &pincnt, sizeof(pcell_t)) >= 0 ||
314 OF_getencprop(node, "ngpios", &pincnt, sizeof(pcell_t)) >= 0) {
315 sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS);
317 device_printf(dev, "%d pins available\n", sc->pin_num);
319 device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n");
323 if (OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset)) == -1)
326 /* Assign generic capabilities to every gpio pin */
327 for(i = 0; i < sc->pin_num; i++)
328 sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP;
330 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN);
333 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
334 RF_ACTIVE | RF_SHAREABLE );
337 mtx_destroy(&sc->mutex);
338 device_printf(dev, "could not allocate memory window\n");
342 sc->bst = rman_get_bustag(sc->mem_res);
343 sc->bsh = rman_get_bushandle(sc->mem_res);
345 rv = mv_gpio_setup_interrupts(sc, node);
349 sc->sc_busdev = gpiobus_attach_bus(dev);
350 if (sc->sc_busdev == NULL) {
351 mtx_destroy(&sc->mutex);
352 bus_release_resource(dev, SYS_RES_IRQ,
353 sc->irq_rid[i], sc->irq_res[i]);
361 mv_gpio_intr(device_t dev, void *arg)
363 uint32_t int_cause, gpio_val;
364 struct mv_gpio_softc *sc;
365 sc = (struct mv_gpio_softc *)device_get_softc(dev);
370 * According to documentation, edge sensitive interrupts are asserted
371 * when unmasked GPIO_INT_CAUSE register bits are set.
373 int_cause = mv_gpio_reg_read(dev, GPIO_INT_CAUSE);
374 int_cause &= mv_gpio_reg_read(dev, GPIO_INT_EDGE_MASK);
377 * Level sensitive interrupts are asserted when unmasked GPIO_DATA_IN
378 * register bits are set.
380 gpio_val = mv_gpio_reg_read(dev, GPIO_DATA_IN);
381 gpio_val &= mv_gpio_reg_read(dev, GPIO_INT_LEV_MASK);
383 mv_gpio_exec_intr_handlers(dev, int_cause | gpio_val, 0);
387 return (FILTER_HANDLED);
391 * GPIO interrupt handling
395 mv_gpio_finish_intrhandler(struct mv_gpio_pindev *s)
397 /* When we acheive full interrupt support
398 * This function will be opposite to
399 * mv_gpio_setup_intrhandler
402 /* Now it exists only to remind that
403 * there should be place to free mv_gpio_pindev
404 * allocated by mv_gpio_setup_intrhandler
410 mv_gpio_setup_intrhandler(device_t dev, const char *name, driver_filter_t *filt,
411 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep)
413 struct intr_event *event;
415 struct mv_gpio_pindev *s;
416 struct mv_gpio_softc *sc;
417 sc = (struct mv_gpio_softc *)device_get_softc(dev);
418 s = malloc(sizeof(struct mv_gpio_pindev), M_DEVBUF, M_NOWAIT | M_ZERO);
420 if (pin < 0 || pin >= sc->pin_num)
422 event = sc->gpio_events[pin];
425 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) {
426 error = mv_gpio_debounce_init(dev, pin);
431 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE)
432 mv_gpio_double_edge_init(dev, pin);
434 error = intr_event_create(&event, (void *)s, 0, pin,
435 (void (*)(void *))mv_gpio_intr_mask,
436 (void (*)(void *))mv_gpio_intr_unmask,
437 (void (*)(void *))mv_gpio_int_ack,
442 sc->gpio_events[pin] = event;
445 intr_event_add_handler(event, name, filt, hand, arg,
446 intr_priority(flags), flags, cookiep);
451 mv_gpio_intr_mask(struct mv_gpio_pindev *s)
453 struct mv_gpio_softc *sc;
454 sc = (struct mv_gpio_softc *)device_get_softc(s->dev);
456 if (s->pin >= sc->pin_num)
461 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE |
462 MV_GPIO_IN_IRQ_DOUBLE_EDGE))
463 mv_gpio_edge(s->dev, s->pin, 0);
465 mv_gpio_level(s->dev, s->pin, 0);
468 * The interrupt has to be acknowledged before scheduling an interrupt
469 * thread. This way we allow for interrupt source to trigger again
470 * (which can happen with shared IRQs e.g. PCI) while processing the
481 mv_gpio_intr_unmask(struct mv_gpio_pindev *s)
483 struct mv_gpio_softc *sc;
484 sc = (struct mv_gpio_softc *)device_get_softc(s->dev);
486 if (s->pin >= sc->pin_num)
491 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE |
492 MV_GPIO_IN_IRQ_DOUBLE_EDGE))
493 mv_gpio_edge(s->dev, s->pin, 1);
495 mv_gpio_level(s->dev, s->pin, 1);
503 mv_gpio_exec_intr_handlers(device_t dev, uint32_t status, int high)
506 struct mv_gpio_softc *sc;
507 sc = (struct mv_gpio_softc *)device_get_softc(dev);
509 MV_GPIO_ASSERT_LOCKED();
512 while (status != 0) {
514 pin = (high ? (i + GPIO_PINS_PER_REG) : i);
515 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE)
516 mv_gpio_debounce_start(dev, pin);
517 else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) {
518 mv_gpio_polarity(dev, pin, 0, 1);
519 mv_gpio_intr_handler(dev, pin);
521 mv_gpio_intr_handler(dev, pin);
529 mv_gpio_intr_handler(device_t dev, int pin)
532 struct intr_irqsrc isrc;
533 struct mv_gpio_softc *sc;
534 sc = (struct mv_gpio_softc *)device_get_softc(dev);
536 MV_GPIO_ASSERT_LOCKED();
539 isrc.isrc_filter = NULL;
541 isrc.isrc_event = sc->gpio_events[pin];
543 if (isrc.isrc_event == NULL ||
544 CK_SLIST_EMPTY(&isrc.isrc_event->ie_handlers))
547 intr_isrc_dispatch(&isrc, NULL);
552 mv_gpio_configure(device_t dev, uint32_t pin, uint32_t flags, uint32_t mask)
555 struct mv_gpio_softc *sc;
556 sc = (struct mv_gpio_softc *)device_get_softc(dev);
559 if (pin >= sc->pin_num)
562 /* check flags consistency */
563 if (((flags & mask) & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) ==
564 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
567 if (mask & MV_GPIO_IN_DEBOUNCE) {
568 if (sc->irq_num == 0)
570 error = mv_gpio_debounce_prepare(dev, pin);
577 if ((mask & flags) & GPIO_PIN_INPUT)
578 mv_gpio_out_en(dev, pin, 0);
579 if ((mask & flags) & GPIO_PIN_OUTPUT) {
580 if ((flags & mask) & GPIO_PIN_OPENDRAIN)
581 mv_gpio_value_set(dev, pin, 0);
583 mv_gpio_value_set(dev, pin, 1);
584 mv_gpio_out_en(dev, pin, 1);
587 if (mask & MV_GPIO_OUT_BLINK)
588 mv_gpio_blink(dev, pin, flags & MV_GPIO_OUT_BLINK);
589 if (mask & MV_GPIO_IN_POL_LOW)
590 mv_gpio_polarity(dev, pin, flags & MV_GPIO_IN_POL_LOW, 0);
591 if (mask & MV_GPIO_IN_DEBOUNCE) {
592 error = mv_gpio_debounce_setup(dev, pin);
599 sc->gpio_setup[pin].gp_flags &= ~(mask);
600 sc->gpio_setup[pin].gp_flags |= (flags & mask);
608 mv_gpio_double_edge_init(device_t dev, int pin)
611 struct mv_gpio_softc *sc;
612 sc = (struct mv_gpio_softc *)device_get_softc(dev);
614 MV_GPIO_ASSERT_LOCKED();
616 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
619 mv_gpio_polarity(dev, pin, 1, 0);
621 mv_gpio_polarity(dev, pin, 0, 0);
625 mv_gpio_debounce_setup(device_t dev, int pin)
628 struct mv_gpio_softc *sc;
630 sc = (struct mv_gpio_softc *)device_get_softc(dev);
632 MV_GPIO_ASSERT_LOCKED();
634 c = sc->debounce_callouts[pin];
638 if (callout_active(c))
639 callout_deactivate(c);
647 mv_gpio_debounce_prepare(device_t dev, int pin)
650 struct mv_gpio_softc *sc;
652 sc = (struct mv_gpio_softc *)device_get_softc(dev);
654 c = sc->debounce_callouts[pin];
656 c = (struct callout *)malloc(sizeof(struct callout),
658 sc->debounce_callouts[pin] = c;
668 mv_gpio_debounce_init(device_t dev, int pin)
672 struct mv_gpio_softc *sc;
674 sc = (struct mv_gpio_softc *)device_get_softc(dev);
676 MV_GPIO_ASSERT_LOCKED();
678 cnt = &sc->debounce_counters[pin];
679 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
681 mv_gpio_polarity(dev, pin, 1, 0);
682 *cnt = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS;
684 mv_gpio_polarity(dev, pin, 0, 0);
685 *cnt = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS;
688 mv_gpio_debounced_state_set(dev, pin, raw_read);
694 mv_gpio_debounce_start(device_t dev, int pin)
697 struct mv_gpio_pindev s = {dev, pin};
698 struct mv_gpio_pindev *sd;
699 struct mv_gpio_softc *sc;
700 sc = (struct mv_gpio_softc *)device_get_softc(dev);
702 MV_GPIO_ASSERT_LOCKED();
704 c = sc->debounce_callouts[pin];
710 if (callout_pending(c) || callout_active(c)) {
715 sd = (struct mv_gpio_pindev *)malloc(sizeof(struct mv_gpio_pindev),
724 callout_reset(c, DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, sd);
728 mv_gpio_debounce(void *arg)
730 uint8_t raw_read, last_state;
733 int *debounce_counter;
734 struct mv_gpio_softc *sc;
735 struct mv_gpio_pindev *s;
737 s = (struct mv_gpio_pindev *)arg;
740 sc = (struct mv_gpio_softc *)device_get_softc(dev);
744 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
745 last_state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0);
746 debounce_counter = &sc->debounce_counters[pin];
748 if (raw_read == last_state) {
750 *debounce_counter = DEBOUNCE_HI_LO_MS /
753 *debounce_counter = DEBOUNCE_LO_HI_MS /
756 callout_reset(sc->debounce_callouts[pin],
757 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg);
759 *debounce_counter = *debounce_counter - 1;
760 if (*debounce_counter != 0)
761 callout_reset(sc->debounce_callouts[pin],
762 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg);
764 mv_gpio_debounced_state_set(dev, pin, raw_read);
767 *debounce_counter = DEBOUNCE_HI_LO_MS /
770 *debounce_counter = DEBOUNCE_LO_HI_MS /
773 if (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) &&
775 (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) == 0) &&
777 (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE))
778 mv_gpio_intr_handler(dev, pin);
780 /* Toggle polarity for next edge. */
781 mv_gpio_polarity(dev, pin, 0, 1);
784 callout_deactivate(sc->debounce_callouts[pin]);
792 mv_gpio_debounced_state_set(device_t dev, int pin, uint8_t new_state)
795 struct mv_gpio_softc *sc;
796 sc = (struct mv_gpio_softc *)device_get_softc(dev);
798 MV_GPIO_ASSERT_LOCKED();
800 if (pin >= GPIO_PINS_PER_REG) {
801 old_state = &sc->debounced_state_hi;
802 pin -= GPIO_PINS_PER_REG;
804 old_state = &sc->debounced_state_lo;
807 *old_state |= (1 << pin);
809 *old_state &= ~(1 << pin);
813 mv_gpio_debounced_state_get(device_t dev, int pin)
816 struct mv_gpio_softc *sc;
817 sc = (struct mv_gpio_softc *)device_get_softc(dev);
819 MV_GPIO_ASSERT_LOCKED();
821 if (pin >= GPIO_PINS_PER_REG) {
822 state = &sc->debounced_state_hi;
823 pin -= GPIO_PINS_PER_REG;
825 state = &sc->debounced_state_lo;
827 return (*state & (1 << pin));
831 mv_gpio_out(device_t dev, uint32_t pin, uint8_t val, uint8_t enable)
833 struct mv_gpio_softc *sc;
834 sc = (struct mv_gpio_softc *)device_get_softc(dev);
838 mv_gpio_value_set(dev, pin, val);
839 mv_gpio_out_en(dev, pin, enable);
845 mv_gpio_in(device_t dev, uint32_t pin)
848 struct mv_gpio_softc *sc;
849 sc = (struct mv_gpio_softc *)device_get_softc(dev);
851 MV_GPIO_ASSERT_LOCKED();
853 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) {
854 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW)
855 state = (mv_gpio_debounced_state_get(dev, pin) ? 0 : 1);
857 state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0);
858 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) {
859 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW)
860 state = (mv_gpio_value_get(dev, pin, 1) ? 0 : 1);
862 state = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
864 state = (mv_gpio_value_get(dev, pin, 0) ? 1 : 0);
870 mv_gpio_reg_read(device_t dev, uint32_t reg)
872 struct mv_gpio_softc *sc;
873 sc = (struct mv_gpio_softc *)device_get_softc(dev);
875 return (bus_space_read_4(sc->bst, sc->bsh, sc->offset + reg));
879 mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val)
881 struct mv_gpio_softc *sc;
882 sc = (struct mv_gpio_softc *)device_get_softc(dev);
884 bus_space_write_4(sc->bst, sc->bsh, sc->offset + reg, val);
888 mv_gpio_reg_set(device_t dev, uint32_t reg, uint32_t pin)
892 reg_val = mv_gpio_reg_read(dev, reg);
893 reg_val |= GPIO(pin);
894 mv_gpio_reg_write(dev, reg, reg_val);
898 mv_gpio_reg_clear(device_t dev, uint32_t reg, uint32_t pin)
902 reg_val = mv_gpio_reg_read(dev, reg);
903 reg_val &= ~(GPIO(pin));
904 mv_gpio_reg_write(dev, reg, reg_val);
908 mv_gpio_out_en(device_t dev, uint32_t pin, uint8_t enable)
911 struct mv_gpio_softc *sc;
912 sc = (struct mv_gpio_softc *)device_get_softc(dev);
914 if (pin >= sc->pin_num)
917 reg = GPIO_DATA_OUT_EN_CTRL;
920 mv_gpio_reg_clear(dev, reg, pin);
922 mv_gpio_reg_set(dev, reg, pin);
926 mv_gpio_blink(device_t dev, uint32_t pin, uint8_t enable)
929 struct mv_gpio_softc *sc;
930 sc = (struct mv_gpio_softc *)device_get_softc(dev);
932 if (pin >= sc->pin_num)
938 mv_gpio_reg_set(dev, reg, pin);
940 mv_gpio_reg_clear(dev, reg, pin);
944 mv_gpio_polarity(device_t dev, uint32_t pin, uint8_t enable, uint8_t toggle)
946 uint32_t reg, reg_val;
947 struct mv_gpio_softc *sc;
948 sc = (struct mv_gpio_softc *)device_get_softc(dev);
950 if (pin >= sc->pin_num)
953 reg = GPIO_DATA_IN_POLAR;
956 reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin);
958 mv_gpio_reg_clear(dev, reg, pin);
960 mv_gpio_reg_set(dev, reg, pin);
962 mv_gpio_reg_set(dev, reg, pin);
964 mv_gpio_reg_clear(dev, reg, pin);
968 mv_gpio_level(device_t dev, uint32_t pin, uint8_t enable)
971 struct mv_gpio_softc *sc;
972 sc = (struct mv_gpio_softc *)device_get_softc(dev);
974 if (pin >= sc->pin_num)
977 reg = GPIO_INT_LEV_MASK;
980 mv_gpio_reg_set(dev, reg, pin);
982 mv_gpio_reg_clear(dev, reg, pin);
986 mv_gpio_edge(device_t dev, uint32_t pin, uint8_t enable)
989 struct mv_gpio_softc *sc;
990 sc = (struct mv_gpio_softc *)device_get_softc(dev);
992 if (pin >= sc->pin_num)
995 reg = GPIO_INT_EDGE_MASK;
998 mv_gpio_reg_set(dev, reg, pin);
1000 mv_gpio_reg_clear(dev, reg, pin);
1004 mv_gpio_int_ack(struct mv_gpio_pindev *s)
1007 struct mv_gpio_softc *sc;
1008 sc = (struct mv_gpio_softc *)device_get_softc(s->dev);
1011 if (pin >= sc->pin_num)
1014 reg = GPIO_INT_CAUSE;
1016 mv_gpio_reg_clear(s->dev, reg, pin);
1020 mv_gpio_value_get(device_t dev, uint32_t pin, uint8_t exclude_polar)
1022 uint32_t reg, polar_reg, reg_val, polar_reg_val;
1023 struct mv_gpio_softc *sc;
1024 sc = (struct mv_gpio_softc *)device_get_softc(dev);
1026 if (pin >= sc->pin_num)
1030 polar_reg = GPIO_DATA_IN_POLAR;
1032 reg_val = mv_gpio_reg_read(dev, reg);
1034 if (exclude_polar) {
1035 polar_reg_val = mv_gpio_reg_read(dev, polar_reg);
1036 return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin)));
1038 return (reg_val & GPIO(pin));
1042 mv_gpio_value_set(device_t dev, uint32_t pin, uint8_t val)
1045 struct mv_gpio_softc *sc;
1046 sc = (struct mv_gpio_softc *)device_get_softc(dev);
1048 MV_GPIO_ASSERT_LOCKED();
1050 if (pin >= sc->pin_num)
1053 reg = GPIO_DATA_OUT;
1056 mv_gpio_reg_set(dev, reg, pin);
1058 mv_gpio_reg_clear(dev, reg, pin);
1062 * GPIO interface methods
1066 mv_gpio_pin_max(device_t dev, int *maxpin)
1068 struct mv_gpio_softc *sc;
1072 sc = device_get_softc(dev);
1073 *maxpin = sc->pin_num;
1079 mv_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
1081 struct mv_gpio_softc *sc = device_get_softc(dev);
1085 if (pin >= sc->pin_num)
1089 *caps = sc->gpio_setup[pin].gp_caps;
1096 mv_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
1098 struct mv_gpio_softc *sc = device_get_softc(dev);
1102 if (pin >= sc->pin_num)
1106 *flags = sc->gpio_setup[pin].gp_flags;
1113 mv_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
1115 struct mv_gpio_softc *sc = device_get_softc(dev);
1119 if (pin >= sc->pin_num)
1123 memcpy(name, sc->gpio_setup[pin].gp_name, GPIOMAXNAME);
1130 mv_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
1133 struct mv_gpio_softc *sc = device_get_softc(dev);
1134 if (pin >= sc->pin_num)
1137 /* Check for unwanted flags. */
1138 if ((flags & sc->gpio_setup[pin].gp_caps) != flags)
1141 ret = mv_gpio_configure(dev, pin, flags, ~0);
1147 mv_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
1149 struct mv_gpio_softc *sc = device_get_softc(dev);
1150 if (pin >= sc->pin_num)
1154 mv_gpio_value_set(dev, pin, value);
1161 mv_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
1163 struct mv_gpio_softc *sc = device_get_softc(dev);
1167 if (pin >= sc->pin_num)
1171 *value = mv_gpio_in(dev, pin);
1178 mv_gpio_pin_toggle(device_t dev, uint32_t pin)
1180 struct mv_gpio_softc *sc = device_get_softc(dev);
1182 if (pin >= sc->pin_num)
1186 value = mv_gpio_in(dev, pin);
1187 value = (~value) & 1;
1188 mv_gpio_value_set(dev, pin, value);
1195 mv_gpio_get_bus(device_t dev)
1197 struct mv_gpio_softc *sc = device_get_softc(dev);
1199 return (sc->sc_busdev);
1203 mv_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
1204 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
1206 struct mv_gpio_softc *sc = device_get_softc(bus);
1208 if (gpios[0] >= sc->pin_num)
1213 mv_gpio_configure(bus, *pin, *flags, ~0);