2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 Benno Rice.
5 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
8 * Adapted and extended for Marvell SoCs by Semihalf.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/kernel.h>
41 #include <sys/interrupt.h>
42 #include <sys/module.h>
43 #include <sys/malloc.h>
44 #include <sys/mutex.h>
46 #include <sys/queue.h>
47 #include <sys/timetc.h>
48 #include <machine/bus.h>
49 #include <machine/intr.h>
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
55 #include <arm/mv/mvvar.h>
56 #include <arm/mv/mvreg.h>
58 #define GPIO_MAX_INTR_COUNT 8
59 #define GPIO_PINS_PER_REG 32
61 struct mv_gpio_softc {
62 struct resource * res[GPIO_MAX_INTR_COUNT + 1];
63 void *ih_cookie[GPIO_MAX_INTR_COUNT];
65 bus_space_handle_t bsh;
66 uint8_t pin_num; /* number of GPIO pins */
67 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */
70 extern struct resource_spec mv_gpio_res[];
72 static struct mv_gpio_softc *mv_gpio_softc = NULL;
73 static uint32_t gpio_setup[MV_GPIO_MAX_NPINS];
75 static int mv_gpio_probe(device_t);
76 static int mv_gpio_attach(device_t);
77 static int mv_gpio_intr(void *);
78 static int mv_gpio_init(void);
80 static void mv_gpio_intr_handler(int pin);
81 static uint32_t mv_gpio_reg_read(uint32_t reg);
82 static void mv_gpio_reg_write(uint32_t reg, uint32_t val);
83 static void mv_gpio_reg_set(uint32_t reg, uint32_t val);
84 static void mv_gpio_reg_clear(uint32_t reg, uint32_t val);
86 static void mv_gpio_blink(uint32_t pin, uint8_t enable);
87 static void mv_gpio_polarity(uint32_t pin, uint8_t enable);
88 static void mv_gpio_level(uint32_t pin, uint8_t enable);
89 static void mv_gpio_edge(uint32_t pin, uint8_t enable);
90 static void mv_gpio_out_en(uint32_t pin, uint8_t enable);
91 static void mv_gpio_int_ack(uint32_t pin);
92 static void mv_gpio_value_set(uint32_t pin, uint8_t val);
93 static uint32_t mv_gpio_value_get(uint32_t pin);
95 static device_method_t mv_gpio_methods[] = {
96 DEVMETHOD(device_probe, mv_gpio_probe),
97 DEVMETHOD(device_attach, mv_gpio_attach),
101 static driver_t mv_gpio_driver = {
104 sizeof(struct mv_gpio_softc),
107 static devclass_t mv_gpio_devclass;
109 DRIVER_MODULE(gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0);
111 typedef int (*gpios_phandler_t)(phandle_t, pcell_t *, int);
113 struct gpio_ctrl_entry {
115 gpios_phandler_t handler;
118 static int mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len);
119 int gpio_get_config_from_dt(void);
121 struct gpio_ctrl_entry gpio_controllers[] = {
122 { "mrvl,gpio", &mv_handle_gpios_prop },
127 mv_gpio_probe(device_t dev)
130 if (!ofw_bus_status_okay(dev))
133 if (!ofw_bus_is_compatible(dev, "mrvl,gpio"))
136 device_set_desc(dev, "Marvell Integrated GPIO Controller");
141 mv_gpio_attach(device_t dev)
144 struct mv_gpio_softc *sc;
145 uint32_t dev_id, rev_id;
147 sc = (struct mv_gpio_softc *)device_get_softc(dev);
153 /* Get chip id and revision */
154 soc_id(&dev_id, &rev_id);
156 if (dev_id == MV_DEV_88F5182 ||
157 dev_id == MV_DEV_88F5281 ||
158 dev_id == MV_DEV_MV78100 ||
159 dev_id == MV_DEV_MV78100_Z0 ) {
163 } else if (dev_id == MV_DEV_88F6281 ||
164 dev_id == MV_DEV_88F6282) {
169 device_printf(dev, "unknown chip id=0x%x\n", dev_id);
173 error = bus_alloc_resources(dev, mv_gpio_res, sc->res);
175 device_printf(dev, "could not allocate resources\n");
179 sc->bst = rman_get_bustag(sc->res[0]);
180 sc->bsh = rman_get_bushandle(sc->res[0]);
182 /* Disable and clear all interrupts */
183 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_EDGE_MASK, 0);
184 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_LEV_MASK, 0);
185 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_CAUSE, 0);
187 if (sc->pin_num > GPIO_PINS_PER_REG) {
188 bus_space_write_4(sc->bst, sc->bsh,
189 GPIO_HI_INT_EDGE_MASK, 0);
190 bus_space_write_4(sc->bst, sc->bsh,
191 GPIO_HI_INT_LEV_MASK, 0);
192 bus_space_write_4(sc->bst, sc->bsh,
193 GPIO_HI_INT_CAUSE, 0);
196 for (i = 0; i < sc->irq_num; i++) {
197 if (bus_setup_intr(dev, sc->res[1 + i],
198 INTR_TYPE_MISC, mv_gpio_intr, NULL,
199 sc, &sc->ih_cookie[i]) != 0) {
200 bus_release_resources(dev, mv_gpio_res, sc->res);
201 device_printf(dev, "could not set up intr %d\n", i);
206 return (mv_gpio_init());
210 mv_gpio_intr(void *arg)
212 uint32_t int_cause, gpio_val;
213 uint32_t int_cause_hi, gpio_val_hi = 0;
216 int_cause = mv_gpio_reg_read(GPIO_INT_CAUSE);
217 gpio_val = mv_gpio_reg_read(GPIO_DATA_IN);
218 gpio_val &= int_cause;
219 if (mv_gpio_softc->pin_num > GPIO_PINS_PER_REG) {
220 int_cause_hi = mv_gpio_reg_read(GPIO_HI_INT_CAUSE);
221 gpio_val_hi = mv_gpio_reg_read(GPIO_HI_DATA_IN);
222 gpio_val_hi &= int_cause_hi;
226 while (gpio_val != 0) {
228 mv_gpio_intr_handler(i);
233 if (mv_gpio_softc->pin_num > GPIO_PINS_PER_REG) {
235 while (gpio_val_hi != 0) {
237 mv_gpio_intr_handler(i + GPIO_PINS_PER_REG);
243 return (FILTER_HANDLED);
247 * GPIO interrupt handling
250 static struct intr_event *gpio_events[MV_GPIO_MAX_NPINS];
253 mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt,
254 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep)
256 struct intr_event *event;
259 if (pin < 0 || pin >= mv_gpio_softc->pin_num)
261 event = gpio_events[pin];
263 error = intr_event_create(&event, (void *)pin, 0, pin,
264 (void (*)(void *))mv_gpio_intr_mask,
265 (void (*)(void *))mv_gpio_intr_unmask,
266 (void (*)(void *))mv_gpio_int_ack,
271 gpio_events[pin] = event;
274 intr_event_add_handler(event, name, filt, hand, arg,
275 intr_priority(flags), flags, cookiep);
280 mv_gpio_intr_mask(int pin)
283 if (pin >= mv_gpio_softc->pin_num)
286 if (gpio_setup[pin] & MV_GPIO_IN_IRQ_EDGE)
287 mv_gpio_edge(pin, 0);
289 mv_gpio_level(pin, 0);
293 mv_gpio_intr_unmask(int pin)
296 if (pin >= mv_gpio_softc->pin_num)
299 if (gpio_setup[pin] & MV_GPIO_IN_IRQ_EDGE)
300 mv_gpio_edge(pin, 1);
302 mv_gpio_level(pin, 1);
306 mv_gpio_intr_handler(int pin)
308 struct intr_event *event;
310 event = gpio_events[pin];
311 if (event == NULL || TAILQ_EMPTY(&event->ie_handlers))
314 intr_event_handle(event, NULL);
318 mv_gpio_configure(uint32_t pin, uint32_t flags)
321 if (pin >= mv_gpio_softc->pin_num)
324 if (flags & MV_GPIO_OUT_BLINK)
325 mv_gpio_blink(pin, 1);
326 if (flags & MV_GPIO_IN_POL_LOW)
327 mv_gpio_polarity(pin, 1);
328 if (flags & MV_GPIO_IN_IRQ_EDGE)
329 mv_gpio_edge(pin, 1);
330 if (flags & MV_GPIO_IN_IRQ_LEVEL)
331 mv_gpio_level(pin, 1);
333 gpio_setup[pin] = flags;
339 mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable)
342 mv_gpio_value_set(pin, val);
343 mv_gpio_out_en(pin, enable);
347 mv_gpio_in(uint32_t pin)
350 return (mv_gpio_value_get(pin) ? 1 : 0);
354 mv_gpio_reg_read(uint32_t reg)
357 return (bus_space_read_4(mv_gpio_softc->bst,
358 mv_gpio_softc->bsh, reg));
362 mv_gpio_reg_write(uint32_t reg, uint32_t val)
365 bus_space_write_4(mv_gpio_softc->bst,
366 mv_gpio_softc->bsh, reg, val);
370 mv_gpio_reg_set(uint32_t reg, uint32_t pin)
374 reg_val = mv_gpio_reg_read(reg);
375 reg_val |= GPIO(pin);
376 mv_gpio_reg_write(reg, reg_val);
380 mv_gpio_reg_clear(uint32_t reg, uint32_t pin)
384 reg_val = mv_gpio_reg_read(reg);
385 reg_val &= ~(GPIO(pin));
386 mv_gpio_reg_write(reg, reg_val);
390 mv_gpio_out_en(uint32_t pin, uint8_t enable)
394 if (pin >= mv_gpio_softc->pin_num)
397 if (pin >= GPIO_PINS_PER_REG) {
398 reg = GPIO_HI_DATA_OUT_EN_CTRL;
399 pin -= GPIO_PINS_PER_REG;
401 reg = GPIO_DATA_OUT_EN_CTRL;
404 mv_gpio_reg_clear(reg, pin);
406 mv_gpio_reg_set(reg, pin);
410 mv_gpio_blink(uint32_t pin, uint8_t enable)
414 if (pin >= mv_gpio_softc->pin_num)
417 if (pin >= GPIO_PINS_PER_REG) {
418 reg = GPIO_HI_BLINK_EN;
419 pin -= GPIO_PINS_PER_REG;
424 mv_gpio_reg_set(reg, pin);
426 mv_gpio_reg_clear(reg, pin);
430 mv_gpio_polarity(uint32_t pin, uint8_t enable)
434 if (pin >= mv_gpio_softc->pin_num)
437 if (pin >= GPIO_PINS_PER_REG) {
438 reg = GPIO_HI_DATA_IN_POLAR;
439 pin -= GPIO_PINS_PER_REG;
441 reg = GPIO_DATA_IN_POLAR;
444 mv_gpio_reg_set(reg, pin);
446 mv_gpio_reg_clear(reg, pin);
450 mv_gpio_level(uint32_t pin, uint8_t enable)
454 if (pin >= mv_gpio_softc->pin_num)
457 if (pin >= GPIO_PINS_PER_REG) {
458 reg = GPIO_HI_INT_LEV_MASK;
459 pin -= GPIO_PINS_PER_REG;
461 reg = GPIO_INT_LEV_MASK;
464 mv_gpio_reg_set(reg, pin);
466 mv_gpio_reg_clear(reg, pin);
470 mv_gpio_edge(uint32_t pin, uint8_t enable)
474 if (pin >= mv_gpio_softc->pin_num)
477 if (pin >= GPIO_PINS_PER_REG) {
478 reg = GPIO_HI_INT_EDGE_MASK;
479 pin -= GPIO_PINS_PER_REG;
481 reg = GPIO_INT_EDGE_MASK;
484 mv_gpio_reg_set(reg, pin);
486 mv_gpio_reg_clear(reg, pin);
490 mv_gpio_int_ack(uint32_t pin)
494 if (pin >= mv_gpio_softc->pin_num)
497 if (pin >= GPIO_PINS_PER_REG) {
498 reg = GPIO_HI_INT_CAUSE;
499 pin -= GPIO_PINS_PER_REG;
501 reg = GPIO_INT_CAUSE;
503 mv_gpio_reg_clear(reg, pin);
507 mv_gpio_value_get(uint32_t pin)
509 uint32_t reg, reg_val;
511 if (pin >= mv_gpio_softc->pin_num)
514 if (pin >= GPIO_PINS_PER_REG) {
515 reg = GPIO_HI_DATA_IN;
516 pin -= GPIO_PINS_PER_REG;
520 reg_val = mv_gpio_reg_read(reg);
522 return (reg_val & GPIO(pin));
526 mv_gpio_value_set(uint32_t pin, uint8_t val)
530 if (pin >= mv_gpio_softc->pin_num)
533 if (pin >= GPIO_PINS_PER_REG) {
534 reg = GPIO_HI_DATA_OUT;
535 pin -= GPIO_PINS_PER_REG;
540 mv_gpio_reg_set(reg, pin);
542 mv_gpio_reg_clear(reg, pin);
546 mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len)
548 pcell_t gpio_cells, pincnt;
549 int inc, t, tuples, tuple_size;
551 u_long gpio_ctrl, size;
552 struct mv_gpio_softc sc;
555 if (!OF_hasprop(ctrl, "gpio-controller"))
556 /* Node is not a GPIO controller. */
559 if (OF_getencprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0)
564 tuple_size = gpio_cells * sizeof(pcell_t) + sizeof(phandle_t);
565 tuples = len / tuple_size;
567 if (fdt_regsize(ctrl, &gpio_ctrl, &size))
570 if (OF_getencprop(ctrl, "pin-count", &pincnt, sizeof(pcell_t)) < 0)
575 * Skip controller reference, since controller's phandle is given
576 * explicitly (in a function argument).
578 inc = sizeof(ihandle_t) / sizeof(pcell_t);
581 for (t = 0; t < tuples; t++) {
586 mv_gpio_configure(pin, flags);
590 mv_gpio_out_en(pin, 0);
593 if (flags & MV_GPIO_OUT_OPEN_DRAIN)
594 mv_gpio_out(pin, 0, 1);
596 if (flags & MV_GPIO_OUT_OPEN_SRC)
597 mv_gpio_out(pin, 1, 1);
599 gpios += gpio_cells + inc;
605 #define MAX_PINS_PER_NODE 5
606 #define GPIOS_PROP_CELLS 4
610 phandle_t child, parent, root, ctrl;
611 pcell_t gpios[MAX_PINS_PER_NODE * GPIOS_PROP_CELLS];
612 struct gpio_ctrl_entry *e;
615 root = OF_finddevice("/");
619 /* Traverse through entire tree to find nodes with 'gpios' prop */
620 for (child = OF_child(parent); child != 0; child = OF_peer(child)) {
622 /* Find a 'leaf'. Start the search from this node. */
623 while (OF_child(child)) {
625 child = OF_child(child);
627 if ((len = OF_getproplen(child, "gpios")) > 0) {
629 if (len > sizeof(gpios))
632 /* Get 'gpios' property. */
633 OF_getencprop(child, "gpios", gpios, len);
635 e = (struct gpio_ctrl_entry *)&gpio_controllers;
637 /* Find and call a handler. */
638 for (; e->compat; e++) {
640 * First cell of 'gpios' property should
641 * contain a ref. to a node defining GPIO
644 ctrl = OF_node_from_xref(gpios[0]);
646 if (ofw_bus_node_is_compatible(ctrl, e->compat))
647 /* Call a handler. */
648 if ((rv = e->handler(ctrl,
649 (pcell_t *)&gpios, len)))
654 if (OF_peer(child) == 0) {
655 /* No more siblings. */
657 parent = OF_parent(child);