2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 Benno Rice.
5 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
6 * Copyright (c) 2017 Semihalf.
9 * Adapted and extended for Marvell SoCs by Semihalf.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/interrupt.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/mutex.h>
47 #include <sys/queue.h>
48 #include <sys/timetc.h>
49 #include <sys/callout.h>
51 #include <machine/bus.h>
52 #include <machine/intr.h>
54 #include <dev/gpio/gpiobusvar.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
58 #include <arm/mv/mvvar.h>
59 #include <arm/mv/mvreg.h>
63 #define GPIO_MAX_INTR_COUNT 8
64 #define GPIO_PINS_PER_REG 32
65 #define GPIO_GENERIC_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
66 GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \
67 GPIO_PIN_TRISTATE | GPIO_PIN_PULLUP | \
68 GPIO_PIN_PULLDOWN | GPIO_PIN_INVIN | \
71 #define DEBOUNCE_CHECK_MS 1
72 #define DEBOUNCE_LO_HI_MS 2
73 #define DEBOUNCE_HI_LO_MS 2
74 #define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS)
76 struct mv_gpio_softc {
79 struct resource * mem_res;
81 struct resource * irq_res[GPIO_MAX_INTR_COUNT];
82 int irq_rid[GPIO_MAX_INTR_COUNT];
83 struct intr_event * gpio_events[MV_GPIO_MAX_NPINS];
84 void *ih_cookie[GPIO_MAX_INTR_COUNT];
86 bus_space_handle_t bsh;
89 uint8_t pin_num; /* number of GPIO pins */
90 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */
91 struct gpio_pin gpio_setup[MV_GPIO_MAX_NPINS];
93 /* Used for debouncing. */
94 uint32_t debounced_state_lo;
95 uint32_t debounced_state_hi;
96 struct callout **debounce_callouts;
97 int *debounce_counters;
100 struct mv_gpio_pindev {
105 static int mv_gpio_probe(device_t);
106 static int mv_gpio_attach(device_t);
107 static int mv_gpio_intr(device_t, void *);
109 static void mv_gpio_double_edge_init(device_t, int);
111 static int mv_gpio_debounce_setup(device_t, int);
112 static int mv_gpio_debounce_prepare(device_t, int);
113 static int mv_gpio_debounce_init(device_t, int);
114 static void mv_gpio_debounce_start(device_t, int);
115 static void mv_gpio_debounce(void *);
116 static void mv_gpio_debounced_state_set(device_t, int, uint8_t);
117 static uint32_t mv_gpio_debounced_state_get(device_t, int);
119 static void mv_gpio_exec_intr_handlers(device_t, uint32_t, int);
120 static void mv_gpio_intr_handler(device_t, int);
121 static uint32_t mv_gpio_reg_read(device_t, uint32_t);
122 static void mv_gpio_reg_write(device_t, uint32_t, uint32_t);
123 static void mv_gpio_reg_set(device_t, uint32_t, uint32_t);
124 static void mv_gpio_reg_clear(device_t, uint32_t, uint32_t);
126 static void mv_gpio_blink(device_t, uint32_t, uint8_t);
127 static void mv_gpio_polarity(device_t, uint32_t, uint8_t, uint8_t);
128 static void mv_gpio_level(device_t, uint32_t, uint8_t);
129 static void mv_gpio_edge(device_t, uint32_t, uint8_t);
130 static void mv_gpio_out_en(device_t, uint32_t, uint8_t);
131 static void mv_gpio_int_ack(struct mv_gpio_pindev *);
132 static void mv_gpio_value_set(device_t, uint32_t, uint8_t);
133 static uint32_t mv_gpio_value_get(device_t, uint32_t, uint8_t);
135 static void mv_gpio_intr_mask(struct mv_gpio_pindev *);
136 static void mv_gpio_intr_unmask(struct mv_gpio_pindev *);
138 void mv_gpio_finish_intrhandler(struct mv_gpio_pindev *);
139 int mv_gpio_setup_intrhandler(device_t, const char *,
140 driver_filter_t *, void (*)(void *), void *,
142 int mv_gpio_configure(device_t, uint32_t, uint32_t, uint32_t);
143 void mv_gpio_out(device_t, uint32_t, uint8_t, uint8_t);
144 uint8_t mv_gpio_in(device_t, uint32_t);
149 static device_t mv_gpio_get_bus(device_t);
150 static int mv_gpio_pin_max(device_t, int *);
151 static int mv_gpio_pin_getcaps(device_t, uint32_t, uint32_t *);
152 static int mv_gpio_pin_getflags(device_t, uint32_t, uint32_t *);
153 static int mv_gpio_pin_getname(device_t, uint32_t, char *);
154 static int mv_gpio_pin_setflags(device_t, uint32_t, uint32_t);
155 static int mv_gpio_pin_set(device_t, uint32_t, unsigned int);
156 static int mv_gpio_pin_get(device_t, uint32_t, unsigned int *);
157 static int mv_gpio_pin_toggle(device_t, uint32_t);
158 static int mv_gpio_map_gpios(device_t, phandle_t, phandle_t,
159 int, pcell_t *, uint32_t *, uint32_t *);
161 #define MV_GPIO_LOCK() mtx_lock_spin(&sc->mutex)
162 #define MV_GPIO_UNLOCK() mtx_unlock_spin(&sc->mutex)
163 #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&sc->mutex, MA_OWNED)
165 static device_method_t mv_gpio_methods[] = {
166 DEVMETHOD(device_probe, mv_gpio_probe),
167 DEVMETHOD(device_attach, mv_gpio_attach),
170 DEVMETHOD(gpio_get_bus, mv_gpio_get_bus),
171 DEVMETHOD(gpio_pin_max, mv_gpio_pin_max),
172 DEVMETHOD(gpio_pin_getname, mv_gpio_pin_getname),
173 DEVMETHOD(gpio_pin_getflags, mv_gpio_pin_getflags),
174 DEVMETHOD(gpio_pin_getcaps, mv_gpio_pin_getcaps),
175 DEVMETHOD(gpio_pin_setflags, mv_gpio_pin_setflags),
176 DEVMETHOD(gpio_pin_get, mv_gpio_pin_get),
177 DEVMETHOD(gpio_pin_set, mv_gpio_pin_set),
178 DEVMETHOD(gpio_pin_toggle, mv_gpio_pin_toggle),
179 DEVMETHOD(gpio_map_gpios, mv_gpio_map_gpios),
184 static driver_t mv_gpio_driver = {
187 sizeof(struct mv_gpio_softc),
190 EARLY_DRIVER_MODULE(mv_gpio, simplebus, mv_gpio_driver, 0, 0,
191 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST);
193 struct ofw_compat_data compat_data[] = {
195 { "marvell,orion-gpio", 1 },
200 mv_gpio_probe(device_t dev)
202 if (!ofw_bus_status_okay(dev))
205 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
208 device_set_desc(dev, "Marvell Integrated GPIO Controller");
213 mv_gpio_setup_interrupts(struct mv_gpio_softc *sc, phandle_t node)
219 /* Find root interrupt controller */
220 iparent = ofw_bus_find_iparent(node);
222 device_printf(sc->dev, "No interrupt-parrent found. "
226 /* While at parent - store interrupt cells prop */
227 if (OF_searchencprop(OF_node_from_xref(iparent),
228 "#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) {
229 device_printf(sc->dev, "DTB: Missing #interrupt-cells "
230 "property in interrupt parent node\n");
235 size = OF_getproplen(node, "interrupts");
237 size = size / sizeof(pcell_t);
238 size = size / irq_cells;
240 device_printf(sc->dev, "%d IRQs available\n", sc->irq_num);
242 device_printf(sc->dev, "ERROR: no interrupts entry found!\n");
246 for (i = 0; i < sc->irq_num; i++) {
248 sc->irq_res[i] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
249 &sc->irq_rid[i], RF_ACTIVE);
250 if (!sc->irq_res[i]) {
251 mtx_destroy(&sc->mutex);
252 device_printf(sc->dev,
253 "could not allocate gpio%d interrupt\n", i+1);
258 device_printf(sc->dev, "Disable interrupts (offset = %x + EDGE(0x18)\n", sc->offset);
259 /* Disable all interrupts */
260 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_EDGE_MASK, 0);
261 device_printf(sc->dev, "Disable interrupts (offset = %x + LEV(0x1C))\n", sc->offset);
262 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_LEV_MASK, 0);
264 for (i = 0; i < sc->irq_num; i++) {
265 device_printf(sc->dev, "Setup intr %d\n", i);
266 if (bus_setup_intr(sc->dev, sc->irq_res[i],
268 (driver_filter_t *)mv_gpio_intr, NULL,
269 sc, &sc->ih_cookie[i]) != 0) {
270 mtx_destroy(&sc->mutex);
271 bus_release_resource(sc->dev, SYS_RES_IRQ,
272 sc->irq_rid[i], sc->irq_res[i]);
273 device_printf(sc->dev, "could not set up intr %d\n", i);
278 /* Clear interrupt status. */
279 device_printf(sc->dev, "Clear int status (offset = %x)\n", sc->offset);
280 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_CAUSE, 0);
282 sc->debounce_callouts = (struct callout **)malloc(sc->pin_num *
283 sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO);
284 if (sc->debounce_callouts == NULL)
287 sc->debounce_counters = (int *)malloc(sc->pin_num * sizeof(int),
289 if (sc->debounce_counters == NULL)
296 mv_gpio_attach(device_t dev)
299 struct mv_gpio_softc *sc;
303 sc = (struct mv_gpio_softc *)device_get_softc(dev);
307 node = ofw_bus_get_node(dev);
310 if (OF_getencprop(node, "pin-count", &pincnt, sizeof(pcell_t)) >= 0 ||
311 OF_getencprop(node, "ngpios", &pincnt, sizeof(pcell_t)) >= 0) {
312 sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS);
314 device_printf(dev, "%d pins available\n", sc->pin_num);
316 device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n");
320 if (OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset)) == -1)
323 /* Assign generic capabilities to every gpio pin */
324 for(i = 0; i < sc->pin_num; i++)
325 sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP;
327 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN);
330 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
331 RF_ACTIVE | RF_SHAREABLE );
334 mtx_destroy(&sc->mutex);
335 device_printf(dev, "could not allocate memory window\n");
339 sc->bst = rman_get_bustag(sc->mem_res);
340 sc->bsh = rman_get_bushandle(sc->mem_res);
342 rv = mv_gpio_setup_interrupts(sc, node);
346 sc->sc_busdev = gpiobus_attach_bus(dev);
347 if (sc->sc_busdev == NULL) {
348 mtx_destroy(&sc->mutex);
349 bus_release_resource(dev, SYS_RES_IRQ,
350 sc->irq_rid[i], sc->irq_res[i]);
358 mv_gpio_intr(device_t dev, void *arg)
360 uint32_t int_cause, gpio_val;
361 struct mv_gpio_softc *sc;
362 sc = (struct mv_gpio_softc *)device_get_softc(dev);
367 * According to documentation, edge sensitive interrupts are asserted
368 * when unmasked GPIO_INT_CAUSE register bits are set.
370 int_cause = mv_gpio_reg_read(dev, GPIO_INT_CAUSE);
371 int_cause &= mv_gpio_reg_read(dev, GPIO_INT_EDGE_MASK);
374 * Level sensitive interrupts are asserted when unmasked GPIO_DATA_IN
375 * register bits are set.
377 gpio_val = mv_gpio_reg_read(dev, GPIO_DATA_IN);
378 gpio_val &= mv_gpio_reg_read(dev, GPIO_INT_LEV_MASK);
380 mv_gpio_exec_intr_handlers(dev, int_cause | gpio_val, 0);
384 return (FILTER_HANDLED);
388 * GPIO interrupt handling
392 mv_gpio_finish_intrhandler(struct mv_gpio_pindev *s)
394 /* When we acheive full interrupt support
395 * This function will be opposite to
396 * mv_gpio_setup_intrhandler
399 /* Now it exists only to remind that
400 * there should be place to free mv_gpio_pindev
401 * allocated by mv_gpio_setup_intrhandler
407 mv_gpio_setup_intrhandler(device_t dev, const char *name, driver_filter_t *filt,
408 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep)
410 struct intr_event *event;
412 struct mv_gpio_pindev *s;
413 struct mv_gpio_softc *sc;
414 sc = (struct mv_gpio_softc *)device_get_softc(dev);
415 s = malloc(sizeof(struct mv_gpio_pindev), M_DEVBUF, M_NOWAIT | M_ZERO);
417 if (pin < 0 || pin >= sc->pin_num)
419 event = sc->gpio_events[pin];
422 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) {
423 error = mv_gpio_debounce_init(dev, pin);
428 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE)
429 mv_gpio_double_edge_init(dev, pin);
431 error = intr_event_create(&event, (void *)s, 0, pin,
432 (void (*)(void *))mv_gpio_intr_mask,
433 (void (*)(void *))mv_gpio_intr_unmask,
434 (void (*)(void *))mv_gpio_int_ack,
439 sc->gpio_events[pin] = event;
442 intr_event_add_handler(event, name, filt, hand, arg,
443 intr_priority(flags), flags, cookiep);
448 mv_gpio_intr_mask(struct mv_gpio_pindev *s)
450 struct mv_gpio_softc *sc;
451 sc = (struct mv_gpio_softc *)device_get_softc(s->dev);
453 if (s->pin >= sc->pin_num)
458 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE |
459 MV_GPIO_IN_IRQ_DOUBLE_EDGE))
460 mv_gpio_edge(s->dev, s->pin, 0);
462 mv_gpio_level(s->dev, s->pin, 0);
465 * The interrupt has to be acknowledged before scheduling an interrupt
466 * thread. This way we allow for interrupt source to trigger again
467 * (which can happen with shared IRQs e.g. PCI) while processing the
478 mv_gpio_intr_unmask(struct mv_gpio_pindev *s)
480 struct mv_gpio_softc *sc;
481 sc = (struct mv_gpio_softc *)device_get_softc(s->dev);
483 if (s->pin >= sc->pin_num)
488 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE |
489 MV_GPIO_IN_IRQ_DOUBLE_EDGE))
490 mv_gpio_edge(s->dev, s->pin, 1);
492 mv_gpio_level(s->dev, s->pin, 1);
500 mv_gpio_exec_intr_handlers(device_t dev, uint32_t status, int high)
503 struct mv_gpio_softc *sc;
504 sc = (struct mv_gpio_softc *)device_get_softc(dev);
506 MV_GPIO_ASSERT_LOCKED();
509 while (status != 0) {
511 pin = (high ? (i + GPIO_PINS_PER_REG) : i);
512 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE)
513 mv_gpio_debounce_start(dev, pin);
514 else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) {
515 mv_gpio_polarity(dev, pin, 0, 1);
516 mv_gpio_intr_handler(dev, pin);
518 mv_gpio_intr_handler(dev, pin);
526 mv_gpio_intr_handler(device_t dev, int pin)
528 struct intr_irqsrc isrc;
529 struct mv_gpio_softc *sc;
530 sc = (struct mv_gpio_softc *)device_get_softc(dev);
532 MV_GPIO_ASSERT_LOCKED();
535 isrc.isrc_filter = NULL;
537 isrc.isrc_event = sc->gpio_events[pin];
539 if (isrc.isrc_event == NULL ||
540 CK_SLIST_EMPTY(&isrc.isrc_event->ie_handlers))
543 intr_isrc_dispatch(&isrc, NULL);
547 mv_gpio_configure(device_t dev, uint32_t pin, uint32_t flags, uint32_t mask)
550 struct mv_gpio_softc *sc;
551 sc = (struct mv_gpio_softc *)device_get_softc(dev);
554 if (pin >= sc->pin_num)
557 /* check flags consistency */
558 if (((flags & mask) & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) ==
559 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
562 if (mask & MV_GPIO_IN_DEBOUNCE) {
563 if (sc->irq_num == 0)
565 error = mv_gpio_debounce_prepare(dev, pin);
572 if ((mask & flags) & GPIO_PIN_INPUT)
573 mv_gpio_out_en(dev, pin, 0);
574 if ((mask & flags) & GPIO_PIN_OUTPUT) {
575 if ((flags & mask) & GPIO_PIN_OPENDRAIN)
576 mv_gpio_value_set(dev, pin, 0);
578 mv_gpio_value_set(dev, pin, 1);
579 mv_gpio_out_en(dev, pin, 1);
582 if (mask & MV_GPIO_OUT_BLINK)
583 mv_gpio_blink(dev, pin, flags & MV_GPIO_OUT_BLINK);
584 if (mask & MV_GPIO_IN_POL_LOW)
585 mv_gpio_polarity(dev, pin, flags & MV_GPIO_IN_POL_LOW, 0);
586 if (mask & MV_GPIO_IN_DEBOUNCE) {
587 error = mv_gpio_debounce_setup(dev, pin);
594 sc->gpio_setup[pin].gp_flags &= ~(mask);
595 sc->gpio_setup[pin].gp_flags |= (flags & mask);
603 mv_gpio_double_edge_init(device_t dev, int pin)
606 struct mv_gpio_softc *sc __unused;
607 sc = (struct mv_gpio_softc *)device_get_softc(dev);
609 MV_GPIO_ASSERT_LOCKED();
611 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
614 mv_gpio_polarity(dev, pin, 1, 0);
616 mv_gpio_polarity(dev, pin, 0, 0);
620 mv_gpio_debounce_setup(device_t dev, int pin)
623 struct mv_gpio_softc *sc;
625 sc = (struct mv_gpio_softc *)device_get_softc(dev);
627 MV_GPIO_ASSERT_LOCKED();
629 c = sc->debounce_callouts[pin];
633 if (callout_active(c))
634 callout_deactivate(c);
642 mv_gpio_debounce_prepare(device_t dev, int pin)
645 struct mv_gpio_softc *sc;
647 sc = (struct mv_gpio_softc *)device_get_softc(dev);
649 c = sc->debounce_callouts[pin];
651 c = (struct callout *)malloc(sizeof(struct callout),
653 sc->debounce_callouts[pin] = c;
663 mv_gpio_debounce_init(device_t dev, int pin)
667 struct mv_gpio_softc *sc;
669 sc = (struct mv_gpio_softc *)device_get_softc(dev);
671 MV_GPIO_ASSERT_LOCKED();
673 cnt = &sc->debounce_counters[pin];
674 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
676 mv_gpio_polarity(dev, pin, 1, 0);
677 *cnt = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS;
679 mv_gpio_polarity(dev, pin, 0, 0);
680 *cnt = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS;
683 mv_gpio_debounced_state_set(dev, pin, raw_read);
689 mv_gpio_debounce_start(device_t dev, int pin)
692 struct mv_gpio_pindev s = {dev, pin};
693 struct mv_gpio_pindev *sd;
694 struct mv_gpio_softc *sc;
695 sc = (struct mv_gpio_softc *)device_get_softc(dev);
697 MV_GPIO_ASSERT_LOCKED();
699 c = sc->debounce_callouts[pin];
705 if (callout_pending(c) || callout_active(c)) {
710 sd = (struct mv_gpio_pindev *)malloc(sizeof(struct mv_gpio_pindev),
719 callout_reset(c, DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, sd);
723 mv_gpio_debounce(void *arg)
725 uint8_t raw_read, last_state;
728 int *debounce_counter;
729 struct mv_gpio_softc *sc;
730 struct mv_gpio_pindev *s;
732 s = (struct mv_gpio_pindev *)arg;
735 sc = (struct mv_gpio_softc *)device_get_softc(dev);
739 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
740 last_state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0);
741 debounce_counter = &sc->debounce_counters[pin];
743 if (raw_read == last_state) {
745 *debounce_counter = DEBOUNCE_HI_LO_MS /
748 *debounce_counter = DEBOUNCE_LO_HI_MS /
751 callout_reset(sc->debounce_callouts[pin],
752 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg);
754 *debounce_counter = *debounce_counter - 1;
755 if (*debounce_counter != 0)
756 callout_reset(sc->debounce_callouts[pin],
757 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg);
759 mv_gpio_debounced_state_set(dev, pin, raw_read);
762 *debounce_counter = DEBOUNCE_HI_LO_MS /
765 *debounce_counter = DEBOUNCE_LO_HI_MS /
768 if (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) &&
770 (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) == 0) &&
772 (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE))
773 mv_gpio_intr_handler(dev, pin);
775 /* Toggle polarity for next edge. */
776 mv_gpio_polarity(dev, pin, 0, 1);
779 callout_deactivate(sc->debounce_callouts[pin]);
787 mv_gpio_debounced_state_set(device_t dev, int pin, uint8_t new_state)
790 struct mv_gpio_softc *sc;
791 sc = (struct mv_gpio_softc *)device_get_softc(dev);
793 MV_GPIO_ASSERT_LOCKED();
795 if (pin >= GPIO_PINS_PER_REG) {
796 old_state = &sc->debounced_state_hi;
797 pin -= GPIO_PINS_PER_REG;
799 old_state = &sc->debounced_state_lo;
802 *old_state |= (1 << pin);
804 *old_state &= ~(1 << pin);
808 mv_gpio_debounced_state_get(device_t dev, int pin)
811 struct mv_gpio_softc *sc;
812 sc = (struct mv_gpio_softc *)device_get_softc(dev);
814 MV_GPIO_ASSERT_LOCKED();
816 if (pin >= GPIO_PINS_PER_REG) {
817 state = &sc->debounced_state_hi;
818 pin -= GPIO_PINS_PER_REG;
820 state = &sc->debounced_state_lo;
822 return (*state & (1 << pin));
826 mv_gpio_out(device_t dev, uint32_t pin, uint8_t val, uint8_t enable)
828 struct mv_gpio_softc *sc;
829 sc = (struct mv_gpio_softc *)device_get_softc(dev);
833 mv_gpio_value_set(dev, pin, val);
834 mv_gpio_out_en(dev, pin, enable);
840 mv_gpio_in(device_t dev, uint32_t pin)
843 struct mv_gpio_softc *sc;
844 sc = (struct mv_gpio_softc *)device_get_softc(dev);
846 MV_GPIO_ASSERT_LOCKED();
848 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) {
849 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW)
850 state = (mv_gpio_debounced_state_get(dev, pin) ? 0 : 1);
852 state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0);
853 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) {
854 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW)
855 state = (mv_gpio_value_get(dev, pin, 1) ? 0 : 1);
857 state = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
859 state = (mv_gpio_value_get(dev, pin, 0) ? 1 : 0);
865 mv_gpio_reg_read(device_t dev, uint32_t reg)
867 struct mv_gpio_softc *sc;
868 sc = (struct mv_gpio_softc *)device_get_softc(dev);
870 return (bus_space_read_4(sc->bst, sc->bsh, sc->offset + reg));
874 mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val)
876 struct mv_gpio_softc *sc;
877 sc = (struct mv_gpio_softc *)device_get_softc(dev);
879 bus_space_write_4(sc->bst, sc->bsh, sc->offset + reg, val);
883 mv_gpio_reg_set(device_t dev, uint32_t reg, uint32_t pin)
887 reg_val = mv_gpio_reg_read(dev, reg);
888 reg_val |= GPIO(pin);
889 mv_gpio_reg_write(dev, reg, reg_val);
893 mv_gpio_reg_clear(device_t dev, uint32_t reg, uint32_t pin)
897 reg_val = mv_gpio_reg_read(dev, reg);
898 reg_val &= ~(GPIO(pin));
899 mv_gpio_reg_write(dev, reg, reg_val);
903 mv_gpio_out_en(device_t dev, uint32_t pin, uint8_t enable)
906 struct mv_gpio_softc *sc;
907 sc = (struct mv_gpio_softc *)device_get_softc(dev);
909 if (pin >= sc->pin_num)
912 reg = GPIO_DATA_OUT_EN_CTRL;
915 mv_gpio_reg_clear(dev, reg, pin);
917 mv_gpio_reg_set(dev, reg, pin);
921 mv_gpio_blink(device_t dev, uint32_t pin, uint8_t enable)
924 struct mv_gpio_softc *sc;
925 sc = (struct mv_gpio_softc *)device_get_softc(dev);
927 if (pin >= sc->pin_num)
933 mv_gpio_reg_set(dev, reg, pin);
935 mv_gpio_reg_clear(dev, reg, pin);
939 mv_gpio_polarity(device_t dev, uint32_t pin, uint8_t enable, uint8_t toggle)
941 uint32_t reg, reg_val;
942 struct mv_gpio_softc *sc;
943 sc = (struct mv_gpio_softc *)device_get_softc(dev);
945 if (pin >= sc->pin_num)
948 reg = GPIO_DATA_IN_POLAR;
951 reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin);
953 mv_gpio_reg_clear(dev, reg, pin);
955 mv_gpio_reg_set(dev, reg, pin);
957 mv_gpio_reg_set(dev, reg, pin);
959 mv_gpio_reg_clear(dev, reg, pin);
963 mv_gpio_level(device_t dev, uint32_t pin, uint8_t enable)
966 struct mv_gpio_softc *sc;
967 sc = (struct mv_gpio_softc *)device_get_softc(dev);
969 if (pin >= sc->pin_num)
972 reg = GPIO_INT_LEV_MASK;
975 mv_gpio_reg_set(dev, reg, pin);
977 mv_gpio_reg_clear(dev, reg, pin);
981 mv_gpio_edge(device_t dev, uint32_t pin, uint8_t enable)
984 struct mv_gpio_softc *sc;
985 sc = (struct mv_gpio_softc *)device_get_softc(dev);
987 if (pin >= sc->pin_num)
990 reg = GPIO_INT_EDGE_MASK;
993 mv_gpio_reg_set(dev, reg, pin);
995 mv_gpio_reg_clear(dev, reg, pin);
999 mv_gpio_int_ack(struct mv_gpio_pindev *s)
1002 struct mv_gpio_softc *sc;
1003 sc = (struct mv_gpio_softc *)device_get_softc(s->dev);
1006 if (pin >= sc->pin_num)
1009 reg = GPIO_INT_CAUSE;
1011 mv_gpio_reg_clear(s->dev, reg, pin);
1015 mv_gpio_value_get(device_t dev, uint32_t pin, uint8_t exclude_polar)
1017 uint32_t reg, polar_reg, reg_val, polar_reg_val;
1018 struct mv_gpio_softc *sc;
1019 sc = (struct mv_gpio_softc *)device_get_softc(dev);
1021 if (pin >= sc->pin_num)
1025 polar_reg = GPIO_DATA_IN_POLAR;
1027 reg_val = mv_gpio_reg_read(dev, reg);
1029 if (exclude_polar) {
1030 polar_reg_val = mv_gpio_reg_read(dev, polar_reg);
1031 return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin)));
1033 return (reg_val & GPIO(pin));
1037 mv_gpio_value_set(device_t dev, uint32_t pin, uint8_t val)
1040 struct mv_gpio_softc *sc;
1041 sc = (struct mv_gpio_softc *)device_get_softc(dev);
1043 MV_GPIO_ASSERT_LOCKED();
1045 if (pin >= sc->pin_num)
1048 reg = GPIO_DATA_OUT;
1051 mv_gpio_reg_set(dev, reg, pin);
1053 mv_gpio_reg_clear(dev, reg, pin);
1057 * GPIO interface methods
1061 mv_gpio_pin_max(device_t dev, int *maxpin)
1063 struct mv_gpio_softc *sc;
1067 sc = device_get_softc(dev);
1068 *maxpin = sc->pin_num;
1074 mv_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
1076 struct mv_gpio_softc *sc = device_get_softc(dev);
1080 if (pin >= sc->pin_num)
1084 *caps = sc->gpio_setup[pin].gp_caps;
1091 mv_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
1093 struct mv_gpio_softc *sc = device_get_softc(dev);
1097 if (pin >= sc->pin_num)
1101 *flags = sc->gpio_setup[pin].gp_flags;
1108 mv_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
1110 struct mv_gpio_softc *sc = device_get_softc(dev);
1114 if (pin >= sc->pin_num)
1118 memcpy(name, sc->gpio_setup[pin].gp_name, GPIOMAXNAME);
1125 mv_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
1128 struct mv_gpio_softc *sc = device_get_softc(dev);
1129 if (pin >= sc->pin_num)
1132 /* Check for unwanted flags. */
1133 if ((flags & sc->gpio_setup[pin].gp_caps) != flags)
1136 ret = mv_gpio_configure(dev, pin, flags, ~0);
1142 mv_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
1144 struct mv_gpio_softc *sc = device_get_softc(dev);
1145 if (pin >= sc->pin_num)
1149 mv_gpio_value_set(dev, pin, value);
1156 mv_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
1158 struct mv_gpio_softc *sc = device_get_softc(dev);
1162 if (pin >= sc->pin_num)
1166 *value = mv_gpio_in(dev, pin);
1173 mv_gpio_pin_toggle(device_t dev, uint32_t pin)
1175 struct mv_gpio_softc *sc = device_get_softc(dev);
1177 if (pin >= sc->pin_num)
1181 value = mv_gpio_in(dev, pin);
1182 value = (~value) & 1;
1183 mv_gpio_value_set(dev, pin, value);
1190 mv_gpio_get_bus(device_t dev)
1192 struct mv_gpio_softc *sc = device_get_softc(dev);
1194 return (sc->sc_busdev);
1198 mv_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
1199 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
1201 struct mv_gpio_softc *sc = device_get_softc(bus);
1203 if (gpios[0] >= sc->pin_num)
1208 mv_gpio_configure(bus, *pin, *flags, ~0);