2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
6 * Adapted and extended for Marvell SoCs by Semihalf.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
39 #include <sys/interrupt.h>
40 #include <sys/module.h>
41 #include <sys/malloc.h>
42 #include <sys/mutex.h>
44 #include <sys/queue.h>
45 #include <sys/timetc.h>
46 #include <machine/bus.h>
47 #include <machine/fdt.h>
48 #include <machine/intr.h>
50 #include <dev/fdt/fdt_common.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
54 #include <arm/mv/mvvar.h>
55 #include <arm/mv/mvreg.h>
57 #define GPIO_MAX_INTR_COUNT 8
58 #define GPIO_PINS_PER_REG 32
60 struct mv_gpio_softc {
61 struct resource * res[GPIO_MAX_INTR_COUNT + 1];
62 void *ih_cookie[GPIO_MAX_INTR_COUNT];
64 bus_space_handle_t bsh;
65 uint8_t pin_num; /* number of GPIO pins */
66 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */
69 extern struct resource_spec mv_gpio_res[];
71 static struct mv_gpio_softc *mv_gpio_softc = NULL;
72 static uint32_t gpio_setup[MV_GPIO_MAX_NPINS];
74 static int mv_gpio_probe(device_t);
75 static int mv_gpio_attach(device_t);
76 static int mv_gpio_intr(void *);
78 static void mv_gpio_intr_handler(int pin);
79 static uint32_t mv_gpio_reg_read(uint32_t reg);
80 static void mv_gpio_reg_write(uint32_t reg, uint32_t val);
81 static void mv_gpio_reg_set(uint32_t reg, uint32_t val);
82 static void mv_gpio_reg_clear(uint32_t reg, uint32_t val);
84 static void mv_gpio_blink(uint32_t pin, uint8_t enable);
85 static void mv_gpio_polarity(uint32_t pin, uint8_t enable);
86 static void mv_gpio_level(uint32_t pin, uint8_t enable);
87 static void mv_gpio_edge(uint32_t pin, uint8_t enable);
88 static void mv_gpio_out_en(uint32_t pin, uint8_t enable);
89 static void mv_gpio_int_ack(uint32_t pin);
90 static void mv_gpio_value_set(uint32_t pin, uint8_t val);
91 static uint32_t mv_gpio_value_get(uint32_t pin);
93 static device_method_t mv_gpio_methods[] = {
94 DEVMETHOD(device_probe, mv_gpio_probe),
95 DEVMETHOD(device_attach, mv_gpio_attach),
99 static driver_t mv_gpio_driver = {
102 sizeof(struct mv_gpio_softc),
105 static devclass_t mv_gpio_devclass;
107 DRIVER_MODULE(gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0);
109 typedef int (*gpios_phandler_t)(phandle_t, pcell_t *, int);
111 struct gpio_ctrl_entry {
113 gpios_phandler_t handler;
116 int mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len);
117 int gpio_get_config_from_dt(void);
119 struct gpio_ctrl_entry gpio_controllers[] = {
120 { "mrvl,gpio", &mv_handle_gpios_prop },
125 mv_gpio_probe(device_t dev)
128 if (!ofw_bus_is_compatible(dev, "mrvl,gpio"))
131 device_set_desc(dev, "Marvell Integrated GPIO Controller");
136 mv_gpio_attach(device_t dev)
139 struct mv_gpio_softc *sc;
140 uint32_t dev_id, rev_id;
142 sc = (struct mv_gpio_softc *)device_get_softc(dev);
148 /* Get chip id and revision */
149 soc_id(&dev_id, &rev_id);
151 if (dev_id == MV_DEV_88F5182 ||
152 dev_id == MV_DEV_88F5281 ||
153 dev_id == MV_DEV_MV78100 ||
154 dev_id == MV_DEV_MV78100_Z0 ) {
158 } else if (dev_id == MV_DEV_88F6281 ||
159 dev_id == MV_DEV_88F6282) {
164 device_printf(dev, "unknown chip id=0x%x\n", dev_id);
168 error = bus_alloc_resources(dev, mv_gpio_res, sc->res);
170 device_printf(dev, "could not allocate resources\n");
174 sc->bst = rman_get_bustag(sc->res[0]);
175 sc->bsh = rman_get_bushandle(sc->res[0]);
177 /* Disable and clear all interrupts */
178 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_EDGE_MASK, 0);
179 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_LEV_MASK, 0);
180 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_CAUSE, 0);
182 if (sc->pin_num > GPIO_PINS_PER_REG) {
183 bus_space_write_4(sc->bst, sc->bsh,
184 GPIO_HI_INT_EDGE_MASK, 0);
185 bus_space_write_4(sc->bst, sc->bsh,
186 GPIO_HI_INT_LEV_MASK, 0);
187 bus_space_write_4(sc->bst, sc->bsh,
188 GPIO_HI_INT_CAUSE, 0);
191 for (i = 0; i < sc->irq_num; i++) {
192 if (bus_setup_intr(dev, sc->res[1 + i],
193 INTR_TYPE_MISC, mv_gpio_intr, NULL,
194 sc, &sc->ih_cookie[i]) != 0) {
195 bus_release_resources(dev, mv_gpio_res, sc->res);
196 device_printf(dev, "could not set up intr %d\n", i);
201 return (platform_gpio_init());
205 mv_gpio_intr(void *arg)
207 uint32_t int_cause, gpio_val;
208 uint32_t int_cause_hi, gpio_val_hi = 0;
211 int_cause = mv_gpio_reg_read(GPIO_INT_CAUSE);
212 gpio_val = mv_gpio_reg_read(GPIO_DATA_IN);
213 gpio_val &= int_cause;
214 if (mv_gpio_softc->pin_num > GPIO_PINS_PER_REG) {
215 int_cause_hi = mv_gpio_reg_read(GPIO_HI_INT_CAUSE);
216 gpio_val_hi = mv_gpio_reg_read(GPIO_HI_DATA_IN);
217 gpio_val_hi &= int_cause_hi;
221 while (gpio_val != 0) {
223 mv_gpio_intr_handler(i);
228 if (mv_gpio_softc->pin_num > GPIO_PINS_PER_REG) {
230 while (gpio_val_hi != 0) {
232 mv_gpio_intr_handler(i + GPIO_PINS_PER_REG);
238 return (FILTER_HANDLED);
242 * GPIO interrupt handling
245 static struct intr_event *gpio_events[MV_GPIO_MAX_NPINS];
248 mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt,
249 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep)
251 struct intr_event *event;
254 if (pin < 0 || pin >= mv_gpio_softc->pin_num)
256 event = gpio_events[pin];
258 error = intr_event_create(&event, (void *)pin, 0, pin,
259 (void (*)(void *))mv_gpio_intr_mask,
260 (void (*)(void *))mv_gpio_intr_unmask,
261 (void (*)(void *))mv_gpio_int_ack,
266 gpio_events[pin] = event;
269 intr_event_add_handler(event, name, filt, hand, arg,
270 intr_priority(flags), flags, cookiep);
275 mv_gpio_intr_mask(int pin)
278 if (pin >= mv_gpio_softc->pin_num)
281 if (gpio_setup[pin] & MV_GPIO_IN_IRQ_EDGE)
282 mv_gpio_edge(pin, 0);
284 mv_gpio_level(pin, 0);
288 mv_gpio_intr_unmask(int pin)
291 if (pin >= mv_gpio_softc->pin_num)
294 if (gpio_setup[pin] & MV_GPIO_IN_IRQ_EDGE)
295 mv_gpio_edge(pin, 1);
297 mv_gpio_level(pin, 1);
301 mv_gpio_intr_handler(int pin)
303 struct intr_event *event;
305 event = gpio_events[pin];
306 if (event == NULL || TAILQ_EMPTY(&event->ie_handlers))
309 intr_event_handle(event, NULL);
313 mv_gpio_configure(uint32_t pin, uint32_t flags)
316 if (pin >= mv_gpio_softc->pin_num)
319 if (flags & MV_GPIO_OUT_BLINK)
320 mv_gpio_blink(pin, 1);
321 if (flags & MV_GPIO_IN_POL_LOW)
322 mv_gpio_polarity(pin, 1);
323 if (flags & MV_GPIO_IN_IRQ_EDGE)
324 mv_gpio_edge(pin, 1);
325 if (flags & MV_GPIO_IN_IRQ_LEVEL)
326 mv_gpio_level(pin, 1);
328 gpio_setup[pin] = flags;
334 mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable)
337 mv_gpio_value_set(pin, val);
338 mv_gpio_out_en(pin, enable);
342 mv_gpio_in(uint32_t pin)
345 return (mv_gpio_value_get(pin) ? 1 : 0);
349 mv_gpio_reg_read(uint32_t reg)
352 return (bus_space_read_4(mv_gpio_softc->bst,
353 mv_gpio_softc->bsh, reg));
357 mv_gpio_reg_write(uint32_t reg, uint32_t val)
360 bus_space_write_4(mv_gpio_softc->bst,
361 mv_gpio_softc->bsh, reg, val);
365 mv_gpio_reg_set(uint32_t reg, uint32_t pin)
369 reg_val = mv_gpio_reg_read(reg);
370 reg_val |= GPIO(pin);
371 mv_gpio_reg_write(reg, reg_val);
375 mv_gpio_reg_clear(uint32_t reg, uint32_t pin)
379 reg_val = mv_gpio_reg_read(reg);
380 reg_val &= ~(GPIO(pin));
381 mv_gpio_reg_write(reg, reg_val);
385 mv_gpio_out_en(uint32_t pin, uint8_t enable)
389 if (pin >= mv_gpio_softc->pin_num)
392 if (pin >= GPIO_PINS_PER_REG) {
393 reg = GPIO_HI_DATA_OUT_EN_CTRL;
394 pin -= GPIO_PINS_PER_REG;
396 reg = GPIO_DATA_OUT_EN_CTRL;
399 mv_gpio_reg_clear(reg, pin);
401 mv_gpio_reg_set(reg, pin);
405 mv_gpio_blink(uint32_t pin, uint8_t enable)
409 if (pin >= mv_gpio_softc->pin_num)
412 if (pin >= GPIO_PINS_PER_REG) {
413 reg = GPIO_HI_BLINK_EN;
414 pin -= GPIO_PINS_PER_REG;
419 mv_gpio_reg_set(reg, pin);
421 mv_gpio_reg_clear(reg, pin);
425 mv_gpio_polarity(uint32_t pin, uint8_t enable)
429 if (pin >= mv_gpio_softc->pin_num)
432 if (pin >= GPIO_PINS_PER_REG) {
433 reg = GPIO_HI_DATA_IN_POLAR;
434 pin -= GPIO_PINS_PER_REG;
436 reg = GPIO_DATA_IN_POLAR;
439 mv_gpio_reg_set(reg, pin);
441 mv_gpio_reg_clear(reg, pin);
445 mv_gpio_level(uint32_t pin, uint8_t enable)
449 if (pin >= mv_gpio_softc->pin_num)
452 if (pin >= GPIO_PINS_PER_REG) {
453 reg = GPIO_HI_INT_LEV_MASK;
454 pin -= GPIO_PINS_PER_REG;
456 reg = GPIO_INT_LEV_MASK;
459 mv_gpio_reg_set(reg, pin);
461 mv_gpio_reg_clear(reg, pin);
465 mv_gpio_edge(uint32_t pin, uint8_t enable)
469 if (pin >= mv_gpio_softc->pin_num)
472 if (pin >= GPIO_PINS_PER_REG) {
473 reg = GPIO_HI_INT_EDGE_MASK;
474 pin -= GPIO_PINS_PER_REG;
476 reg = GPIO_INT_EDGE_MASK;
479 mv_gpio_reg_set(reg, pin);
481 mv_gpio_reg_clear(reg, pin);
485 mv_gpio_int_ack(uint32_t pin)
489 if (pin >= mv_gpio_softc->pin_num)
492 if (pin >= GPIO_PINS_PER_REG) {
493 reg = GPIO_HI_INT_CAUSE;
494 pin -= GPIO_PINS_PER_REG;
496 reg = GPIO_INT_CAUSE;
498 mv_gpio_reg_clear(reg, pin);
502 mv_gpio_value_get(uint32_t pin)
504 uint32_t reg, reg_val;
506 if (pin >= mv_gpio_softc->pin_num)
509 if (pin >= GPIO_PINS_PER_REG) {
510 reg = GPIO_HI_DATA_IN;
511 pin -= GPIO_PINS_PER_REG;
515 reg_val = mv_gpio_reg_read(reg);
517 return (reg_val & GPIO(pin));
521 mv_gpio_value_set(uint32_t pin, uint8_t val)
525 if (pin >= mv_gpio_softc->pin_num)
528 if (pin >= GPIO_PINS_PER_REG) {
529 reg = GPIO_HI_DATA_OUT;
530 pin -= GPIO_PINS_PER_REG;
535 mv_gpio_reg_set(reg, pin);
537 mv_gpio_reg_clear(reg, pin);
541 mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len)
543 pcell_t gpio_cells, pincnt;
544 int inc, t, tuples, tuple_size;
546 u_long gpio_ctrl, size;
547 struct mv_gpio_softc sc;
550 if (!OF_hasprop(ctrl, "gpio-controller"))
551 /* Node is not a GPIO controller. */
554 if (OF_getprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0)
557 gpio_cells = fdt32_to_cpu(gpio_cells);
561 tuple_size = gpio_cells * sizeof(pcell_t) + sizeof(phandle_t);
562 tuples = len / tuple_size;
564 if (fdt_regsize(ctrl, &gpio_ctrl, &size))
567 if (OF_getprop(ctrl, "pin-count", &pincnt, sizeof(pcell_t)) < 0)
569 sc.pin_num = fdt32_to_cpu(pincnt);
572 * Skip controller reference, since controller's phandle is given
573 * explicitly (in a function argument).
575 inc = sizeof(ihandle_t) / sizeof(pcell_t);
578 for (t = 0; t < tuples; t++) {
579 pin = fdt32_to_cpu(gpios[0]);
580 dir = fdt32_to_cpu(gpios[1]);
581 flags = fdt32_to_cpu(gpios[2]);
583 mv_gpio_configure(pin, flags);
587 mv_gpio_out_en(pin, 0);
590 if (flags & MV_GPIO_OUT_OPEN_DRAIN)
591 mv_gpio_out(pin, 0, 1);
593 if (flags & MV_GPIO_OUT_OPEN_SRC)
594 mv_gpio_out(pin, 1, 1);
596 gpios += gpio_cells + inc;
602 #define MAX_PINS_PER_NODE 5
603 #define GPIOS_PROP_CELLS 4
605 platform_gpio_init(void)
607 phandle_t child, parent, root, ctrl;
608 ihandle_t ctrl_ihandle;
609 pcell_t gpios[MAX_PINS_PER_NODE * GPIOS_PROP_CELLS];
610 struct gpio_ctrl_entry *e;
613 root = OF_finddevice("/");
617 /* Traverse through entire tree to find nodes with 'gpios' prop */
618 for (child = OF_child(parent); child != 0; child = OF_peer(child)) {
620 /* Find a 'leaf'. Start the search from this node. */
621 while (OF_child(child)) {
623 child = OF_child(child);
625 if ((len = OF_getproplen(child, "gpios")) > 0) {
627 if (len > sizeof(gpios))
630 /* Get 'gpios' property. */
631 OF_getprop(child, "gpios", &gpios, len);
633 e = (struct gpio_ctrl_entry *)&gpio_controllers;
635 /* Find and call a handler. */
636 for (; e->compat; e++) {
638 * First cell of 'gpios' property should
639 * contain a ref. to a node defining GPIO
642 ctrl_ihandle = (ihandle_t)gpios[0];
643 ctrl_ihandle = fdt32_to_cpu(ctrl_ihandle);
644 ctrl = OF_instance_to_package(ctrl_ihandle);
646 if (fdt_is_compatible(ctrl, e->compat))
647 /* Call a handler. */
648 if ((rv = e->handler(ctrl,
649 (pcell_t *)&gpios, len)))
654 if (OF_peer(child) == 0) {
655 /* No more siblings. */
657 parent = OF_parent(child);