2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 Benno Rice.
5 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
6 * Copyright (c) 2017 Semihalf.
9 * Adapted and extended for Marvell SoCs by Semihalf.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/interrupt.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/mutex.h>
47 #include <sys/queue.h>
48 #include <sys/timetc.h>
49 #include <sys/callout.h>
51 #include <machine/bus.h>
52 #include <machine/intr.h>
54 #include <dev/gpio/gpiobusvar.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
58 #include <arm/mv/mvvar.h>
59 #include <arm/mv/mvreg.h>
67 #define GPIO_MAX_INTR_COUNT 8
68 #define GPIO_PINS_PER_REG 32
69 #define GPIO_GENERIC_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
70 GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \
71 GPIO_PIN_TRISTATE | GPIO_PIN_PULLUP | \
72 GPIO_PIN_PULLDOWN | GPIO_PIN_INVIN | \
75 #define DEBOUNCE_CHECK_MS 1
76 #define DEBOUNCE_LO_HI_MS 2
77 #define DEBOUNCE_HI_LO_MS 2
78 #define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS)
80 struct mv_gpio_softc {
83 struct resource * mem_res;
85 struct resource * irq_res[GPIO_MAX_INTR_COUNT];
86 int irq_rid[GPIO_MAX_INTR_COUNT];
87 struct intr_event * gpio_events[MV_GPIO_MAX_NPINS];
88 void *ih_cookie[GPIO_MAX_INTR_COUNT];
90 bus_space_handle_t bsh;
93 uint8_t pin_num; /* number of GPIO pins */
94 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */
95 struct gpio_pin gpio_setup[MV_GPIO_MAX_NPINS];
97 /* Used for debouncing. */
98 uint32_t debounced_state_lo;
99 uint32_t debounced_state_hi;
100 struct callout **debounce_callouts;
101 int *debounce_counters;
104 struct mv_gpio_pindev {
109 static int mv_gpio_probe(device_t);
110 static int mv_gpio_attach(device_t);
111 static int mv_gpio_intr(device_t, void *);
113 static void mv_gpio_double_edge_init(device_t, int);
115 static int mv_gpio_debounce_setup(device_t, int);
116 static int mv_gpio_debounce_prepare(device_t, int);
117 static int mv_gpio_debounce_init(device_t, int);
118 static void mv_gpio_debounce_start(device_t, int);
119 static void mv_gpio_debounce(void *);
120 static void mv_gpio_debounced_state_set(device_t, int, uint8_t);
121 static uint32_t mv_gpio_debounced_state_get(device_t, int);
123 static void mv_gpio_exec_intr_handlers(device_t, uint32_t, int);
124 static void mv_gpio_intr_handler(device_t, int);
125 static uint32_t mv_gpio_reg_read(device_t, uint32_t);
126 static void mv_gpio_reg_write(device_t, uint32_t, uint32_t);
127 static void mv_gpio_reg_set(device_t, uint32_t, uint32_t);
128 static void mv_gpio_reg_clear(device_t, uint32_t, uint32_t);
130 static void mv_gpio_blink(device_t, uint32_t, uint8_t);
131 static void mv_gpio_polarity(device_t, uint32_t, uint8_t, uint8_t);
132 static void mv_gpio_level(device_t, uint32_t, uint8_t);
133 static void mv_gpio_edge(device_t, uint32_t, uint8_t);
134 static void mv_gpio_out_en(device_t, uint32_t, uint8_t);
135 static void mv_gpio_int_ack(struct mv_gpio_pindev *);
136 static void mv_gpio_value_set(device_t, uint32_t, uint8_t);
137 static uint32_t mv_gpio_value_get(device_t, uint32_t, uint8_t);
139 static void mv_gpio_intr_mask(struct mv_gpio_pindev *);
140 static void mv_gpio_intr_unmask(struct mv_gpio_pindev *);
142 void mv_gpio_finish_intrhandler(struct mv_gpio_pindev *);
143 int mv_gpio_setup_intrhandler(device_t, const char *,
144 driver_filter_t *, void (*)(void *), void *,
146 int mv_gpio_configure(device_t, uint32_t, uint32_t, uint32_t);
147 void mv_gpio_out(device_t, uint32_t, uint8_t, uint8_t);
148 uint8_t mv_gpio_in(device_t, uint32_t);
153 static device_t mv_gpio_get_bus(device_t);
154 static int mv_gpio_pin_max(device_t, int *);
155 static int mv_gpio_pin_getcaps(device_t, uint32_t, uint32_t *);
156 static int mv_gpio_pin_getflags(device_t, uint32_t, uint32_t *);
157 static int mv_gpio_pin_getname(device_t, uint32_t, char *);
158 static int mv_gpio_pin_setflags(device_t, uint32_t, uint32_t);
159 static int mv_gpio_pin_set(device_t, uint32_t, unsigned int);
160 static int mv_gpio_pin_get(device_t, uint32_t, unsigned int *);
161 static int mv_gpio_pin_toggle(device_t, uint32_t);
162 static int mv_gpio_map_gpios(device_t, phandle_t, phandle_t,
163 int, pcell_t *, uint32_t *, uint32_t *);
165 #define MV_GPIO_LOCK() mtx_lock_spin(&sc->mutex)
166 #define MV_GPIO_UNLOCK() mtx_unlock_spin(&sc->mutex)
167 #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&sc->mutex, MA_OWNED)
169 static device_method_t mv_gpio_methods[] = {
170 DEVMETHOD(device_probe, mv_gpio_probe),
171 DEVMETHOD(device_attach, mv_gpio_attach),
174 DEVMETHOD(gpio_get_bus, mv_gpio_get_bus),
175 DEVMETHOD(gpio_pin_max, mv_gpio_pin_max),
176 DEVMETHOD(gpio_pin_getname, mv_gpio_pin_getname),
177 DEVMETHOD(gpio_pin_getflags, mv_gpio_pin_getflags),
178 DEVMETHOD(gpio_pin_getcaps, mv_gpio_pin_getcaps),
179 DEVMETHOD(gpio_pin_setflags, mv_gpio_pin_setflags),
180 DEVMETHOD(gpio_pin_get, mv_gpio_pin_get),
181 DEVMETHOD(gpio_pin_set, mv_gpio_pin_set),
182 DEVMETHOD(gpio_pin_toggle, mv_gpio_pin_toggle),
183 DEVMETHOD(gpio_map_gpios, mv_gpio_map_gpios),
188 static driver_t mv_gpio_driver = {
191 sizeof(struct mv_gpio_softc),
194 static devclass_t mv_gpio_devclass;
196 EARLY_DRIVER_MODULE(mv_gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0,
197 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST);
199 struct ofw_compat_data compat_data[] = {
201 { "marvell,orion-gpio", 1 },
202 #ifdef SOC_MARVELL_8K
203 { "marvell,armada-8k-gpio", 1 },
209 mv_gpio_probe(device_t dev)
211 if (!ofw_bus_status_okay(dev))
214 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
217 device_set_desc(dev, "Marvell Integrated GPIO Controller");
222 mv_gpio_setup_interrupts(struct mv_gpio_softc *sc, phandle_t node)
228 /* Find root interrupt controller */
229 iparent = ofw_bus_find_iparent(node);
231 device_printf(sc->dev, "No interrupt-parrent found. "
235 /* While at parent - store interrupt cells prop */
236 if (OF_searchencprop(OF_node_from_xref(iparent),
237 "#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) {
238 device_printf(sc->dev, "DTB: Missing #interrupt-cells "
239 "property in interrupt parent node\n");
244 size = OF_getproplen(node, "interrupts");
246 size = size / sizeof(pcell_t);
247 size = size / irq_cells;
249 device_printf(sc->dev, "%d IRQs available\n", sc->irq_num);
251 device_printf(sc->dev, "ERROR: no interrupts entry found!\n");
255 for (i = 0; i < sc->irq_num; i++) {
257 sc->irq_res[i] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
258 &sc->irq_rid[i], RF_ACTIVE);
259 if (!sc->irq_res[i]) {
260 mtx_destroy(&sc->mutex);
261 device_printf(sc->dev,
262 "could not allocate gpio%d interrupt\n", i+1);
267 device_printf(sc->dev, "Disable interrupts (offset = %x + EDGE(0x18)\n", sc->offset);
268 /* Disable all interrupts */
269 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_EDGE_MASK, 0);
270 device_printf(sc->dev, "Disable interrupts (offset = %x + LEV(0x1C))\n", sc->offset);
271 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_LEV_MASK, 0);
273 for (i = 0; i < sc->irq_num; i++) {
274 device_printf(sc->dev, "Setup intr %d\n", i);
275 if (bus_setup_intr(sc->dev, sc->irq_res[i],
277 (driver_filter_t *)mv_gpio_intr, NULL,
278 sc, &sc->ih_cookie[i]) != 0) {
279 mtx_destroy(&sc->mutex);
280 bus_release_resource(sc->dev, SYS_RES_IRQ,
281 sc->irq_rid[i], sc->irq_res[i]);
282 device_printf(sc->dev, "could not set up intr %d\n", i);
287 /* Clear interrupt status. */
288 device_printf(sc->dev, "Clear int status (offset = %x)\n", sc->offset);
289 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_CAUSE, 0);
291 sc->debounce_callouts = (struct callout **)malloc(sc->pin_num *
292 sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO);
293 if (sc->debounce_callouts == NULL)
296 sc->debounce_counters = (int *)malloc(sc->pin_num * sizeof(int),
298 if (sc->debounce_counters == NULL)
305 mv_gpio_attach(device_t dev)
308 struct mv_gpio_softc *sc;
312 sc = (struct mv_gpio_softc *)device_get_softc(dev);
316 node = ofw_bus_get_node(dev);
319 if (OF_getencprop(node, "pin-count", &pincnt, sizeof(pcell_t)) >= 0 ||
320 OF_getencprop(node, "ngpios", &pincnt, sizeof(pcell_t)) >= 0) {
321 sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS);
323 device_printf(dev, "%d pins available\n", sc->pin_num);
325 device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n");
329 if (OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset)) == -1)
332 /* Assign generic capabilities to every gpio pin */
333 for(i = 0; i < sc->pin_num; i++)
334 sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP;
336 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN);
339 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
340 RF_ACTIVE | RF_SHAREABLE );
343 mtx_destroy(&sc->mutex);
344 device_printf(dev, "could not allocate memory window\n");
348 sc->bst = rman_get_bustag(sc->mem_res);
349 sc->bsh = rman_get_bushandle(sc->mem_res);
351 rv = mv_gpio_setup_interrupts(sc, node);
355 sc->sc_busdev = gpiobus_attach_bus(dev);
356 if (sc->sc_busdev == NULL) {
357 mtx_destroy(&sc->mutex);
358 bus_release_resource(dev, SYS_RES_IRQ,
359 sc->irq_rid[i], sc->irq_res[i]);
367 mv_gpio_intr(device_t dev, void *arg)
369 uint32_t int_cause, gpio_val;
370 struct mv_gpio_softc *sc;
371 sc = (struct mv_gpio_softc *)device_get_softc(dev);
376 * According to documentation, edge sensitive interrupts are asserted
377 * when unmasked GPIO_INT_CAUSE register bits are set.
379 int_cause = mv_gpio_reg_read(dev, GPIO_INT_CAUSE);
380 int_cause &= mv_gpio_reg_read(dev, GPIO_INT_EDGE_MASK);
383 * Level sensitive interrupts are asserted when unmasked GPIO_DATA_IN
384 * register bits are set.
386 gpio_val = mv_gpio_reg_read(dev, GPIO_DATA_IN);
387 gpio_val &= mv_gpio_reg_read(dev, GPIO_INT_LEV_MASK);
389 mv_gpio_exec_intr_handlers(dev, int_cause | gpio_val, 0);
393 return (FILTER_HANDLED);
397 * GPIO interrupt handling
401 mv_gpio_finish_intrhandler(struct mv_gpio_pindev *s)
403 /* When we acheive full interrupt support
404 * This function will be opposite to
405 * mv_gpio_setup_intrhandler
408 /* Now it exists only to remind that
409 * there should be place to free mv_gpio_pindev
410 * allocated by mv_gpio_setup_intrhandler
416 mv_gpio_setup_intrhandler(device_t dev, const char *name, driver_filter_t *filt,
417 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep)
419 struct intr_event *event;
421 struct mv_gpio_pindev *s;
422 struct mv_gpio_softc *sc;
423 sc = (struct mv_gpio_softc *)device_get_softc(dev);
424 s = malloc(sizeof(struct mv_gpio_pindev), M_DEVBUF, M_NOWAIT | M_ZERO);
426 if (pin < 0 || pin >= sc->pin_num)
428 event = sc->gpio_events[pin];
431 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) {
432 error = mv_gpio_debounce_init(dev, pin);
437 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE)
438 mv_gpio_double_edge_init(dev, pin);
440 error = intr_event_create(&event, (void *)s, 0, pin,
441 (void (*)(void *))mv_gpio_intr_mask,
442 (void (*)(void *))mv_gpio_intr_unmask,
443 (void (*)(void *))mv_gpio_int_ack,
448 sc->gpio_events[pin] = event;
451 intr_event_add_handler(event, name, filt, hand, arg,
452 intr_priority(flags), flags, cookiep);
457 mv_gpio_intr_mask(struct mv_gpio_pindev *s)
459 struct mv_gpio_softc *sc;
460 sc = (struct mv_gpio_softc *)device_get_softc(s->dev);
462 if (s->pin >= sc->pin_num)
467 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE |
468 MV_GPIO_IN_IRQ_DOUBLE_EDGE))
469 mv_gpio_edge(s->dev, s->pin, 0);
471 mv_gpio_level(s->dev, s->pin, 0);
474 * The interrupt has to be acknowledged before scheduling an interrupt
475 * thread. This way we allow for interrupt source to trigger again
476 * (which can happen with shared IRQs e.g. PCI) while processing the
487 mv_gpio_intr_unmask(struct mv_gpio_pindev *s)
489 struct mv_gpio_softc *sc;
490 sc = (struct mv_gpio_softc *)device_get_softc(s->dev);
492 if (s->pin >= sc->pin_num)
497 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE |
498 MV_GPIO_IN_IRQ_DOUBLE_EDGE))
499 mv_gpio_edge(s->dev, s->pin, 1);
501 mv_gpio_level(s->dev, s->pin, 1);
509 mv_gpio_exec_intr_handlers(device_t dev, uint32_t status, int high)
512 struct mv_gpio_softc *sc;
513 sc = (struct mv_gpio_softc *)device_get_softc(dev);
515 MV_GPIO_ASSERT_LOCKED();
518 while (status != 0) {
520 pin = (high ? (i + GPIO_PINS_PER_REG) : i);
521 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE)
522 mv_gpio_debounce_start(dev, pin);
523 else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) {
524 mv_gpio_polarity(dev, pin, 0, 1);
525 mv_gpio_intr_handler(dev, pin);
527 mv_gpio_intr_handler(dev, pin);
535 mv_gpio_intr_handler(device_t dev, int pin)
538 struct intr_irqsrc isrc;
539 struct mv_gpio_softc *sc;
540 sc = (struct mv_gpio_softc *)device_get_softc(dev);
542 MV_GPIO_ASSERT_LOCKED();
545 isrc.isrc_filter = NULL;
547 isrc.isrc_event = sc->gpio_events[pin];
549 if (isrc.isrc_event == NULL ||
550 CK_SLIST_EMPTY(&isrc.isrc_event->ie_handlers))
553 intr_isrc_dispatch(&isrc, NULL);
558 mv_gpio_configure(device_t dev, uint32_t pin, uint32_t flags, uint32_t mask)
561 struct mv_gpio_softc *sc;
562 sc = (struct mv_gpio_softc *)device_get_softc(dev);
565 if (pin >= sc->pin_num)
568 /* check flags consistency */
569 if (((flags & mask) & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) ==
570 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
573 if (mask & MV_GPIO_IN_DEBOUNCE) {
574 if (sc->irq_num == 0)
576 error = mv_gpio_debounce_prepare(dev, pin);
583 if ((mask & flags) & GPIO_PIN_INPUT)
584 mv_gpio_out_en(dev, pin, 0);
585 if ((mask & flags) & GPIO_PIN_OUTPUT) {
586 if ((flags & mask) & GPIO_PIN_OPENDRAIN)
587 mv_gpio_value_set(dev, pin, 0);
589 mv_gpio_value_set(dev, pin, 1);
590 mv_gpio_out_en(dev, pin, 1);
593 if (mask & MV_GPIO_OUT_BLINK)
594 mv_gpio_blink(dev, pin, flags & MV_GPIO_OUT_BLINK);
595 if (mask & MV_GPIO_IN_POL_LOW)
596 mv_gpio_polarity(dev, pin, flags & MV_GPIO_IN_POL_LOW, 0);
597 if (mask & MV_GPIO_IN_DEBOUNCE) {
598 error = mv_gpio_debounce_setup(dev, pin);
605 sc->gpio_setup[pin].gp_flags &= ~(mask);
606 sc->gpio_setup[pin].gp_flags |= (flags & mask);
614 mv_gpio_double_edge_init(device_t dev, int pin)
617 struct mv_gpio_softc *sc;
618 sc = (struct mv_gpio_softc *)device_get_softc(dev);
620 MV_GPIO_ASSERT_LOCKED();
622 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
625 mv_gpio_polarity(dev, pin, 1, 0);
627 mv_gpio_polarity(dev, pin, 0, 0);
631 mv_gpio_debounce_setup(device_t dev, int pin)
634 struct mv_gpio_softc *sc;
636 sc = (struct mv_gpio_softc *)device_get_softc(dev);
638 MV_GPIO_ASSERT_LOCKED();
640 c = sc->debounce_callouts[pin];
644 if (callout_active(c))
645 callout_deactivate(c);
653 mv_gpio_debounce_prepare(device_t dev, int pin)
656 struct mv_gpio_softc *sc;
658 sc = (struct mv_gpio_softc *)device_get_softc(dev);
660 c = sc->debounce_callouts[pin];
662 c = (struct callout *)malloc(sizeof(struct callout),
664 sc->debounce_callouts[pin] = c;
674 mv_gpio_debounce_init(device_t dev, int pin)
678 struct mv_gpio_softc *sc;
680 sc = (struct mv_gpio_softc *)device_get_softc(dev);
682 MV_GPIO_ASSERT_LOCKED();
684 cnt = &sc->debounce_counters[pin];
685 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
687 mv_gpio_polarity(dev, pin, 1, 0);
688 *cnt = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS;
690 mv_gpio_polarity(dev, pin, 0, 0);
691 *cnt = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS;
694 mv_gpio_debounced_state_set(dev, pin, raw_read);
700 mv_gpio_debounce_start(device_t dev, int pin)
703 struct mv_gpio_pindev s = {dev, pin};
704 struct mv_gpio_pindev *sd;
705 struct mv_gpio_softc *sc;
706 sc = (struct mv_gpio_softc *)device_get_softc(dev);
708 MV_GPIO_ASSERT_LOCKED();
710 c = sc->debounce_callouts[pin];
716 if (callout_pending(c) || callout_active(c)) {
721 sd = (struct mv_gpio_pindev *)malloc(sizeof(struct mv_gpio_pindev),
730 callout_reset(c, DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, sd);
734 mv_gpio_debounce(void *arg)
736 uint8_t raw_read, last_state;
739 int *debounce_counter;
740 struct mv_gpio_softc *sc;
741 struct mv_gpio_pindev *s;
743 s = (struct mv_gpio_pindev *)arg;
746 sc = (struct mv_gpio_softc *)device_get_softc(dev);
750 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
751 last_state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0);
752 debounce_counter = &sc->debounce_counters[pin];
754 if (raw_read == last_state) {
756 *debounce_counter = DEBOUNCE_HI_LO_MS /
759 *debounce_counter = DEBOUNCE_LO_HI_MS /
762 callout_reset(sc->debounce_callouts[pin],
763 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg);
765 *debounce_counter = *debounce_counter - 1;
766 if (*debounce_counter != 0)
767 callout_reset(sc->debounce_callouts[pin],
768 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg);
770 mv_gpio_debounced_state_set(dev, pin, raw_read);
773 *debounce_counter = DEBOUNCE_HI_LO_MS /
776 *debounce_counter = DEBOUNCE_LO_HI_MS /
779 if (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) &&
781 (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) == 0) &&
783 (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE))
784 mv_gpio_intr_handler(dev, pin);
786 /* Toggle polarity for next edge. */
787 mv_gpio_polarity(dev, pin, 0, 1);
790 callout_deactivate(sc->debounce_callouts[pin]);
798 mv_gpio_debounced_state_set(device_t dev, int pin, uint8_t new_state)
801 struct mv_gpio_softc *sc;
802 sc = (struct mv_gpio_softc *)device_get_softc(dev);
804 MV_GPIO_ASSERT_LOCKED();
806 if (pin >= GPIO_PINS_PER_REG) {
807 old_state = &sc->debounced_state_hi;
808 pin -= GPIO_PINS_PER_REG;
810 old_state = &sc->debounced_state_lo;
813 *old_state |= (1 << pin);
815 *old_state &= ~(1 << pin);
819 mv_gpio_debounced_state_get(device_t dev, int pin)
822 struct mv_gpio_softc *sc;
823 sc = (struct mv_gpio_softc *)device_get_softc(dev);
825 MV_GPIO_ASSERT_LOCKED();
827 if (pin >= GPIO_PINS_PER_REG) {
828 state = &sc->debounced_state_hi;
829 pin -= GPIO_PINS_PER_REG;
831 state = &sc->debounced_state_lo;
833 return (*state & (1 << pin));
837 mv_gpio_out(device_t dev, uint32_t pin, uint8_t val, uint8_t enable)
839 struct mv_gpio_softc *sc;
840 sc = (struct mv_gpio_softc *)device_get_softc(dev);
844 mv_gpio_value_set(dev, pin, val);
845 mv_gpio_out_en(dev, pin, enable);
851 mv_gpio_in(device_t dev, uint32_t pin)
854 struct mv_gpio_softc *sc;
855 sc = (struct mv_gpio_softc *)device_get_softc(dev);
857 MV_GPIO_ASSERT_LOCKED();
859 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) {
860 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW)
861 state = (mv_gpio_debounced_state_get(dev, pin) ? 0 : 1);
863 state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0);
864 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) {
865 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW)
866 state = (mv_gpio_value_get(dev, pin, 1) ? 0 : 1);
868 state = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
870 state = (mv_gpio_value_get(dev, pin, 0) ? 1 : 0);
876 mv_gpio_reg_read(device_t dev, uint32_t reg)
878 struct mv_gpio_softc *sc;
879 sc = (struct mv_gpio_softc *)device_get_softc(dev);
881 return (bus_space_read_4(sc->bst, sc->bsh, sc->offset + reg));
885 mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val)
887 struct mv_gpio_softc *sc;
888 sc = (struct mv_gpio_softc *)device_get_softc(dev);
890 bus_space_write_4(sc->bst, sc->bsh, sc->offset + reg, val);
894 mv_gpio_reg_set(device_t dev, uint32_t reg, uint32_t pin)
898 reg_val = mv_gpio_reg_read(dev, reg);
899 reg_val |= GPIO(pin);
900 mv_gpio_reg_write(dev, reg, reg_val);
904 mv_gpio_reg_clear(device_t dev, uint32_t reg, uint32_t pin)
908 reg_val = mv_gpio_reg_read(dev, reg);
909 reg_val &= ~(GPIO(pin));
910 mv_gpio_reg_write(dev, reg, reg_val);
914 mv_gpio_out_en(device_t dev, uint32_t pin, uint8_t enable)
917 struct mv_gpio_softc *sc;
918 sc = (struct mv_gpio_softc *)device_get_softc(dev);
920 if (pin >= sc->pin_num)
923 reg = GPIO_DATA_OUT_EN_CTRL;
926 mv_gpio_reg_clear(dev, reg, pin);
928 mv_gpio_reg_set(dev, reg, pin);
932 mv_gpio_blink(device_t dev, uint32_t pin, uint8_t enable)
935 struct mv_gpio_softc *sc;
936 sc = (struct mv_gpio_softc *)device_get_softc(dev);
938 if (pin >= sc->pin_num)
944 mv_gpio_reg_set(dev, reg, pin);
946 mv_gpio_reg_clear(dev, reg, pin);
950 mv_gpio_polarity(device_t dev, uint32_t pin, uint8_t enable, uint8_t toggle)
952 uint32_t reg, reg_val;
953 struct mv_gpio_softc *sc;
954 sc = (struct mv_gpio_softc *)device_get_softc(dev);
956 if (pin >= sc->pin_num)
959 reg = GPIO_DATA_IN_POLAR;
962 reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin);
964 mv_gpio_reg_clear(dev, reg, pin);
966 mv_gpio_reg_set(dev, reg, pin);
968 mv_gpio_reg_set(dev, reg, pin);
970 mv_gpio_reg_clear(dev, reg, pin);
974 mv_gpio_level(device_t dev, uint32_t pin, uint8_t enable)
977 struct mv_gpio_softc *sc;
978 sc = (struct mv_gpio_softc *)device_get_softc(dev);
980 if (pin >= sc->pin_num)
983 reg = GPIO_INT_LEV_MASK;
986 mv_gpio_reg_set(dev, reg, pin);
988 mv_gpio_reg_clear(dev, reg, pin);
992 mv_gpio_edge(device_t dev, uint32_t pin, uint8_t enable)
995 struct mv_gpio_softc *sc;
996 sc = (struct mv_gpio_softc *)device_get_softc(dev);
998 if (pin >= sc->pin_num)
1001 reg = GPIO_INT_EDGE_MASK;
1004 mv_gpio_reg_set(dev, reg, pin);
1006 mv_gpio_reg_clear(dev, reg, pin);
1010 mv_gpio_int_ack(struct mv_gpio_pindev *s)
1013 struct mv_gpio_softc *sc;
1014 sc = (struct mv_gpio_softc *)device_get_softc(s->dev);
1017 if (pin >= sc->pin_num)
1020 reg = GPIO_INT_CAUSE;
1022 mv_gpio_reg_clear(s->dev, reg, pin);
1026 mv_gpio_value_get(device_t dev, uint32_t pin, uint8_t exclude_polar)
1028 uint32_t reg, polar_reg, reg_val, polar_reg_val;
1029 struct mv_gpio_softc *sc;
1030 sc = (struct mv_gpio_softc *)device_get_softc(dev);
1032 if (pin >= sc->pin_num)
1036 polar_reg = GPIO_DATA_IN_POLAR;
1038 reg_val = mv_gpio_reg_read(dev, reg);
1040 if (exclude_polar) {
1041 polar_reg_val = mv_gpio_reg_read(dev, polar_reg);
1042 return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin)));
1044 return (reg_val & GPIO(pin));
1048 mv_gpio_value_set(device_t dev, uint32_t pin, uint8_t val)
1051 struct mv_gpio_softc *sc;
1052 sc = (struct mv_gpio_softc *)device_get_softc(dev);
1054 MV_GPIO_ASSERT_LOCKED();
1056 if (pin >= sc->pin_num)
1059 reg = GPIO_DATA_OUT;
1062 mv_gpio_reg_set(dev, reg, pin);
1064 mv_gpio_reg_clear(dev, reg, pin);
1068 * GPIO interface methods
1072 mv_gpio_pin_max(device_t dev, int *maxpin)
1074 struct mv_gpio_softc *sc;
1078 sc = device_get_softc(dev);
1079 *maxpin = sc->pin_num;
1085 mv_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
1087 struct mv_gpio_softc *sc = device_get_softc(dev);
1091 if (pin >= sc->pin_num)
1095 *caps = sc->gpio_setup[pin].gp_caps;
1102 mv_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
1104 struct mv_gpio_softc *sc = device_get_softc(dev);
1108 if (pin >= sc->pin_num)
1112 *flags = sc->gpio_setup[pin].gp_flags;
1119 mv_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
1121 struct mv_gpio_softc *sc = device_get_softc(dev);
1125 if (pin >= sc->pin_num)
1129 memcpy(name, sc->gpio_setup[pin].gp_name, GPIOMAXNAME);
1136 mv_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
1139 struct mv_gpio_softc *sc = device_get_softc(dev);
1140 if (pin >= sc->pin_num)
1143 /* Check for unwanted flags. */
1144 if ((flags & sc->gpio_setup[pin].gp_caps) != flags)
1147 ret = mv_gpio_configure(dev, pin, flags, ~0);
1153 mv_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
1155 struct mv_gpio_softc *sc = device_get_softc(dev);
1156 if (pin >= sc->pin_num)
1160 mv_gpio_value_set(dev, pin, value);
1167 mv_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
1169 struct mv_gpio_softc *sc = device_get_softc(dev);
1173 if (pin >= sc->pin_num)
1177 *value = mv_gpio_in(dev, pin);
1184 mv_gpio_pin_toggle(device_t dev, uint32_t pin)
1186 struct mv_gpio_softc *sc = device_get_softc(dev);
1188 if (pin >= sc->pin_num)
1192 value = mv_gpio_in(dev, pin);
1193 value = (~value) & 1;
1194 mv_gpio_value_set(dev, pin, value);
1201 mv_gpio_get_bus(device_t dev)
1203 struct mv_gpio_softc *sc = device_get_softc(dev);
1205 return (sc->sc_busdev);
1209 mv_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
1210 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
1212 struct mv_gpio_softc *sc = device_get_softc(bus);
1214 if (gpios[0] >= sc->pin_num)
1219 mv_gpio_configure(bus, *pin, *flags, ~0);