2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 Benno Rice.
5 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
6 * Copyright (c) 2017 Semihalf.
9 * Adapted and extended for Marvell SoCs by Semihalf.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/interrupt.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/mutex.h>
47 #include <sys/queue.h>
48 #include <sys/timetc.h>
49 #include <sys/callout.h>
51 #include <machine/bus.h>
52 #include <machine/intr.h>
54 #include <dev/gpio/gpiobusvar.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
58 #include <arm/mv/mvvar.h>
59 #include <arm/mv/mvreg.h>
63 #define GPIO_MAX_INTR_COUNT 8
64 #define GPIO_PINS_PER_REG 32
65 #define GPIO_GENERIC_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
66 GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \
67 GPIO_PIN_TRISTATE | GPIO_PIN_PULLUP | \
68 GPIO_PIN_PULLDOWN | GPIO_PIN_INVIN | \
71 #define DEBOUNCE_CHECK_MS 1
72 #define DEBOUNCE_LO_HI_MS 2
73 #define DEBOUNCE_HI_LO_MS 2
74 #define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS)
76 struct mv_gpio_softc {
79 struct resource * mem_res;
81 struct resource * irq_res[GPIO_MAX_INTR_COUNT];
82 int irq_rid[GPIO_MAX_INTR_COUNT];
83 struct intr_event * gpio_events[MV_GPIO_MAX_NPINS];
84 void *ih_cookie[GPIO_MAX_INTR_COUNT];
86 bus_space_handle_t bsh;
89 uint8_t pin_num; /* number of GPIO pins */
90 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */
91 struct gpio_pin gpio_setup[MV_GPIO_MAX_NPINS];
93 /* Used for debouncing. */
94 uint32_t debounced_state_lo;
95 uint32_t debounced_state_hi;
96 struct callout **debounce_callouts;
97 int *debounce_counters;
100 struct mv_gpio_pindev {
105 static int mv_gpio_probe(device_t);
106 static int mv_gpio_attach(device_t);
107 static int mv_gpio_intr(device_t, void *);
109 static void mv_gpio_double_edge_init(device_t, int);
111 static int mv_gpio_debounce_setup(device_t, int);
112 static int mv_gpio_debounce_prepare(device_t, int);
113 static int mv_gpio_debounce_init(device_t, int);
114 static void mv_gpio_debounce_start(device_t, int);
115 static void mv_gpio_debounce(void *);
116 static void mv_gpio_debounced_state_set(device_t, int, uint8_t);
117 static uint32_t mv_gpio_debounced_state_get(device_t, int);
119 static void mv_gpio_exec_intr_handlers(device_t, uint32_t, int);
120 static void mv_gpio_intr_handler(device_t, int);
121 static uint32_t mv_gpio_reg_read(device_t, uint32_t);
122 static void mv_gpio_reg_write(device_t, uint32_t, uint32_t);
123 static void mv_gpio_reg_set(device_t, uint32_t, uint32_t);
124 static void mv_gpio_reg_clear(device_t, uint32_t, uint32_t);
126 static void mv_gpio_blink(device_t, uint32_t, uint8_t);
127 static void mv_gpio_polarity(device_t, uint32_t, uint8_t, uint8_t);
128 static void mv_gpio_level(device_t, uint32_t, uint8_t);
129 static void mv_gpio_edge(device_t, uint32_t, uint8_t);
130 static void mv_gpio_out_en(device_t, uint32_t, uint8_t);
131 static void mv_gpio_int_ack(struct mv_gpio_pindev *);
132 static void mv_gpio_value_set(device_t, uint32_t, uint8_t);
133 static uint32_t mv_gpio_value_get(device_t, uint32_t, uint8_t);
135 static void mv_gpio_intr_mask(struct mv_gpio_pindev *);
136 static void mv_gpio_intr_unmask(struct mv_gpio_pindev *);
138 void mv_gpio_finish_intrhandler(struct mv_gpio_pindev *);
139 int mv_gpio_setup_intrhandler(device_t, const char *,
140 driver_filter_t *, void (*)(void *), void *,
142 int mv_gpio_configure(device_t, uint32_t, uint32_t, uint32_t);
143 void mv_gpio_out(device_t, uint32_t, uint8_t, uint8_t);
144 uint8_t mv_gpio_in(device_t, uint32_t);
149 static device_t mv_gpio_get_bus(device_t);
150 static int mv_gpio_pin_max(device_t, int *);
151 static int mv_gpio_pin_getcaps(device_t, uint32_t, uint32_t *);
152 static int mv_gpio_pin_getflags(device_t, uint32_t, uint32_t *);
153 static int mv_gpio_pin_getname(device_t, uint32_t, char *);
154 static int mv_gpio_pin_setflags(device_t, uint32_t, uint32_t);
155 static int mv_gpio_pin_set(device_t, uint32_t, unsigned int);
156 static int mv_gpio_pin_get(device_t, uint32_t, unsigned int *);
157 static int mv_gpio_pin_toggle(device_t, uint32_t);
158 static int mv_gpio_map_gpios(device_t, phandle_t, phandle_t,
159 int, pcell_t *, uint32_t *, uint32_t *);
161 #define MV_GPIO_LOCK() mtx_lock_spin(&sc->mutex)
162 #define MV_GPIO_UNLOCK() mtx_unlock_spin(&sc->mutex)
163 #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&sc->mutex, MA_OWNED)
165 static device_method_t mv_gpio_methods[] = {
166 DEVMETHOD(device_probe, mv_gpio_probe),
167 DEVMETHOD(device_attach, mv_gpio_attach),
170 DEVMETHOD(gpio_get_bus, mv_gpio_get_bus),
171 DEVMETHOD(gpio_pin_max, mv_gpio_pin_max),
172 DEVMETHOD(gpio_pin_getname, mv_gpio_pin_getname),
173 DEVMETHOD(gpio_pin_getflags, mv_gpio_pin_getflags),
174 DEVMETHOD(gpio_pin_getcaps, mv_gpio_pin_getcaps),
175 DEVMETHOD(gpio_pin_setflags, mv_gpio_pin_setflags),
176 DEVMETHOD(gpio_pin_get, mv_gpio_pin_get),
177 DEVMETHOD(gpio_pin_set, mv_gpio_pin_set),
178 DEVMETHOD(gpio_pin_toggle, mv_gpio_pin_toggle),
179 DEVMETHOD(gpio_map_gpios, mv_gpio_map_gpios),
184 static driver_t mv_gpio_driver = {
187 sizeof(struct mv_gpio_softc),
190 static devclass_t mv_gpio_devclass;
192 EARLY_DRIVER_MODULE(mv_gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0,
193 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST);
195 struct ofw_compat_data compat_data[] = {
197 { "marvell,orion-gpio", 1 },
202 mv_gpio_probe(device_t dev)
204 if (!ofw_bus_status_okay(dev))
207 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
210 device_set_desc(dev, "Marvell Integrated GPIO Controller");
215 mv_gpio_setup_interrupts(struct mv_gpio_softc *sc, phandle_t node)
221 /* Find root interrupt controller */
222 iparent = ofw_bus_find_iparent(node);
224 device_printf(sc->dev, "No interrupt-parrent found. "
228 /* While at parent - store interrupt cells prop */
229 if (OF_searchencprop(OF_node_from_xref(iparent),
230 "#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) {
231 device_printf(sc->dev, "DTB: Missing #interrupt-cells "
232 "property in interrupt parent node\n");
237 size = OF_getproplen(node, "interrupts");
239 size = size / sizeof(pcell_t);
240 size = size / irq_cells;
242 device_printf(sc->dev, "%d IRQs available\n", sc->irq_num);
244 device_printf(sc->dev, "ERROR: no interrupts entry found!\n");
248 for (i = 0; i < sc->irq_num; i++) {
250 sc->irq_res[i] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
251 &sc->irq_rid[i], RF_ACTIVE);
252 if (!sc->irq_res[i]) {
253 mtx_destroy(&sc->mutex);
254 device_printf(sc->dev,
255 "could not allocate gpio%d interrupt\n", i+1);
260 device_printf(sc->dev, "Disable interrupts (offset = %x + EDGE(0x18)\n", sc->offset);
261 /* Disable all interrupts */
262 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_EDGE_MASK, 0);
263 device_printf(sc->dev, "Disable interrupts (offset = %x + LEV(0x1C))\n", sc->offset);
264 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_LEV_MASK, 0);
266 for (i = 0; i < sc->irq_num; i++) {
267 device_printf(sc->dev, "Setup intr %d\n", i);
268 if (bus_setup_intr(sc->dev, sc->irq_res[i],
270 (driver_filter_t *)mv_gpio_intr, NULL,
271 sc, &sc->ih_cookie[i]) != 0) {
272 mtx_destroy(&sc->mutex);
273 bus_release_resource(sc->dev, SYS_RES_IRQ,
274 sc->irq_rid[i], sc->irq_res[i]);
275 device_printf(sc->dev, "could not set up intr %d\n", i);
280 /* Clear interrupt status. */
281 device_printf(sc->dev, "Clear int status (offset = %x)\n", sc->offset);
282 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_CAUSE, 0);
284 sc->debounce_callouts = (struct callout **)malloc(sc->pin_num *
285 sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO);
286 if (sc->debounce_callouts == NULL)
289 sc->debounce_counters = (int *)malloc(sc->pin_num * sizeof(int),
291 if (sc->debounce_counters == NULL)
298 mv_gpio_attach(device_t dev)
301 struct mv_gpio_softc *sc;
305 sc = (struct mv_gpio_softc *)device_get_softc(dev);
309 node = ofw_bus_get_node(dev);
312 if (OF_getencprop(node, "pin-count", &pincnt, sizeof(pcell_t)) >= 0 ||
313 OF_getencprop(node, "ngpios", &pincnt, sizeof(pcell_t)) >= 0) {
314 sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS);
316 device_printf(dev, "%d pins available\n", sc->pin_num);
318 device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n");
322 if (OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset)) == -1)
325 /* Assign generic capabilities to every gpio pin */
326 for(i = 0; i < sc->pin_num; i++)
327 sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP;
329 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN);
332 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
333 RF_ACTIVE | RF_SHAREABLE );
336 mtx_destroy(&sc->mutex);
337 device_printf(dev, "could not allocate memory window\n");
341 sc->bst = rman_get_bustag(sc->mem_res);
342 sc->bsh = rman_get_bushandle(sc->mem_res);
344 rv = mv_gpio_setup_interrupts(sc, node);
348 sc->sc_busdev = gpiobus_attach_bus(dev);
349 if (sc->sc_busdev == NULL) {
350 mtx_destroy(&sc->mutex);
351 bus_release_resource(dev, SYS_RES_IRQ,
352 sc->irq_rid[i], sc->irq_res[i]);
360 mv_gpio_intr(device_t dev, void *arg)
362 uint32_t int_cause, gpio_val;
363 struct mv_gpio_softc *sc;
364 sc = (struct mv_gpio_softc *)device_get_softc(dev);
369 * According to documentation, edge sensitive interrupts are asserted
370 * when unmasked GPIO_INT_CAUSE register bits are set.
372 int_cause = mv_gpio_reg_read(dev, GPIO_INT_CAUSE);
373 int_cause &= mv_gpio_reg_read(dev, GPIO_INT_EDGE_MASK);
376 * Level sensitive interrupts are asserted when unmasked GPIO_DATA_IN
377 * register bits are set.
379 gpio_val = mv_gpio_reg_read(dev, GPIO_DATA_IN);
380 gpio_val &= mv_gpio_reg_read(dev, GPIO_INT_LEV_MASK);
382 mv_gpio_exec_intr_handlers(dev, int_cause | gpio_val, 0);
386 return (FILTER_HANDLED);
390 * GPIO interrupt handling
394 mv_gpio_finish_intrhandler(struct mv_gpio_pindev *s)
396 /* When we acheive full interrupt support
397 * This function will be opposite to
398 * mv_gpio_setup_intrhandler
401 /* Now it exists only to remind that
402 * there should be place to free mv_gpio_pindev
403 * allocated by mv_gpio_setup_intrhandler
409 mv_gpio_setup_intrhandler(device_t dev, const char *name, driver_filter_t *filt,
410 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep)
412 struct intr_event *event;
414 struct mv_gpio_pindev *s;
415 struct mv_gpio_softc *sc;
416 sc = (struct mv_gpio_softc *)device_get_softc(dev);
417 s = malloc(sizeof(struct mv_gpio_pindev), M_DEVBUF, M_NOWAIT | M_ZERO);
419 if (pin < 0 || pin >= sc->pin_num)
421 event = sc->gpio_events[pin];
424 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) {
425 error = mv_gpio_debounce_init(dev, pin);
430 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE)
431 mv_gpio_double_edge_init(dev, pin);
433 error = intr_event_create(&event, (void *)s, 0, pin,
434 (void (*)(void *))mv_gpio_intr_mask,
435 (void (*)(void *))mv_gpio_intr_unmask,
436 (void (*)(void *))mv_gpio_int_ack,
441 sc->gpio_events[pin] = event;
444 intr_event_add_handler(event, name, filt, hand, arg,
445 intr_priority(flags), flags, cookiep);
450 mv_gpio_intr_mask(struct mv_gpio_pindev *s)
452 struct mv_gpio_softc *sc;
453 sc = (struct mv_gpio_softc *)device_get_softc(s->dev);
455 if (s->pin >= sc->pin_num)
460 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE |
461 MV_GPIO_IN_IRQ_DOUBLE_EDGE))
462 mv_gpio_edge(s->dev, s->pin, 0);
464 mv_gpio_level(s->dev, s->pin, 0);
467 * The interrupt has to be acknowledged before scheduling an interrupt
468 * thread. This way we allow for interrupt source to trigger again
469 * (which can happen with shared IRQs e.g. PCI) while processing the
480 mv_gpio_intr_unmask(struct mv_gpio_pindev *s)
482 struct mv_gpio_softc *sc;
483 sc = (struct mv_gpio_softc *)device_get_softc(s->dev);
485 if (s->pin >= sc->pin_num)
490 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE |
491 MV_GPIO_IN_IRQ_DOUBLE_EDGE))
492 mv_gpio_edge(s->dev, s->pin, 1);
494 mv_gpio_level(s->dev, s->pin, 1);
502 mv_gpio_exec_intr_handlers(device_t dev, uint32_t status, int high)
505 struct mv_gpio_softc *sc;
506 sc = (struct mv_gpio_softc *)device_get_softc(dev);
508 MV_GPIO_ASSERT_LOCKED();
511 while (status != 0) {
513 pin = (high ? (i + GPIO_PINS_PER_REG) : i);
514 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE)
515 mv_gpio_debounce_start(dev, pin);
516 else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) {
517 mv_gpio_polarity(dev, pin, 0, 1);
518 mv_gpio_intr_handler(dev, pin);
520 mv_gpio_intr_handler(dev, pin);
528 mv_gpio_intr_handler(device_t dev, int pin)
531 struct intr_irqsrc isrc;
532 struct mv_gpio_softc *sc;
533 sc = (struct mv_gpio_softc *)device_get_softc(dev);
535 MV_GPIO_ASSERT_LOCKED();
538 isrc.isrc_filter = NULL;
540 isrc.isrc_event = sc->gpio_events[pin];
542 if (isrc.isrc_event == NULL ||
543 CK_SLIST_EMPTY(&isrc.isrc_event->ie_handlers))
546 intr_isrc_dispatch(&isrc, NULL);
551 mv_gpio_configure(device_t dev, uint32_t pin, uint32_t flags, uint32_t mask)
554 struct mv_gpio_softc *sc;
555 sc = (struct mv_gpio_softc *)device_get_softc(dev);
558 if (pin >= sc->pin_num)
561 /* check flags consistency */
562 if (((flags & mask) & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) ==
563 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
566 if (mask & MV_GPIO_IN_DEBOUNCE) {
567 if (sc->irq_num == 0)
569 error = mv_gpio_debounce_prepare(dev, pin);
576 if ((mask & flags) & GPIO_PIN_INPUT)
577 mv_gpio_out_en(dev, pin, 0);
578 if ((mask & flags) & GPIO_PIN_OUTPUT) {
579 if ((flags & mask) & GPIO_PIN_OPENDRAIN)
580 mv_gpio_value_set(dev, pin, 0);
582 mv_gpio_value_set(dev, pin, 1);
583 mv_gpio_out_en(dev, pin, 1);
586 if (mask & MV_GPIO_OUT_BLINK)
587 mv_gpio_blink(dev, pin, flags & MV_GPIO_OUT_BLINK);
588 if (mask & MV_GPIO_IN_POL_LOW)
589 mv_gpio_polarity(dev, pin, flags & MV_GPIO_IN_POL_LOW, 0);
590 if (mask & MV_GPIO_IN_DEBOUNCE) {
591 error = mv_gpio_debounce_setup(dev, pin);
598 sc->gpio_setup[pin].gp_flags &= ~(mask);
599 sc->gpio_setup[pin].gp_flags |= (flags & mask);
607 mv_gpio_double_edge_init(device_t dev, int pin)
610 struct mv_gpio_softc *sc;
611 sc = (struct mv_gpio_softc *)device_get_softc(dev);
613 MV_GPIO_ASSERT_LOCKED();
615 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
618 mv_gpio_polarity(dev, pin, 1, 0);
620 mv_gpio_polarity(dev, pin, 0, 0);
624 mv_gpio_debounce_setup(device_t dev, int pin)
627 struct mv_gpio_softc *sc;
629 sc = (struct mv_gpio_softc *)device_get_softc(dev);
631 MV_GPIO_ASSERT_LOCKED();
633 c = sc->debounce_callouts[pin];
637 if (callout_active(c))
638 callout_deactivate(c);
646 mv_gpio_debounce_prepare(device_t dev, int pin)
649 struct mv_gpio_softc *sc;
651 sc = (struct mv_gpio_softc *)device_get_softc(dev);
653 c = sc->debounce_callouts[pin];
655 c = (struct callout *)malloc(sizeof(struct callout),
657 sc->debounce_callouts[pin] = c;
667 mv_gpio_debounce_init(device_t dev, int pin)
671 struct mv_gpio_softc *sc;
673 sc = (struct mv_gpio_softc *)device_get_softc(dev);
675 MV_GPIO_ASSERT_LOCKED();
677 cnt = &sc->debounce_counters[pin];
678 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
680 mv_gpio_polarity(dev, pin, 1, 0);
681 *cnt = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS;
683 mv_gpio_polarity(dev, pin, 0, 0);
684 *cnt = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS;
687 mv_gpio_debounced_state_set(dev, pin, raw_read);
693 mv_gpio_debounce_start(device_t dev, int pin)
696 struct mv_gpio_pindev s = {dev, pin};
697 struct mv_gpio_pindev *sd;
698 struct mv_gpio_softc *sc;
699 sc = (struct mv_gpio_softc *)device_get_softc(dev);
701 MV_GPIO_ASSERT_LOCKED();
703 c = sc->debounce_callouts[pin];
709 if (callout_pending(c) || callout_active(c)) {
714 sd = (struct mv_gpio_pindev *)malloc(sizeof(struct mv_gpio_pindev),
723 callout_reset(c, DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, sd);
727 mv_gpio_debounce(void *arg)
729 uint8_t raw_read, last_state;
732 int *debounce_counter;
733 struct mv_gpio_softc *sc;
734 struct mv_gpio_pindev *s;
736 s = (struct mv_gpio_pindev *)arg;
739 sc = (struct mv_gpio_softc *)device_get_softc(dev);
743 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
744 last_state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0);
745 debounce_counter = &sc->debounce_counters[pin];
747 if (raw_read == last_state) {
749 *debounce_counter = DEBOUNCE_HI_LO_MS /
752 *debounce_counter = DEBOUNCE_LO_HI_MS /
755 callout_reset(sc->debounce_callouts[pin],
756 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg);
758 *debounce_counter = *debounce_counter - 1;
759 if (*debounce_counter != 0)
760 callout_reset(sc->debounce_callouts[pin],
761 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg);
763 mv_gpio_debounced_state_set(dev, pin, raw_read);
766 *debounce_counter = DEBOUNCE_HI_LO_MS /
769 *debounce_counter = DEBOUNCE_LO_HI_MS /
772 if (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) &&
774 (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) == 0) &&
776 (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE))
777 mv_gpio_intr_handler(dev, pin);
779 /* Toggle polarity for next edge. */
780 mv_gpio_polarity(dev, pin, 0, 1);
783 callout_deactivate(sc->debounce_callouts[pin]);
791 mv_gpio_debounced_state_set(device_t dev, int pin, uint8_t new_state)
794 struct mv_gpio_softc *sc;
795 sc = (struct mv_gpio_softc *)device_get_softc(dev);
797 MV_GPIO_ASSERT_LOCKED();
799 if (pin >= GPIO_PINS_PER_REG) {
800 old_state = &sc->debounced_state_hi;
801 pin -= GPIO_PINS_PER_REG;
803 old_state = &sc->debounced_state_lo;
806 *old_state |= (1 << pin);
808 *old_state &= ~(1 << pin);
812 mv_gpio_debounced_state_get(device_t dev, int pin)
815 struct mv_gpio_softc *sc;
816 sc = (struct mv_gpio_softc *)device_get_softc(dev);
818 MV_GPIO_ASSERT_LOCKED();
820 if (pin >= GPIO_PINS_PER_REG) {
821 state = &sc->debounced_state_hi;
822 pin -= GPIO_PINS_PER_REG;
824 state = &sc->debounced_state_lo;
826 return (*state & (1 << pin));
830 mv_gpio_out(device_t dev, uint32_t pin, uint8_t val, uint8_t enable)
832 struct mv_gpio_softc *sc;
833 sc = (struct mv_gpio_softc *)device_get_softc(dev);
837 mv_gpio_value_set(dev, pin, val);
838 mv_gpio_out_en(dev, pin, enable);
844 mv_gpio_in(device_t dev, uint32_t pin)
847 struct mv_gpio_softc *sc;
848 sc = (struct mv_gpio_softc *)device_get_softc(dev);
850 MV_GPIO_ASSERT_LOCKED();
852 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) {
853 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW)
854 state = (mv_gpio_debounced_state_get(dev, pin) ? 0 : 1);
856 state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0);
857 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) {
858 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW)
859 state = (mv_gpio_value_get(dev, pin, 1) ? 0 : 1);
861 state = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0);
863 state = (mv_gpio_value_get(dev, pin, 0) ? 1 : 0);
869 mv_gpio_reg_read(device_t dev, uint32_t reg)
871 struct mv_gpio_softc *sc;
872 sc = (struct mv_gpio_softc *)device_get_softc(dev);
874 return (bus_space_read_4(sc->bst, sc->bsh, sc->offset + reg));
878 mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val)
880 struct mv_gpio_softc *sc;
881 sc = (struct mv_gpio_softc *)device_get_softc(dev);
883 bus_space_write_4(sc->bst, sc->bsh, sc->offset + reg, val);
887 mv_gpio_reg_set(device_t dev, uint32_t reg, uint32_t pin)
891 reg_val = mv_gpio_reg_read(dev, reg);
892 reg_val |= GPIO(pin);
893 mv_gpio_reg_write(dev, reg, reg_val);
897 mv_gpio_reg_clear(device_t dev, uint32_t reg, uint32_t pin)
901 reg_val = mv_gpio_reg_read(dev, reg);
902 reg_val &= ~(GPIO(pin));
903 mv_gpio_reg_write(dev, reg, reg_val);
907 mv_gpio_out_en(device_t dev, uint32_t pin, uint8_t enable)
910 struct mv_gpio_softc *sc;
911 sc = (struct mv_gpio_softc *)device_get_softc(dev);
913 if (pin >= sc->pin_num)
916 reg = GPIO_DATA_OUT_EN_CTRL;
919 mv_gpio_reg_clear(dev, reg, pin);
921 mv_gpio_reg_set(dev, reg, pin);
925 mv_gpio_blink(device_t dev, uint32_t pin, uint8_t enable)
928 struct mv_gpio_softc *sc;
929 sc = (struct mv_gpio_softc *)device_get_softc(dev);
931 if (pin >= sc->pin_num)
937 mv_gpio_reg_set(dev, reg, pin);
939 mv_gpio_reg_clear(dev, reg, pin);
943 mv_gpio_polarity(device_t dev, uint32_t pin, uint8_t enable, uint8_t toggle)
945 uint32_t reg, reg_val;
946 struct mv_gpio_softc *sc;
947 sc = (struct mv_gpio_softc *)device_get_softc(dev);
949 if (pin >= sc->pin_num)
952 reg = GPIO_DATA_IN_POLAR;
955 reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin);
957 mv_gpio_reg_clear(dev, reg, pin);
959 mv_gpio_reg_set(dev, reg, pin);
961 mv_gpio_reg_set(dev, reg, pin);
963 mv_gpio_reg_clear(dev, reg, pin);
967 mv_gpio_level(device_t dev, uint32_t pin, uint8_t enable)
970 struct mv_gpio_softc *sc;
971 sc = (struct mv_gpio_softc *)device_get_softc(dev);
973 if (pin >= sc->pin_num)
976 reg = GPIO_INT_LEV_MASK;
979 mv_gpio_reg_set(dev, reg, pin);
981 mv_gpio_reg_clear(dev, reg, pin);
985 mv_gpio_edge(device_t dev, uint32_t pin, uint8_t enable)
988 struct mv_gpio_softc *sc;
989 sc = (struct mv_gpio_softc *)device_get_softc(dev);
991 if (pin >= sc->pin_num)
994 reg = GPIO_INT_EDGE_MASK;
997 mv_gpio_reg_set(dev, reg, pin);
999 mv_gpio_reg_clear(dev, reg, pin);
1003 mv_gpio_int_ack(struct mv_gpio_pindev *s)
1006 struct mv_gpio_softc *sc;
1007 sc = (struct mv_gpio_softc *)device_get_softc(s->dev);
1010 if (pin >= sc->pin_num)
1013 reg = GPIO_INT_CAUSE;
1015 mv_gpio_reg_clear(s->dev, reg, pin);
1019 mv_gpio_value_get(device_t dev, uint32_t pin, uint8_t exclude_polar)
1021 uint32_t reg, polar_reg, reg_val, polar_reg_val;
1022 struct mv_gpio_softc *sc;
1023 sc = (struct mv_gpio_softc *)device_get_softc(dev);
1025 if (pin >= sc->pin_num)
1029 polar_reg = GPIO_DATA_IN_POLAR;
1031 reg_val = mv_gpio_reg_read(dev, reg);
1033 if (exclude_polar) {
1034 polar_reg_val = mv_gpio_reg_read(dev, polar_reg);
1035 return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin)));
1037 return (reg_val & GPIO(pin));
1041 mv_gpio_value_set(device_t dev, uint32_t pin, uint8_t val)
1044 struct mv_gpio_softc *sc;
1045 sc = (struct mv_gpio_softc *)device_get_softc(dev);
1047 MV_GPIO_ASSERT_LOCKED();
1049 if (pin >= sc->pin_num)
1052 reg = GPIO_DATA_OUT;
1055 mv_gpio_reg_set(dev, reg, pin);
1057 mv_gpio_reg_clear(dev, reg, pin);
1061 * GPIO interface methods
1065 mv_gpio_pin_max(device_t dev, int *maxpin)
1067 struct mv_gpio_softc *sc;
1071 sc = device_get_softc(dev);
1072 *maxpin = sc->pin_num;
1078 mv_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
1080 struct mv_gpio_softc *sc = device_get_softc(dev);
1084 if (pin >= sc->pin_num)
1088 *caps = sc->gpio_setup[pin].gp_caps;
1095 mv_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
1097 struct mv_gpio_softc *sc = device_get_softc(dev);
1101 if (pin >= sc->pin_num)
1105 *flags = sc->gpio_setup[pin].gp_flags;
1112 mv_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
1114 struct mv_gpio_softc *sc = device_get_softc(dev);
1118 if (pin >= sc->pin_num)
1122 memcpy(name, sc->gpio_setup[pin].gp_name, GPIOMAXNAME);
1129 mv_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
1132 struct mv_gpio_softc *sc = device_get_softc(dev);
1133 if (pin >= sc->pin_num)
1136 /* Check for unwanted flags. */
1137 if ((flags & sc->gpio_setup[pin].gp_caps) != flags)
1140 ret = mv_gpio_configure(dev, pin, flags, ~0);
1146 mv_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
1148 struct mv_gpio_softc *sc = device_get_softc(dev);
1149 if (pin >= sc->pin_num)
1153 mv_gpio_value_set(dev, pin, value);
1160 mv_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
1162 struct mv_gpio_softc *sc = device_get_softc(dev);
1166 if (pin >= sc->pin_num)
1170 *value = mv_gpio_in(dev, pin);
1177 mv_gpio_pin_toggle(device_t dev, uint32_t pin)
1179 struct mv_gpio_softc *sc = device_get_softc(dev);
1181 if (pin >= sc->pin_num)
1185 value = mv_gpio_in(dev, pin);
1186 value = (~value) & 1;
1187 mv_gpio_value_set(dev, pin, value);
1194 mv_gpio_get_bus(device_t dev)
1196 struct mv_gpio_softc *sc = device_get_softc(dev);
1198 return (sc->sc_busdev);
1202 mv_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
1203 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
1205 struct mv_gpio_softc *sc = device_get_softc(bus);
1207 if (gpios[0] >= sc->pin_num)
1212 mv_gpio_configure(bus, *pin, *flags, ~0);