2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 Benno Rice.
5 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
6 * Copyright (c) 2012 Semihalf.
9 * Developed by Semihalf.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
32 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include "opt_platform.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/kernel.h>
44 #include <sys/cpuset.h>
47 #include <sys/module.h>
49 #include <sys/mutex.h>
54 #include <machine/bus.h>
55 #include <machine/intr.h>
56 #include <machine/smp.h>
58 #include <arm/mv/mvvar.h>
59 #include <arm/mv/mvreg.h>
61 #include <dev/ofw/ofw_bus.h>
62 #include <dev/ofw/ofw_bus_subr.h>
63 #include <dev/fdt/fdt_common.h>
70 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \
71 printf(fmt,##args); } while (0)
73 #define debugf(fmt, args...)
76 #define MPIC_INT_LOCAL 3
77 #define MPIC_INT_ERR 4
78 #define MPIC_INT_MSI 96
80 #define MPIC_IRQ_MASK 0x3ff
83 #define MPIC_SOFT_INT 0x4
84 #define MPIC_SOFT_INT_DRBL1 (1 << 5)
85 #define MPIC_ERR_CAUSE 0x20
88 #define MPIC_INT_CTL(irq) (0x100 + (irq)*4)
90 #define MPIC_INT_IRQ_FIQ_MASK(cpuid) (0x101 << (cpuid))
91 #define MPIC_CTRL_NIRQS(ctrl) (((ctrl) >> 2) & 0x3ff)
93 #define MPIC_IN_DRBL 0x08
94 #define MPIC_IN_DRBL_MASK 0x0c
95 #define MPIC_PPI_CAUSE 0x10
97 #define MPIC_IIACK 0x44
100 #define MPIC_ERR_MASK 0x50
101 #define MPIC_LOCAL_MASK 0x54
102 #define MPIC_CPU(n) (n) * 0x100
106 struct mv_mpic_irqsrc {
107 struct intr_irqsrc mmi_isrc;
111 struct mv_mpic_softc {
113 struct resource * mpic_res[4];
114 bus_space_tag_t mpic_bst;
115 bus_space_handle_t mpic_bsh;
116 bus_space_tag_t cpu_bst;
117 bus_space_handle_t cpu_bsh;
118 bus_space_tag_t drbl_bst;
119 bus_space_handle_t drbl_bsh;
121 struct mv_mpic_irqsrc * mpic_isrcs;
126 static struct resource_spec mv_mpic_spec[] = {
127 { SYS_RES_MEMORY, 0, RF_ACTIVE },
128 { SYS_RES_MEMORY, 1, RF_ACTIVE },
129 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
130 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL },
134 static struct ofw_compat_data compat_data[] = {
136 {"marvell,mpic", true},
140 static struct mv_mpic_softc *mv_mpic_sc = NULL;
142 void mpic_send_ipi(int cpus, u_int ipi);
144 static int mv_mpic_probe(device_t);
145 static int mv_mpic_attach(device_t);
146 uint32_t mv_mpic_get_cause(void);
147 uint32_t mv_mpic_get_cause_err(void);
148 uint32_t mv_mpic_get_msi(void);
149 static void mpic_unmask_irq(uintptr_t nb);
150 static void mpic_mask_irq(uintptr_t nb);
151 static void mpic_mask_irq_err(uintptr_t nb);
152 static void mpic_unmask_irq_err(uintptr_t nb);
153 static boolean_t mpic_irq_is_percpu(uintptr_t);
154 static int mpic_intr(void *arg);
155 static void mpic_unmask_msi(void);
156 void mpic_init_secondary(device_t);
157 void mpic_ipi_send(device_t, struct intr_irqsrc*, cpuset_t, u_int);
158 int mpic_ipi_read(int);
159 void mpic_ipi_clear(int);
161 #define MPIC_WRITE(softc, reg, val) \
162 bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val))
163 #define MPIC_READ(softc, reg) \
164 bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg))
166 #define MPIC_CPU_WRITE(softc, reg, val) \
167 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val))
168 #define MPIC_CPU_READ(softc, reg) \
169 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg))
171 #define MPIC_DRBL_WRITE(softc, reg, val) \
172 bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val))
173 #define MPIC_DRBL_READ(softc, reg) \
174 bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg))
177 mv_mpic_probe(device_t dev)
180 if (!ofw_bus_status_okay(dev))
183 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
186 device_set_desc(dev, "Marvell Integrated Interrupt Controller");
191 mv_mpic_register_isrcs(struct mv_mpic_softc *sc)
195 struct intr_irqsrc *isrc;
198 sc->mpic_isrcs = malloc(sc->nirqs * sizeof (*sc->mpic_isrcs), M_DEVBUF,
201 name = device_get_nameunit(sc->sc_dev);
202 for (irq = 0; irq < sc->nirqs; irq++) {
203 sc->mpic_isrcs[irq].mmi_irq = irq;
205 isrc = &sc->mpic_isrcs[irq].mmi_isrc;
206 if (irq < MPIC_PPI) {
207 error = intr_isrc_register(isrc, sc->sc_dev,
208 INTR_ISRCF_PPI, "%s", name);
210 error = intr_isrc_register(isrc, sc->sc_dev, 0, "%s",
214 /* XXX call intr_isrc_deregister() */
215 device_printf(sc->sc_dev, "%s failed", __func__);
223 mv_mpic_attach(device_t dev)
225 struct mv_mpic_softc *sc;
230 sc = (struct mv_mpic_softc *)device_get_softc(dev);
232 if (mv_mpic_sc != NULL)
238 mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN);
240 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res);
242 device_printf(dev, "could not allocate resources\n");
245 if (sc->mpic_res[3] == NULL)
246 device_printf(dev, "No interrupt to use.\n");
248 bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK,
249 mpic_intr, NULL, sc, &sc->intr_hand);
251 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]);
252 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]);
254 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]);
255 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]);
257 if (sc->mpic_res[2] != NULL) {
258 /* This is required only if MSIs are used. */
259 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]);
260 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]);
263 MPIC_WRITE(mv_mpic_sc, MPIC_CTRL, 1);
264 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);
266 val = MPIC_READ(mv_mpic_sc, MPIC_CTRL);
267 sc->nirqs = MPIC_CTRL_NIRQS(val);
269 if (mv_mpic_register_isrcs(sc) != 0) {
270 device_printf(dev, "could not register PIC ISRCs\n");
271 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
275 OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev);
277 if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) {
278 device_printf(dev, "could not register PIC\n");
279 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
285 /* Unmask CPU performance counters overflow irq */
286 for (cpu = 0; cpu < mp_ncpus; cpu++)
287 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CPU(cpu) + MPIC_LOCAL_MASK,
288 (1 << cpu) | MPIC_CPU_READ(mv_mpic_sc,
289 MPIC_CPU(cpu) + MPIC_LOCAL_MASK));
297 struct mv_mpic_softc *sc;
298 uint32_t cause, irqsrc;
303 cpuid = PCPU_GET(cpuid);
306 for (cause = MPIC_CPU_READ(sc, MPIC_PPI_CAUSE); cause > 0;
307 cause >>= 1, irq++) {
309 irqsrc = MPIC_READ(sc, MPIC_INT_CTL(irq));
310 if ((irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)) == 0)
312 if (intr_isrc_dispatch(&sc->mpic_isrcs[irq].mmi_isrc,
313 curthread->td_intr_frame) != 0) {
315 device_printf(sc->sc_dev, "Stray irq %u "
321 return (FILTER_HANDLED);
325 mpic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
329 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq;
334 mpic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
338 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq;
339 mpic_unmask_irq(irq);
343 mpic_map_intr(device_t dev, struct intr_map_data *data,
344 struct intr_irqsrc **isrcp)
346 struct intr_map_data_fdt *daf;
347 struct mv_mpic_softc *sc;
349 if (data->type != INTR_MAP_DATA_FDT)
352 sc = device_get_softc(dev);
353 daf = (struct intr_map_data_fdt *)data;
355 if (daf->ncells !=1 || daf->cells[0] >= sc->nirqs)
358 *isrcp = &sc->mpic_isrcs[daf->cells[0]].mmi_isrc;
363 mpic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
366 mpic_disable_intr(dev, isrc);
370 mpic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
373 mpic_enable_intr(dev, isrc);
377 mpic_post_filter(device_t dev, struct intr_irqsrc *isrc)
381 static device_method_t mv_mpic_methods[] = {
382 DEVMETHOD(device_probe, mv_mpic_probe),
383 DEVMETHOD(device_attach, mv_mpic_attach),
385 DEVMETHOD(pic_disable_intr, mpic_disable_intr),
386 DEVMETHOD(pic_enable_intr, mpic_enable_intr),
387 DEVMETHOD(pic_map_intr, mpic_map_intr),
388 DEVMETHOD(pic_post_filter, mpic_post_filter),
389 DEVMETHOD(pic_post_ithread, mpic_post_ithread),
390 DEVMETHOD(pic_pre_ithread, mpic_pre_ithread),
391 DEVMETHOD(pic_init_secondary, mpic_init_secondary),
392 DEVMETHOD(pic_ipi_send, mpic_ipi_send),
396 static driver_t mv_mpic_driver = {
399 sizeof(struct mv_mpic_softc),
402 static devclass_t mv_mpic_devclass;
404 EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0,
405 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
408 mpic_unmask_msi(void)
411 mpic_unmask_irq(MPIC_INT_MSI);
415 mpic_unmask_irq_err(uintptr_t nb)
420 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, MPIC_INT_ERR);
421 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR);
423 bit_off = nb - ERR_IRQ;
424 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
425 mask |= (1 << bit_off);
426 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
430 mpic_mask_irq_err(uintptr_t nb)
435 bit_off = nb - ERR_IRQ;
436 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
437 mask &= ~(1 << bit_off);
438 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
442 mpic_irq_is_percpu(uintptr_t nb)
451 mpic_unmask_irq(uintptr_t nb)
457 if (nb == MPIC_INT_LOCAL) {
458 for (cpu = 0; cpu < mp_ncpus; cpu++)
459 MPIC_CPU_WRITE(mv_mpic_sc,
460 MPIC_CPU(cpu) + MPIC_ICM, nb);
464 if (mpic_irq_is_percpu(nb))
465 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb);
466 else if (nb < ERR_IRQ)
467 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, nb);
468 else if (nb < MSI_IRQ)
469 mpic_unmask_irq_err(nb);
472 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff);
476 mpic_mask_irq(uintptr_t nb)
482 if (nb == MPIC_INT_LOCAL) {
483 for (cpu = 0; cpu < mp_ncpus; cpu++)
484 MPIC_CPU_WRITE(mv_mpic_sc,
485 MPIC_CPU(cpu) + MPIC_ISM, nb);
489 if (mpic_irq_is_percpu(nb))
490 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb);
491 else if (nb < ERR_IRQ)
492 MPIC_WRITE(mv_mpic_sc, MPIC_ICE, nb);
493 else if (nb < MSI_IRQ)
494 mpic_mask_irq_err(nb);
498 mv_mpic_get_cause(void)
501 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK));
505 mv_mpic_get_cause_err(void)
510 err_cause = MPIC_READ(mv_mpic_sc, MPIC_ERR_CAUSE);
513 bit_off = ffs(err_cause) - 1;
517 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause);
518 return (ERR_IRQ + bit_off);
522 mv_mpic_get_msi(void)
527 KASSERT(mv_mpic_sc->drbl_bst != NULL, ("No doorbell in mv_mpic_get_msi"));
528 cause = MPIC_DRBL_READ(mv_mpic_sc, 0);
531 bit_off = ffs(cause) - 1;
535 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause);
537 cause &= ~(1 << bit_off);
538 MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause);
540 return (MSI_IRQ + bit_off);
544 mv_msi_data(int irq, uint64_t *addr, uint32_t *data)
546 u_long phys, base, size;
550 node = ofw_bus_get_node(mv_mpic_sc->sc_dev);
552 /* Get physical address of register space */
553 error = fdt_get_range(OF_parent(node), 0, &phys, &size);
555 printf("%s: Cannot get register physical address, err:%d",
560 /* Get offset of MPIC register space */
561 error = fdt_regsize(node, &base, &size);
563 printf("%s: Cannot get MPIC register offset, err:%d",
568 *addr = phys + base + MPIC_SOFT_INT;
569 *data = MPIC_SOFT_INT_DRBL1 | irq;
575 mpic_init_secondary(device_t dev)
580 mpic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, u_int ipi)
585 for (i = 0; i < MAXCPU; i++)
586 if (CPU_ISSET(i, &cpus))
587 val |= (1 << (8 + i));
589 MPIC_WRITE(mv_mpic_sc, MPIC_SOFT_INT, val);
593 mpic_ipi_read(int i __unused)
598 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL);
601 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi));
609 mpic_ipi_clear(int ipi)