sys/arm/mv/mpic.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2006 Benno Rice.
   5  * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
   6  * Copyright (c) 2012 Semihalf.
   7  * All rights reserved.
   8  *
   9  * Developed by Semihalf.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
  32  * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30
  33  */
  34
  35 #include <sys/cdefs.h>
  36 __FBSDID("$FreeBSD$");
  37
  38 #include "opt_platform.h"
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/bus.h>
  43 #include <sys/kernel.h>
  44 #include <sys/cpuset.h>
  45 #include <sys/ktr.h>
  46 #include <sys/kdb.h>
  47 #include <sys/module.h>
  48 #include <sys/lock.h>
  49 #include <sys/mutex.h>
  50 #include <sys/rman.h>
  51 #include <sys/proc.h>
  52 #include <sys/smp.h>
  53
  54 #include <machine/bus.h>
  55 #include <machine/intr.h>
  56 #include <machine/smp.h>
  57
  58 #include <arm/mv/mvvar.h>
  59 #include <arm/mv/mvreg.h>
  60
  61 #include <dev/ofw/ofw_bus.h>
  62 #include <dev/ofw/ofw_bus_subr.h>
  63 #include <dev/fdt/fdt_common.h>
  64
  65 #ifdef INTRNG
  66 #include "pic_if.h"
  67 #endif
  68
  69 #ifdef DEBUG
  70 #define debugf(fmt, args...) do { printf("%s(): ", __func__);   \
  71     printf(fmt,##args); } while (0)
  72 #else
  73 #define debugf(fmt, args...)
  74 #endif
  75
  76 #define MPIC_INT_LOCAL                  3
  77 #define MPIC_INT_ERR                    4
  78 #define MPIC_INT_MSI                    96
  79
  80 #define MPIC_IRQ_MASK           0x3ff
  81
  82 #define MPIC_CTRL               0x0
  83 #define MPIC_SOFT_INT           0x4
  84 #define MPIC_SOFT_INT_DRBL1     (1 << 5)
  85 #define MPIC_ERR_CAUSE          0x20
  86 #define MPIC_ISE                0x30
  87 #define MPIC_ICE                0x34
  88 #define MPIC_INT_CTL(irq)       (0x100 + (irq)*4)
  89
  90 #define MPIC_INT_IRQ_FIQ_MASK(cpuid)    (0x101 << (cpuid))
  91 #define MPIC_CTRL_NIRQS(ctrl)   (((ctrl) >> 2) & 0x3ff)
  92
  93 #define MPIC_IN_DRBL            0x08
  94 #define MPIC_IN_DRBL_MASK       0x0c
  95 #define MPIC_PPI_CAUSE          0x10
  96 #define MPIC_CTP                0x40
  97 #define MPIC_IIACK              0x44
  98 #define MPIC_ISM                0x48
  99 #define MPIC_ICM                0x4c
 100 #define MPIC_ERR_MASK           0x50
 101 #define MPIC_LOCAL_MASK         0x54
 102 #define MPIC_CPU(n)             (n) * 0x100
 103
 104 #define MPIC_PPI        32
 105
 106 struct mv_mpic_irqsrc {
 107         struct intr_irqsrc      mmi_isrc;
 108         u_int                   mmi_irq;
 109 };
 110
 111 struct mv_mpic_softc {
 112         device_t                sc_dev;
 113         struct resource *       mpic_res[4];
 114         bus_space_tag_t         mpic_bst;
 115         bus_space_handle_t      mpic_bsh;
 116         bus_space_tag_t         cpu_bst;
 117         bus_space_handle_t      cpu_bsh;
 118         bus_space_tag_t         drbl_bst;
 119         bus_space_handle_t      drbl_bsh;
 120         struct mtx              mtx;
 121         struct mv_mpic_irqsrc * mpic_isrcs;
 122         int                     nirqs;
 123         void *                  intr_hand;
 124 };
 125
 126 static struct resource_spec mv_mpic_spec[] = {
 127         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
 128         { SYS_RES_MEMORY,       1,      RF_ACTIVE },
 129         { SYS_RES_MEMORY,       2,      RF_ACTIVE | RF_OPTIONAL },
 130         { SYS_RES_IRQ,          0,      RF_ACTIVE | RF_OPTIONAL },
 131         { -1, 0 }
 132 };
 133
 134 static struct ofw_compat_data compat_data[] = {
 135         {"mrvl,mpic",           true},
 136         {"marvell,mpic",        true},
 137         {NULL,                  false}
 138 };
 139
 140 static struct mv_mpic_softc *mv_mpic_sc = NULL;
 141
 142 void mpic_send_ipi(int cpus, u_int ipi);
 143
 144 static int      mv_mpic_probe(device_t);
 145 static int      mv_mpic_attach(device_t);
 146 uint32_t        mv_mpic_get_cause(void);
 147 uint32_t        mv_mpic_get_cause_err(void);
 148 uint32_t        mv_mpic_get_msi(void);
 149 static void     mpic_unmask_irq(uintptr_t nb);
 150 static void     mpic_mask_irq(uintptr_t nb);
 151 static void     mpic_mask_irq_err(uintptr_t nb);
 152 static void     mpic_unmask_irq_err(uintptr_t nb);
 153 static boolean_t mpic_irq_is_percpu(uintptr_t);
 154 static int      mpic_intr(void *arg);
 155 static void     mpic_unmask_msi(void);
 156 void mpic_init_secondary(device_t);
 157 void mpic_ipi_send(device_t, struct intr_irqsrc*, cpuset_t, u_int);
 158 int mpic_ipi_read(int);
 159 void mpic_ipi_clear(int);
 160
 161 #define MPIC_WRITE(softc, reg, val) \
 162     bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val))
 163 #define MPIC_READ(softc, reg) \
 164     bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg))
 165
 166 #define MPIC_CPU_WRITE(softc, reg, val) \
 167     bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val))
 168 #define MPIC_CPU_READ(softc, reg) \
 169     bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg))
 170
 171 #define MPIC_DRBL_WRITE(softc, reg, val) \
 172     bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val))
 173 #define MPIC_DRBL_READ(softc, reg) \
 174     bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg))
 175
 176 static int
 177 mv_mpic_probe(device_t dev)
 178 {
 179
 180         if (!ofw_bus_status_okay(dev))
 181                 return (ENXIO);
 182
 183         if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
 184                 return (ENXIO);
 185
 186         device_set_desc(dev, "Marvell Integrated Interrupt Controller");
 187         return (0);
 188 }
 189
 190 static int
 191 mv_mpic_register_isrcs(struct mv_mpic_softc *sc)
 192 {
 193         int error;
 194         uint32_t irq;
 195         struct intr_irqsrc *isrc;
 196         const char *name;
 197
 198         sc->mpic_isrcs = malloc(sc->nirqs * sizeof (*sc->mpic_isrcs), M_DEVBUF,
 199             M_WAITOK | M_ZERO);
 200
 201         name = device_get_nameunit(sc->sc_dev);
 202         for (irq = 0; irq < sc->nirqs; irq++) {
 203                 sc->mpic_isrcs[irq].mmi_irq = irq;
 204
 205                 isrc = &sc->mpic_isrcs[irq].mmi_isrc;
 206                 if (irq < MPIC_PPI) {
 207                         error = intr_isrc_register(isrc, sc->sc_dev,
 208                             INTR_ISRCF_PPI, "%s", name);
 209                 } else {
 210                         error = intr_isrc_register(isrc, sc->sc_dev, 0, "%s",
 211                             name);
 212                 }
 213                 if (error != 0) {
 214                         /* XXX call intr_isrc_deregister() */
 215                         device_printf(sc->sc_dev, "%s failed", __func__);
 216                         return (error);
 217                 }
 218         }
 219         return (0);
 220 }
 221
 222 static int
 223 mv_mpic_attach(device_t dev)
 224 {
 225         struct mv_mpic_softc *sc;
 226         int error;
 227         uint32_t val;
 228         int cpu;
 229
 230         sc = (struct mv_mpic_softc *)device_get_softc(dev);
 231
 232         if (mv_mpic_sc != NULL)
 233                 return (ENXIO);
 234         mv_mpic_sc = sc;
 235
 236         sc->sc_dev = dev;
 237
 238         mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN);
 239
 240         error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res);
 241         if (error) {
 242                 device_printf(dev, "could not allocate resources\n");
 243                 return (ENXIO);
 244         }
 245         if (sc->mpic_res[3] == NULL)
 246                 device_printf(dev, "No interrupt to use.\n");
 247         else
 248                 bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK,
 249                     mpic_intr, NULL, sc, &sc->intr_hand);
 250
 251         sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]);
 252         sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]);
 253
 254         sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]);
 255         sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]);
 256
 257         if (sc->mpic_res[2] != NULL) {
 258                 /* This is required only if MSIs are used. */
 259                 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]);
 260                 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]);
 261         }
 262
 263         MPIC_WRITE(mv_mpic_sc, MPIC_CTRL, 1);
 264         MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);
 265
 266         val = MPIC_READ(mv_mpic_sc, MPIC_CTRL);
 267         sc->nirqs = MPIC_CTRL_NIRQS(val);
 268
 269         if (mv_mpic_register_isrcs(sc) != 0) {
 270                 device_printf(dev, "could not register PIC ISRCs\n");
 271                 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
 272                 return (ENXIO);
 273         }
 274
 275         OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev);
 276
 277         if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) {
 278                 device_printf(dev, "could not register PIC\n");
 279                 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
 280                 return (ENXIO);
 281         }
 282
 283         mpic_unmask_msi();
 284
 285         /* Unmask CPU performance counters overflow irq */
 286         for (cpu = 0; cpu < mp_ncpus; cpu++)
 287                 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CPU(cpu) + MPIC_LOCAL_MASK,
 288                     (1 << cpu) | MPIC_CPU_READ(mv_mpic_sc,
 289                     MPIC_CPU(cpu) + MPIC_LOCAL_MASK));
 290
 291         return (0);
 292 }
 293
 294 static int
 295 mpic_intr(void *arg)
 296 {
 297         struct mv_mpic_softc *sc;
 298         uint32_t cause, irqsrc;
 299         unsigned int irq;
 300         u_int cpuid;
 301
 302         sc = arg;
 303         cpuid = PCPU_GET(cpuid);
 304         irq = 0;
 305
 306         for (cause = MPIC_CPU_READ(sc, MPIC_PPI_CAUSE); cause > 0;
 307             cause >>= 1, irq++) {
 308                 if (cause & 1) {
 309                         irqsrc = MPIC_READ(sc, MPIC_INT_CTL(irq));
 310                         if ((irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)) == 0)
 311                                 continue;
 312                         if (intr_isrc_dispatch(&sc->mpic_isrcs[irq].mmi_isrc,
 313                             curthread->td_intr_frame) != 0) {
 314                                 mpic_mask_irq(irq);
 315                                 device_printf(sc->sc_dev, "Stray irq %u "
 316                                     "disabled\n", irq);
 317                         }
 318                 }
 319         }
 320
 321         return (FILTER_HANDLED);
 322 }
 323
 324 static void
 325 mpic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
 326 {
 327         u_int irq;
 328
 329         irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq;
 330         mpic_mask_irq(irq);
 331 }
 332
 333 static void
 334 mpic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
 335 {
 336         u_int irq;
 337
 338         irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq;
 339         mpic_unmask_irq(irq);
 340 }
 341
 342 static int
 343 mpic_map_intr(device_t dev, struct intr_map_data *data,
 344     struct intr_irqsrc **isrcp)
 345 {
 346         struct intr_map_data_fdt *daf;
 347         struct mv_mpic_softc *sc;
 348
 349         if (data->type != INTR_MAP_DATA_FDT)
 350                 return (ENOTSUP);
 351
 352         sc = device_get_softc(dev);
 353         daf = (struct intr_map_data_fdt *)data;
 354
 355         if (daf->ncells !=1 || daf->cells[0] >= sc->nirqs)
 356                 return (EINVAL);
 357
 358         *isrcp = &sc->mpic_isrcs[daf->cells[0]].mmi_isrc;
 359         return (0);
 360 }
 361
 362 static void
 363 mpic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
 364 {
 365
 366         mpic_disable_intr(dev, isrc);
 367 }
 368
 369 static void
 370 mpic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
 371 {
 372
 373         mpic_enable_intr(dev, isrc);
 374 }
 375
 376 static void
 377 mpic_post_filter(device_t dev, struct intr_irqsrc *isrc)
 378 {
 379 }
 380
 381 static device_method_t mv_mpic_methods[] = {
 382         DEVMETHOD(device_probe,         mv_mpic_probe),
 383         DEVMETHOD(device_attach,        mv_mpic_attach),
 384
 385         DEVMETHOD(pic_disable_intr,     mpic_disable_intr),
 386         DEVMETHOD(pic_enable_intr,      mpic_enable_intr),
 387         DEVMETHOD(pic_map_intr,         mpic_map_intr),
 388         DEVMETHOD(pic_post_filter,      mpic_post_filter),
 389         DEVMETHOD(pic_post_ithread,     mpic_post_ithread),
 390         DEVMETHOD(pic_pre_ithread,      mpic_pre_ithread),
 391         DEVMETHOD(pic_init_secondary,   mpic_init_secondary),
 392         DEVMETHOD(pic_ipi_send,         mpic_ipi_send),
 393         { 0, 0 }
 394 };
 395
 396 static driver_t mv_mpic_driver = {
 397         "mpic",
 398         mv_mpic_methods,
 399         sizeof(struct mv_mpic_softc),
 400 };
 401
 402 static devclass_t mv_mpic_devclass;
 403
 404 EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0,
 405     BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
 406
 407 static void
 408 mpic_unmask_msi(void)
 409 {
 410
 411         mpic_unmask_irq(MPIC_INT_MSI);
 412 }
 413
 414 static void
 415 mpic_unmask_irq_err(uintptr_t nb)
 416 {
 417         uint32_t mask;
 418         uint8_t bit_off;
 419
 420         MPIC_WRITE(mv_mpic_sc, MPIC_ISE, MPIC_INT_ERR);
 421         MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR);
 422
 423         bit_off = nb - ERR_IRQ;
 424         mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
 425         mask |= (1 << bit_off);
 426         MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
 427 }
 428
 429 static void
 430 mpic_mask_irq_err(uintptr_t nb)
 431 {
 432         uint32_t mask;
 433         uint8_t bit_off;
 434
 435         bit_off = nb - ERR_IRQ;
 436         mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
 437         mask &= ~(1 << bit_off);
 438         MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
 439 }
 440
 441 static boolean_t
 442 mpic_irq_is_percpu(uintptr_t nb)
 443 {
 444         if (nb < MPIC_PPI)
 445                 return TRUE;
 446
 447         return FALSE;
 448 }
 449
 450 static void
 451 mpic_unmask_irq(uintptr_t nb)
 452 {
 453
 454 #ifdef SMP
 455         int cpu;
 456
 457         if (nb == MPIC_INT_LOCAL) {
 458                 for (cpu = 0; cpu < mp_ncpus; cpu++)
 459                         MPIC_CPU_WRITE(mv_mpic_sc,
 460                             MPIC_CPU(cpu) + MPIC_ICM, nb);
 461                 return;
 462         }
 463 #endif
 464         if (mpic_irq_is_percpu(nb))
 465                 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb);
 466         else if (nb < ERR_IRQ)
 467                 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, nb);
 468         else if (nb < MSI_IRQ)
 469                 mpic_unmask_irq_err(nb);
 470
 471         if (nb == 0)
 472                 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff);
 473 }
 474
 475 static void
 476 mpic_mask_irq(uintptr_t nb)
 477 {
 478
 479 #ifdef SMP
 480         int cpu;
 481
 482         if (nb == MPIC_INT_LOCAL) {
 483                 for (cpu = 0; cpu < mp_ncpus; cpu++)
 484                         MPIC_CPU_WRITE(mv_mpic_sc,
 485                             MPIC_CPU(cpu) + MPIC_ISM, nb);
 486                 return;
 487         }
 488 #endif
 489         if (mpic_irq_is_percpu(nb))
 490                 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb);
 491         else if (nb < ERR_IRQ)
 492                 MPIC_WRITE(mv_mpic_sc, MPIC_ICE, nb);
 493         else if (nb < MSI_IRQ)
 494                 mpic_mask_irq_err(nb);
 495 }
 496
 497 uint32_t
 498 mv_mpic_get_cause(void)
 499 {
 500
 501         return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK));
 502 }
 503
 504 uint32_t
 505 mv_mpic_get_cause_err(void)
 506 {
 507         uint32_t err_cause;
 508         uint8_t bit_off;
 509
 510         err_cause = MPIC_READ(mv_mpic_sc, MPIC_ERR_CAUSE);
 511
 512         if (err_cause)
 513                 bit_off = ffs(err_cause) - 1;
 514         else
 515                 return (-1);
 516
 517         debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause);
 518         return (ERR_IRQ + bit_off);
 519 }
 520
 521 uint32_t
 522 mv_mpic_get_msi(void)
 523 {
 524         uint32_t cause;
 525         uint8_t bit_off;
 526
 527         KASSERT(mv_mpic_sc->drbl_bst != NULL, ("No doorbell in mv_mpic_get_msi"));
 528         cause = MPIC_DRBL_READ(mv_mpic_sc, 0);
 529
 530         if (cause)
 531                 bit_off = ffs(cause) - 1;
 532         else
 533                 return (-1);
 534
 535         debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause);
 536
 537         cause &= ~(1 << bit_off);
 538         MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause);
 539
 540         return (MSI_IRQ + bit_off);
 541 }
 542
 543 int
 544 mv_msi_data(int irq, uint64_t *addr, uint32_t *data)
 545 {
 546         u_long phys, base, size;
 547         phandle_t node;
 548         int error;
 549
 550         node = ofw_bus_get_node(mv_mpic_sc->sc_dev);
 551
 552         /* Get physical address of register space */
 553         error = fdt_get_range(OF_parent(node), 0, &phys, &size);
 554         if (error) {
 555                 printf("%s: Cannot get register physical address, err:%d",
 556                     __func__, error);
 557                 return (error);
 558         }
 559
 560         /* Get offset of MPIC register space */
 561         error = fdt_regsize(node, &base, &size);
 562         if (error) {
 563                 printf("%s: Cannot get MPIC register offset, err:%d",
 564                     __func__, error);
 565                 return (error);
 566         }
 567
 568         *addr = phys + base + MPIC_SOFT_INT;
 569         *data = MPIC_SOFT_INT_DRBL1 | irq;
 570
 571         return (0);
 572 }
 573
 574 void
 575 mpic_init_secondary(device_t dev)
 576 {
 577 }
 578
 579 void
 580 mpic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, u_int ipi)
 581 {
 582         uint32_t val, i;
 583
 584         val = 0x00000000;
 585         for (i = 0; i < MAXCPU; i++)
 586                 if (CPU_ISSET(i, &cpus))
 587                         val |= (1 << (8 + i));
 588         val |= ipi;
 589         MPIC_WRITE(mv_mpic_sc, MPIC_SOFT_INT, val);
 590 }
 591
 592 int
 593 mpic_ipi_read(int i __unused)
 594 {
 595         uint32_t val;
 596         int ipi;
 597
 598         val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL);
 599         if (val) {
 600                 ipi = ffs(val) - 1;
 601                 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi));
 602                 return (ipi);
 603         }
 604
 605         return (0x3ff);
 606 }
 607
 608 void
 609 mpic_ipi_clear(int ipi)
 610 {
 611 }