2 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD.
5 * Developed by Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
41 #include <sys/reboot.h>
43 #include <dev/fdt/fdt_common.h>
44 #include <dev/ofw/openfirm.h>
45 #include <dev/ofw/ofw_bus_subr.h>
47 #include <machine/bus.h>
48 #include <machine/fdt.h>
49 #include <machine/vmparam.h>
50 #include <machine/intr.h>
52 #include <arm/mv/mvreg.h>
53 #include <arm/mv/mvvar.h>
54 #include <arm/mv/mvwin.h>
57 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory");
65 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \
66 printf(fmt,##args); } while (0)
68 #define debugf(fmt, args...)
77 static int win_eth_can_remap(int i);
79 static int decode_win_cesa_valid(void);
80 static int decode_win_cpu_valid(void);
81 static int decode_win_usb_valid(void);
82 static int decode_win_usb3_valid(void);
83 static int decode_win_eth_valid(void);
84 static int decode_win_pcie_valid(void);
85 static int decode_win_sata_valid(void);
86 static int decode_win_sdhci_valid(void);
88 static int decode_win_idma_valid(void);
89 static int decode_win_xor_valid(void);
91 static void decode_win_cpu_setup(void);
92 #ifdef SOC_MV_ARMADAXP
93 static int decode_win_sdram_fixup(void);
95 static void decode_win_cesa_setup(u_long);
96 static void decode_win_usb_setup(u_long);
97 static void decode_win_usb3_setup(u_long);
98 static void decode_win_eth_setup(u_long);
99 static void decode_win_neta_setup(u_long);
100 static void decode_win_sata_setup(u_long);
101 static void decode_win_ahci_setup(u_long);
102 static void decode_win_sdhci_setup(u_long);
104 static void decode_win_idma_setup(u_long);
105 static void decode_win_xor_setup(u_long);
107 static void decode_win_cesa_dump(u_long);
108 static void decode_win_usb_dump(u_long);
109 static void decode_win_usb3_dump(u_long);
110 static void decode_win_eth_dump(u_long base);
111 static void decode_win_neta_dump(u_long base);
112 static void decode_win_idma_dump(u_long base);
113 static void decode_win_xor_dump(u_long base);
114 static void decode_win_ahci_dump(u_long base);
115 static void decode_win_sdhci_dump(u_long);
116 static void decode_win_pcie_dump(u_long);
118 static int fdt_get_ranges(const char *, void *, int, int *, int *);
119 #ifdef SOC_MV_ARMADA38X
120 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
121 int *trig, int *pol);
124 static int win_cpu_from_dt(void);
125 static int fdt_win_setup(void);
127 static uint32_t dev_mask = 0;
128 static int cpu_wins_no = 0;
129 static int eth_port = 0;
130 static int usb_port = 0;
132 static struct decode_win cpu_win_tbl[MAX_CPU_WIN];
134 const struct decode_win *cpu_wins = cpu_win_tbl;
136 typedef void (*decode_win_setup_t)(u_long);
137 typedef void (*dump_win_t)(u_long);
140 * The power status of device feature is only supported on
141 * Kirkwood and Discovery SoCs.
143 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
144 #define SOC_MV_POWER_STAT_SUPPORTED 1
146 #define SOC_MV_POWER_STAT_SUPPORTED 0
149 struct soc_node_spec {
151 decode_win_setup_t decode_handler;
152 dump_win_t dump_handler;
155 static struct soc_node_spec soc_nodes[] = {
156 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump },
157 { "marvell,armada-370-neta", &decode_win_neta_setup, &decode_win_neta_dump },
158 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
159 { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
160 { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump },
161 { "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_ahci_dump },
162 { "marvell,armada-380-sdhci", &decode_win_sdhci_setup, &decode_win_sdhci_dump },
163 { "mrvl,sata", &decode_win_sata_setup, NULL },
164 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump },
165 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump },
166 { "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump },
167 { "mrvl,pcie", &decode_win_pcie_setup, &decode_win_pcie_dump },
168 { NULL, NULL, NULL },
171 struct fdt_pm_mask_entry {
176 static struct fdt_pm_mask_entry fdt_pm_mask_table[] = {
177 { "mrvl,ge", CPU_PM_CTRL_GE(0) },
178 { "mrvl,ge", CPU_PM_CTRL_GE(1) },
179 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) },
180 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) },
181 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) },
182 { "mrvl,xor", CPU_PM_CTRL_XOR },
183 { "mrvl,sata", CPU_PM_CTRL_SATA },
189 pm_is_disabled(uint32_t mask)
191 #if SOC_MV_POWER_STAT_SUPPORTED
192 return (soc_power_ctrl_get(mask) == mask ? 0 : 1);
199 * Disable device using power management register.
200 * 1 - Device Power On
201 * 0 - Device Power Off
202 * Mask can be set in loader.
204 * loader> set hw.pm-disable-mask=0x2
207 * |-------------------------------|
208 * | Device | Kirkwood | Discovery |
209 * |-------------------------------|
210 * | USB0 | 0x00008 | 0x020000 |
211 * |-------------------------------|
212 * | USB1 | - | 0x040000 |
213 * |-------------------------------|
214 * | USB2 | - | 0x080000 |
215 * |-------------------------------|
216 * | GE0 | 0x00001 | 0x000002 |
217 * |-------------------------------|
218 * | GE1 | - | 0x000004 |
219 * |-------------------------------|
220 * | IDMA | - | 0x100000 |
221 * |-------------------------------|
222 * | XOR | 0x10000 | 0x200000 |
223 * |-------------------------------|
224 * | CESA | 0x20000 | 0x400000 |
225 * |-------------------------------|
226 * | SATA | 0x04000 | 0x004000 |
227 * --------------------------------|
228 * This feature can be used only on Kirkwood and Discovery
232 pm_disable_device(int mask)
237 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
238 printf("Power Management Register: 0%x\n", reg);
241 soc_power_ctrl_set(reg);
242 printf("Device %x is disabled\n", mask);
244 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
245 printf("Power Management Register: 0%x\n", reg);
250 fdt_pm(phandle_t node)
252 uint32_t cpu_pm_ctrl;
256 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL);
257 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) {
258 if (dev_mask & (1 << i))
261 compat = ofw_bus_node_is_compatible(node,
262 fdt_pm_mask_table[i].compat);
263 #if defined(SOC_MV_KIRKWOOD)
264 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) {
265 dev_mask |= (1 << i);
269 dev_mask |= (1 << i);
273 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) {
274 dev_mask |= (1 << i);
278 dev_mask |= (1 << i);
288 read_cpu_ctrl(uint32_t reg)
291 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg));
295 write_cpu_ctrl(uint32_t reg, uint32_t val)
298 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val);
301 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
303 read_cpu_mp_clocks(uint32_t reg)
306 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg));
310 write_cpu_mp_clocks(uint32_t reg, uint32_t val)
313 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val);
317 read_cpu_misc(uint32_t reg)
320 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg));
324 write_cpu_misc(uint32_t reg, uint32_t val)
327 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val);
335 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X)
336 write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
337 write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
339 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
340 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
356 case MV_DEV_88RC8180:
357 case MV_DEV_MV78100_Z0:
359 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
363 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
367 printf("This ARM Core does not support any extra features\n");
374 * Get the power status of device. This feature is only supported on
375 * Kirkwood and Discovery SoCs.
378 soc_power_ctrl_get(uint32_t mask)
381 #if SOC_MV_POWER_STAT_SUPPORTED
382 if (mask != CPU_PM_CTRL_NONE)
383 mask &= read_cpu_ctrl(CPU_PM_CTRL);
392 * Set the power status of device. This feature is only supported on
393 * Kirkwood and Discovery SoCs.
396 soc_power_ctrl_set(uint32_t mask)
399 #if !defined(SOC_MV_ORION)
400 if (mask != CPU_PM_CTRL_NONE)
401 write_cpu_ctrl(CPU_PM_CTRL, mask);
406 soc_id(uint32_t *dev, uint32_t *rev)
410 * Notice: system identifiers are available in the registers range of
411 * PCIE controller, so using this function is only allowed (and
412 * possible) after the internal registers range has been mapped in via
413 * devmap_bootstrap().
415 *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16;
416 *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff;
422 uint32_t d, r, size, mode, freq;
430 printf("(0x%4x:0x%02x) ", d, r);
435 dev = "Marvell 88F5181";
440 dev = "Marvell 88F5182";
445 dev = "Marvell 88F5281";
454 dev = "Marvell 88F6281";
462 case MV_DEV_88RC8180:
463 dev = "Marvell 88RC8180";
465 case MV_DEV_88RC9480:
466 dev = "Marvell 88RC9480";
468 case MV_DEV_88RC9580:
469 dev = "Marvell 88RC9580";
472 dev = "Marvell 88F6781";
477 dev = "Marvell 88F6282";
484 dev = "Marvell 88F6828";
487 dev = "Marvell 88F6820";
490 dev = "Marvell 88F6810";
492 case MV_DEV_MV78100_Z0:
493 dev = "Marvell MV78100 Z0";
496 dev = "Marvell MV78100";
499 dev = "Marvell MV78160";
502 dev = "Marvell MV78260";
505 dev = "Marvell MV78460";
514 printf(" rev %s", rev);
515 printf(", TClock %dMHz", get_tclk() / 1000 / 1000);
516 freq = get_cpu_freq();
518 printf(", Frequency %dMHz", freq / 1000 / 1000);
521 mode = read_cpu_ctrl(CPU_CONFIG);
522 printf(" Instruction cache prefetch %s, data cache prefetch %s\n",
523 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled",
524 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled");
529 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE;
530 printf(" 256KB 4-way set-associative %s unified L2 cache\n",
531 mode ? "write-through" : "write-back");
534 mode = read_cpu_ctrl(CPU_CONTROL);
535 size = mode & CPU_CONTROL_L2_SIZE;
536 mode = mode & CPU_CONTROL_L2_MODE;
537 printf(" %s set-associative %s unified L2 cache\n",
538 size ? "256KB 4-way" : "512KB 8-way",
539 mode ? "write-through" : "write-back");
547 platform_identify(void *dummy)
553 * XXX Board identification e.g. read out from FPGA or similar should
557 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify,
562 mv_enter_debugger(void *dummy)
565 if (boothowto & RB_KDB)
566 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
568 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL);
578 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask);
581 pm_disable_device(mask);
583 /* Retrieve data about physical addresses from device tree. */
584 if ((err = win_cpu_from_dt()) != 0)
587 /* Retrieve our ID: some windows facilities vary between SoC models */
590 #ifdef SOC_MV_ARMADAXP
591 if ((err = decode_win_sdram_fixup()) != 0)
595 if (!decode_win_cpu_valid() || !decode_win_usb_valid() ||
596 !decode_win_eth_valid() || !decode_win_idma_valid() ||
597 !decode_win_pcie_valid() || !decode_win_sata_valid() ||
598 !decode_win_xor_valid() || !decode_win_usb3_valid() ||
599 !decode_win_sdhci_valid() || !decode_win_cesa_valid())
602 decode_win_cpu_setup();
604 soc_dump_decode_win();
608 if ((err = fdt_win_setup()) != 0)
614 /**************************************************************************
615 * Decode windows registers accessors
616 **************************************************************************/
617 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
618 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
619 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
620 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
621 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
622 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
623 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
624 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
626 WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL)
627 WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE)
628 WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL)
629 WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE)
631 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL)
632 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE)
633 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL)
634 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE)
636 #ifdef SOC_MV_ARMADA38X
637 WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL)
638 WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE)
639 WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL)
640 WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE)
643 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
644 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
645 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
646 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)
647 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)
648 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)
650 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE)
651 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE)
652 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP)
653 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL)
654 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE)
655 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE)
656 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP)
657 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL)
659 WIN_REG_BASE_RD(win_eth, bare, 0x290)
660 WIN_REG_BASE_RD(win_eth, epap, 0x294)
661 WIN_REG_BASE_WR(win_eth, bare, 0x290)
662 WIN_REG_BASE_WR(win_eth, epap, 0x294)
664 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL);
665 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE);
666 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP);
667 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL);
668 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE);
669 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP);
670 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE);
671 WIN_REG_BASE_IDX_RD(pcie_bar, brh, MV_PCIE_BAR_BASE_H);
672 WIN_REG_BASE_IDX_RD(pcie_bar, cr, MV_PCIE_BAR_CTRL);
673 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE);
674 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H);
675 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL);
677 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE)
678 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE)
679 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP)
680 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP)
681 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE)
682 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE)
683 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP)
684 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP)
685 WIN_REG_BASE_RD(win_idma, bare, 0xa80)
686 WIN_REG_BASE_WR(win_idma, bare, 0xa80)
688 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL);
689 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE);
690 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL);
691 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE);
692 #if defined(SOC_MV_ARMADA38X)
693 WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE);
694 WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE);
697 WIN_REG_BASE_IDX_RD(win_sdhci, cr, MV_WIN_SDHCI_CTRL);
698 WIN_REG_BASE_IDX_RD(win_sdhci, br, MV_WIN_SDHCI_BASE);
699 WIN_REG_BASE_IDX_WR(win_sdhci, cr, MV_WIN_SDHCI_CTRL);
700 WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE);
703 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
704 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
705 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
706 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
709 * On 88F6781 (Dove) SoC DDR Controller is accessed through
710 * single MBUS <-> AXI bridge. In this case we provide emulated
711 * ddr_br_read() and ddr_sz_read() functions to keep compatibility
712 * with common decoding windows setup code.
715 static inline uint32_t ddr_br_read(int i)
719 /* Read Memory Address Map Register for CS i */
720 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0);
722 /* Return CS i base address */
723 return (mmap & 0xFF000000);
726 static inline uint32_t ddr_sz_read(int i)
730 /* Read Memory Address Map Register for CS i */
731 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0);
733 /* Extract size of CS space in 64kB units */
734 size = (1 << ((mmap >> 16) & 0x0F));
736 /* Return CS size and enable/disable status */
737 return (((size - 1) << 16) | (mmap & 0x01));
741 /**************************************************************************
742 * Decode windows helper routines
743 **************************************************************************/
745 soc_dump_decode_win(void)
752 for (i = 0; i < MV_WIN_CPU_MAX; i++) {
753 printf("CPU window#%d: c 0x%08x, b 0x%08x", i,
757 if (win_cpu_can_remap(i))
758 printf(", rl 0x%08x, rh 0x%08x",
759 win_cpu_remap_l_read(i),
760 win_cpu_remap_h_read(i));
764 printf("Internal regs base: 0x%08x\n",
765 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0));
767 for (i = 0; i < MV_WIN_DDR_MAX; i++)
768 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i,
769 ddr_br_read(i), ddr_sz_read(i));
772 /**************************************************************************
773 * CPU windows routines
774 **************************************************************************/
776 win_cpu_can_remap(int i)
782 /* Depending on the SoC certain windows have remap capability */
783 if ((dev == MV_DEV_88F5182 && i < 2) ||
784 (dev == MV_DEV_88F5281 && i < 4) ||
785 (dev == MV_DEV_88F6281 && i < 4) ||
786 (dev == MV_DEV_88F6282 && i < 4) ||
787 (dev == MV_DEV_88F6828 && i < 20) ||
788 (dev == MV_DEV_88F6820 && i < 20) ||
789 (dev == MV_DEV_88F6810 && i < 20) ||
790 (dev == MV_DEV_88RC8180 && i < 2) ||
791 (dev == MV_DEV_88F6781 && i < 4) ||
792 (dev == MV_DEV_MV78100_Z0 && i < 8) ||
793 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8))
799 /* XXX This should check for overlapping remap fields too.. */
801 decode_win_overlap(int win, int win_no, const struct decode_win *wintab)
803 const struct decode_win *tab;
808 for (i = 0; i < win_no; i++, tab++) {
813 if ((tab->base + tab->size - 1) < (wintab + win)->base)
816 else if (((wintab + win)->base + (wintab + win)->size - 1) <
827 decode_win_cpu_valid(void)
832 if (cpu_wins_no > MV_WIN_CPU_MAX) {
833 printf("CPU windows: too many entries: %d\n", cpu_wins_no);
838 for (i = 0; i < cpu_wins_no; i++) {
840 if (cpu_wins[i].target == 0) {
841 printf("CPU window#%d: DDR target window is not "
842 "supposed to be reprogrammed!\n", i);
846 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) {
847 printf("CPU window#%d: not capable of remapping, but "
848 "val 0x%08x defined\n", i, cpu_wins[i].remap);
852 s = cpu_wins[i].size;
853 b = cpu_wins[i].base;
855 if (s > (0xFFFFFFFF - b + 1)) {
857 * XXX this boundary check should account for 64bit
860 printf("CPU window#%d: no space for size 0x%08x at "
861 "0x%08x\n", i, s, b);
866 if (b != rounddown2(b, s)) {
867 printf("CPU window#%d: address 0x%08x is not aligned "
868 "to 0x%08x\n", i, b, s);
873 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]);
875 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps "
876 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
878 cpu_wins[j].base + cpu_wins[j].size - 1);
887 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
894 win = MV_WIN_CPU_MAX - 1;
901 while ((win >= 0) && (win < MV_WIN_CPU_MAX)) {
902 cr = win_cpu_cr_read(win);
903 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0)
905 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) |
906 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) ==
907 ((attr << MV_WIN_CPU_ATTR_SHIFT) |
908 (target << MV_WIN_CPU_TARGET_SHIFT)))
912 if ((win < 0) || (win >= MV_WIN_CPU_MAX) ||
913 ((remap != ~0) && (win_cpu_can_remap(win) == 0)))
916 br = base & 0xffff0000;
917 win_cpu_br_write(win, br);
919 if (win_cpu_can_remap(win)) {
921 win_cpu_remap_l_write(win, remap & 0xffff0000);
922 win_cpu_remap_h_write(win, 0);
925 * Remap function is not used for a given window
926 * (capable of remapping) - set remap field with the
927 * same value as base.
929 win_cpu_remap_l_write(win, base & 0xffff0000);
930 win_cpu_remap_h_write(win, 0);
934 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) |
935 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT;
936 win_cpu_cr_write(win, cr);
942 decode_win_cpu_setup(void)
946 /* Disable all CPU windows */
947 for (i = 0; i < MV_WIN_CPU_MAX; i++) {
948 win_cpu_cr_write(i, 0);
949 win_cpu_br_write(i, 0);
950 if (win_cpu_can_remap(i)) {
951 win_cpu_remap_l_write(i, 0);
952 win_cpu_remap_h_write(i, 0);
956 for (i = 0; i < cpu_wins_no; i++)
957 if (cpu_wins[i].target > 0)
958 decode_win_cpu_set(cpu_wins[i].target,
959 cpu_wins[i].attr, cpu_wins[i].base,
960 cpu_wins[i].size, cpu_wins[i].remap);
964 #ifdef SOC_MV_ARMADAXP
966 decode_win_sdram_fixup(void)
968 struct mem_region mr[FDT_MEM_REGIONS];
969 uint8_t window_valid[MV_WIN_DDR_MAX];
970 int mr_cnt, err, i, j;
971 uint32_t valid_win_num = 0;
973 /* Grab physical memory regions information from device tree. */
974 err = fdt_get_mem_regions(mr, &mr_cnt, NULL);
978 for (i = 0; i < MV_WIN_DDR_MAX; i++)
981 /* Try to match entries from device tree with settings from u-boot */
982 for (i = 0; i < mr_cnt; i++) {
983 for (j = 0; j < MV_WIN_DDR_MAX; j++) {
984 if (ddr_is_active(j) &&
985 (ddr_base(j) == mr[i].mr_start) &&
986 (ddr_size(j) == mr[i].mr_size)) {
993 if (mr_cnt != valid_win_num)
996 /* Destroy windows without corresponding device tree entry */
997 for (j = 0; j < MV_WIN_DDR_MAX; j++) {
998 if (ddr_is_active(j) && (window_valid[j] != 1)) {
999 printf("Disabling SDRAM decoding window: %d\n", j);
1008 * Check if we're able to cover all active DDR banks.
1011 decode_win_can_cover_ddr(int max)
1016 for (i = 0; i < MV_WIN_DDR_MAX; i++)
1017 if (ddr_is_active(i))
1021 printf("Unable to cover all active DDR banks: "
1022 "%d, available windows: %d\n", c, max);
1029 /**************************************************************************
1030 * DDR windows routines
1031 **************************************************************************/
1033 ddr_is_active(int i)
1036 if (ddr_sz_read(i) & 0x1)
1054 return (ddr_br_read(i) & 0xff000000);
1061 return ((ddr_sz_read(i) | 0x00ffffff) + 1);
1070 if (dev == MV_DEV_88RC8180)
1071 return ((ddr_sz_read(i) & 0xf0) >> 4);
1072 if (dev == MV_DEV_88F6781)
1075 return (i == 0 ? 0xe :
1078 (i == 3 ? 0x7 : 0xff))));
1087 if (dev == MV_DEV_88RC8180) {
1088 i = (ddr_sz_read(i) & 0xf0) >> 4;
1089 return (i == 0xe ? 0xc :
1092 (i == 0x7 ? 0xf : 0xc))));
1096 * On SOCs other than 88RC8180 Mbus unit ID for
1097 * DDR SDRAM controller is always 0x0.
1102 /**************************************************************************
1103 * CESA windows routines
1104 **************************************************************************/
1106 decode_win_cesa_valid(void)
1109 return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX));
1113 decode_win_cesa_dump(u_long base)
1117 for (i = 0; i < MV_WIN_CESA_MAX; i++)
1118 printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i,
1119 win_cesa_cr_read(base, i), win_cesa_br_read(base, i));
1123 * Set CESA decode windows.
1126 decode_win_cesa_setup(u_long base)
1132 for (i = 0; i < MV_WIN_CESA_MAX; i++) {
1133 win_cesa_cr_write(base, i, 0);
1134 win_cesa_br_write(base, i, 0);
1137 /* Only access to active DRAM banks is required */
1138 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1139 if (ddr_is_active(i)) {
1143 #ifdef SOC_MV_ARMADA38X
1145 * Armada 38x SoC's equipped with 4GB DRAM
1146 * suffer freeze during CESA operation, if
1147 * MBUS window opened at given DRAM CS reaches
1148 * end of the address space. Apply a workaround
1149 * by setting the window size to the closest possible
1150 * value, i.e. divide it by 2.
1152 if (size + ddr_base(i) == 0x100000000ULL)
1156 cr = (((size - 1) & 0xffff0000) |
1157 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
1158 (ddr_target(i) << IO_WIN_TGT_SHIFT) |
1161 /* Set the first free CESA window */
1162 for (j = 0; j < MV_WIN_CESA_MAX; j++) {
1163 if (win_cesa_cr_read(base, j) & 0x1)
1166 win_cesa_br_write(base, j, br);
1167 win_cesa_cr_write(base, j, cr);
1174 /**************************************************************************
1175 * USB windows routines
1176 **************************************************************************/
1178 decode_win_usb_valid(void)
1181 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX));
1185 decode_win_usb_dump(u_long base)
1189 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1)))
1192 for (i = 0; i < MV_WIN_USB_MAX; i++)
1193 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i,
1194 win_usb_cr_read(base, i), win_usb_br_read(base, i));
1198 * Set USB decode windows.
1201 decode_win_usb_setup(u_long base)
1206 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port)))
1211 for (i = 0; i < MV_WIN_USB_MAX; i++) {
1212 win_usb_cr_write(base, i, 0);
1213 win_usb_br_write(base, i, 0);
1216 /* Only access to active DRAM banks is required */
1217 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1218 if (ddr_is_active(i)) {
1221 * XXX for 6281 we should handle Mbus write
1222 * burst limit field in the ctrl reg
1224 cr = (((ddr_size(i) - 1) & 0xffff0000) |
1225 (ddr_attr(i) << 8) |
1226 (ddr_target(i) << 4) | 1);
1228 /* Set the first free USB window */
1229 for (j = 0; j < MV_WIN_USB_MAX; j++) {
1230 if (win_usb_cr_read(base, j) & 0x1)
1233 win_usb_br_write(base, j, br);
1234 win_usb_cr_write(base, j, cr);
1241 /**************************************************************************
1242 * USB3 windows routines
1243 **************************************************************************/
1244 #ifdef SOC_MV_ARMADA38X
1246 decode_win_usb3_valid(void)
1249 return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX));
1253 decode_win_usb3_dump(u_long base)
1257 for (i = 0; i < MV_WIN_USB3_MAX; i++)
1258 printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i,
1259 win_usb3_cr_read(base, i), win_usb3_br_read(base, i));
1263 * Set USB3 decode windows
1266 decode_win_usb3_setup(u_long base)
1271 for (i = 0; i < MV_WIN_USB3_MAX; i++) {
1272 win_usb3_cr_write(base, i, 0);
1273 win_usb3_br_write(base, i, 0);
1276 /* Only access to active DRAM banks is required */
1277 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1278 if (ddr_is_active(i)) {
1280 cr = (((ddr_size(i) - 1) &
1281 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) |
1282 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
1283 (ddr_target(i) << IO_WIN_TGT_SHIFT) |
1286 /* Set the first free USB3.0 window */
1287 for (j = 0; j < MV_WIN_USB3_MAX; j++) {
1288 if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK)
1291 win_usb3_br_write(base, j, br);
1292 win_usb3_cr_write(base, j, cr);
1300 * Provide dummy functions to satisfy the build
1301 * for SoCs not equipped with USB3
1304 decode_win_usb3_valid(void)
1311 decode_win_usb3_setup(u_long base)
1316 decode_win_usb3_dump(u_long base)
1320 /**************************************************************************
1321 * ETH windows routines
1322 **************************************************************************/
1325 win_eth_can_remap(int i)
1328 /* ETH encode windows 0-3 have remap capability */
1336 eth_bare_read(uint32_t base, int i)
1340 v = win_eth_bare_read(base);
1347 eth_bare_write(uint32_t base, int i, int val)
1351 v = win_eth_bare_read(base);
1354 win_eth_bare_write(base, v);
1358 eth_epap_write(uint32_t base, int i, int val)
1362 v = win_eth_epap_read(base);
1363 v &= ~(0x3 << (i * 2));
1364 v |= (val << (i * 2));
1365 win_eth_epap_write(base, v);
1369 decode_win_eth_dump(u_long base)
1373 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1)))
1376 for (i = 0; i < MV_WIN_ETH_MAX; i++) {
1377 printf("ETH window#%d: b 0x%08x, s 0x%08x", i,
1378 win_eth_br_read(base, i),
1379 win_eth_sz_read(base, i));
1381 if (win_eth_can_remap(i))
1382 printf(", ha 0x%08x",
1383 win_eth_har_read(base, i));
1387 printf("ETH windows: bare 0x%08x, epap 0x%08x\n",
1388 win_eth_bare_read(base),
1389 win_eth_epap_read(base));
1392 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n)
1395 decode_win_eth_setup(u_long base)
1400 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port)))
1405 /* Disable, clear and revoke protection for all ETH windows */
1406 for (i = 0; i < MV_WIN_ETH_MAX; i++) {
1408 eth_bare_write(base, i, 1);
1409 eth_epap_write(base, i, 0);
1410 win_eth_br_write(base, i, 0);
1411 win_eth_sz_write(base, i, 0);
1412 if (win_eth_can_remap(i))
1413 win_eth_har_write(base, i, 0);
1416 /* Only access to active DRAM banks is required */
1417 for (i = 0; i < MV_WIN_DDR_MAX; i++)
1418 if (ddr_is_active(i)) {
1420 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i);
1421 sz = ((ddr_size(i) - 1) & 0xffff0000);
1423 /* Set the first free ETH window */
1424 for (j = 0; j < MV_WIN_ETH_MAX; j++) {
1425 if (eth_bare_read(base, j) == 0)
1428 win_eth_br_write(base, j, br);
1429 win_eth_sz_write(base, j, sz);
1431 /* XXX remapping ETH windows not supported */
1433 /* Set protection RW */
1434 eth_epap_write(base, j, 0x3);
1437 eth_bare_write(base, j, 0);
1444 decode_win_neta_dump(u_long base)
1447 decode_win_eth_dump(base + MV_WIN_NETA_OFFSET);
1451 decode_win_neta_setup(u_long base)
1454 decode_win_eth_setup(base + MV_WIN_NETA_OFFSET);
1458 decode_win_eth_valid(void)
1461 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX));
1464 /**************************************************************************
1465 * PCIE windows routines
1466 **************************************************************************/
1468 decode_win_pcie_dump(u_long base)
1472 printf("PCIE windows base 0x%08lx\n", base);
1473 for (i = 0; i < MV_WIN_PCIE_MAX; i++)
1474 printf("PCIE window#%d: cr 0x%08x br 0x%08x remap 0x%08x\n",
1475 i, win_pcie_cr_read(base, i),
1476 win_pcie_br_read(base, i), win_pcie_remap_read(base, i));
1478 for (i = 0; i < MV_PCIE_BAR_MAX; i++)
1479 printf("PCIE bar#%d: cr 0x%08x br 0x%08x brh 0x%08x\n",
1480 i, pcie_bar_cr_read(base, i),
1481 pcie_bar_br_read(base, i), pcie_bar_brh_read(base, i));
1485 decode_win_pcie_setup(u_long base)
1487 uint32_t size = 0, ddrbase = ~0;
1491 for (i = 0; i < MV_PCIE_BAR_MAX; i++) {
1492 pcie_bar_br_write(base, i,
1493 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
1495 pcie_bar_brh_write(base, i, 0);
1497 pcie_bar_cr_write(base, i, 0);
1500 for (i = 0; i < MV_WIN_PCIE_MAX; i++) {
1501 win_pcie_cr_write(base, i, 0);
1502 win_pcie_br_write(base, i, 0);
1503 win_pcie_remap_write(base, i, 0);
1506 /* On End-Point only set BAR size to 1MB regardless of DDR size */
1507 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL)
1508 & MV_PCIE_ROOT_CMPLX) == 0) {
1509 pcie_bar_cr_write(base, 1, 0xf0000 | 1);
1513 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1514 if (ddr_is_active(i)) {
1515 /* Map DDR to BAR 1 */
1516 cr = (ddr_size(i) - 1) & 0xffff0000;
1517 size += ddr_size(i) & 0xffff0000;
1518 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
1523 /* Use the first available PCIE window */
1524 for (j = 0; j < MV_WIN_PCIE_MAX; j++) {
1525 if (win_pcie_cr_read(base, j) != 0)
1528 win_pcie_br_write(base, j, br);
1529 win_pcie_cr_write(base, j, cr);
1536 * Upper 16 bits in BAR register is interpreted as BAR size
1537 * (in 64 kB units) plus 64kB, so subtract 0x10000
1538 * form value passed to register to get correct value.
1541 pcie_bar_cr_write(base, 1, size | 1);
1542 pcie_bar_br_write(base, 1, ddrbase |
1543 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
1544 pcie_bar_br_write(base, 0, fdt_immr_pa |
1545 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
1549 decode_win_pcie_valid(void)
1552 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX));
1555 /**************************************************************************
1556 * IDMA windows routines
1557 **************************************************************************/
1558 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY)
1560 idma_bare_read(u_long base, int i)
1564 v = win_idma_bare_read(base);
1571 idma_bare_write(u_long base, int i, int val)
1575 v = win_idma_bare_read(base);
1578 win_idma_bare_write(base, v);
1582 * Sets channel protection 'val' for window 'w' on channel 'c'
1585 idma_cap_write(u_long base, int c, int w, int val)
1589 v = win_idma_cap_read(base, c);
1590 v &= ~(0x3 << (w * 2));
1591 v |= (val << (w * 2));
1592 win_idma_cap_write(base, c, v);
1596 * Set protection 'val' on all channels for window 'w'
1599 idma_set_prot(u_long base, int w, int val)
1603 for (c = 0; c < MV_IDMA_CHAN_MAX; c++)
1604 idma_cap_write(base, c, w, val);
1608 win_idma_can_remap(int i)
1611 /* IDMA decode windows 0-3 have remap capability */
1619 decode_win_idma_setup(u_long base)
1624 if (pm_is_disabled(CPU_PM_CTRL_IDMA))
1627 * Disable and clear all IDMA windows, revoke protection for all channels
1629 for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
1631 idma_bare_write(base, i, 1);
1632 win_idma_br_write(base, i, 0);
1633 win_idma_sz_write(base, i, 0);
1634 if (win_idma_can_remap(i) == 1)
1635 win_idma_har_write(base, i, 0);
1637 for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
1638 win_idma_cap_write(base, i, 0);
1641 * Set up access to all active DRAM banks
1643 for (i = 0; i < MV_WIN_DDR_MAX; i++)
1644 if (ddr_is_active(i)) {
1645 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
1646 sz = ((ddr_size(i) - 1) & 0xffff0000);
1648 /* Place DDR entries in non-remapped windows */
1649 for (j = 0; j < MV_WIN_IDMA_MAX; j++)
1650 if (win_idma_can_remap(j) != 1 &&
1651 idma_bare_read(base, j) == 1) {
1653 /* Configure window */
1654 win_idma_br_write(base, j, br);
1655 win_idma_sz_write(base, j, sz);
1657 /* Set protection RW on all channels */
1658 idma_set_prot(base, j, 0x3);
1661 idma_bare_write(base, j, 0);
1667 * Remaining targets -- from statically defined table
1669 for (i = 0; i < idma_wins_no; i++)
1670 if (idma_wins[i].target > 0) {
1671 br = (idma_wins[i].base & 0xffff0000) |
1672 (idma_wins[i].attr << 8) | idma_wins[i].target;
1673 sz = ((idma_wins[i].size - 1) & 0xffff0000);
1675 /* Set the first free IDMA window */
1676 for (j = 0; j < MV_WIN_IDMA_MAX; j++) {
1677 if (idma_bare_read(base, j) == 0)
1680 /* Configure window */
1681 win_idma_br_write(base, j, br);
1682 win_idma_sz_write(base, j, sz);
1683 if (win_idma_can_remap(j) &&
1684 idma_wins[j].remap >= 0)
1685 win_idma_har_write(base, j,
1686 idma_wins[j].remap);
1688 /* Set protection RW on all channels */
1689 idma_set_prot(base, j, 0x3);
1692 idma_bare_write(base, j, 0);
1699 decode_win_idma_valid(void)
1701 const struct decode_win *wintab;
1705 if (idma_wins_no > MV_WIN_IDMA_MAX) {
1706 printf("IDMA windows: too many entries: %d\n", idma_wins_no);
1709 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
1710 if (ddr_is_active(i))
1713 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) {
1714 printf("IDMA windows: too many entries: %d, available: %d\n",
1715 idma_wins_no, MV_WIN_IDMA_MAX - c);
1721 for (i = 0; i < idma_wins_no; i++, wintab++) {
1723 if (wintab->target == 0) {
1724 printf("IDMA window#%d: DDR target window is not "
1725 "supposed to be reprogrammed!\n", i);
1729 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
1730 printf("IDMA window#%d: not capable of remapping, but "
1731 "val 0x%08x defined\n", i, wintab->remap);
1738 if (s > (0xFFFFFFFF - b + 1)) {
1739 /* XXX this boundary check should account for 64bit and
1741 printf("IDMA window#%d: no space for size 0x%08x at "
1742 "0x%08x\n", i, s, b);
1747 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]);
1749 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps "
1750 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
1752 idma_wins[j].base + idma_wins[j].size - 1);
1761 decode_win_idma_dump(u_long base)
1765 if (pm_is_disabled(CPU_PM_CTRL_IDMA))
1768 for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
1769 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i,
1770 win_idma_br_read(base, i), win_idma_sz_read(base, i));
1772 if (win_idma_can_remap(i))
1773 printf(", ha 0x%08x", win_idma_har_read(base, i));
1777 for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
1778 printf("IDMA channel#%d: ap 0x%08x\n", i,
1779 win_idma_cap_read(base, i));
1780 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base));
1784 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */
1786 decode_win_idma_valid(void)
1793 decode_win_idma_setup(u_long base)
1798 decode_win_idma_dump(u_long base)
1803 /**************************************************************************
1804 * XOR windows routines
1805 **************************************************************************/
1806 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
1808 xor_ctrl_read(u_long base, int i, int c, int e)
1811 v = win_xor_ctrl_read(base, c, e);
1818 xor_ctrl_write(u_long base, int i, int c, int e, int val)
1822 v = win_xor_ctrl_read(base, c, e);
1825 win_xor_ctrl_write(base, c, e, v);
1829 * Set channel protection 'val' for window 'w' on channel 'c'
1832 xor_chan_write(u_long base, int c, int e, int w, int val)
1836 v = win_xor_ctrl_read(base, c, e);
1837 v &= ~(0x3 << (w * 2 + 16));
1838 v |= (val << (w * 2 + 16));
1839 win_xor_ctrl_write(base, c, e, v);
1843 * Set protection 'val' on all channels for window 'w' on engine 'e'
1846 xor_set_prot(u_long base, int w, int e, int val)
1850 for (c = 0; c < MV_XOR_CHAN_MAX; c++)
1851 xor_chan_write(base, c, e, w, val);
1855 win_xor_can_remap(int i)
1858 /* XOR decode windows 0-3 have remap capability */
1872 case MV_DEV_88F6281:
1873 case MV_DEV_88F6282:
1874 case MV_DEV_MV78130:
1875 case MV_DEV_MV78160:
1876 case MV_DEV_MV78230:
1877 case MV_DEV_MV78260:
1878 case MV_DEV_MV78460:
1880 case MV_DEV_MV78100:
1881 case MV_DEV_MV78100_Z0:
1889 xor_active_dram(u_long base, int c, int e, int *window)
1895 * Set up access to all active DRAM banks
1898 for (i = 0; i < m; i++)
1899 if (ddr_is_active(i)) {
1900 br = ddr_base(i) | (ddr_attr(i) << 8) |
1902 sz = ((ddr_size(i) - 1) & 0xffff0000);
1904 /* Place DDR entries in non-remapped windows */
1905 for (w = 0; w < MV_WIN_XOR_MAX; w++)
1906 if (win_xor_can_remap(w) != 1 &&
1907 (xor_ctrl_read(base, w, c, e) == 0) &&
1909 /* Configure window */
1910 win_xor_br_write(base, w, e, br);
1911 win_xor_sz_write(base, w, e, sz);
1913 /* Set protection RW on all channels */
1914 xor_set_prot(base, w, e, 0x3);
1917 xor_ctrl_write(base, w, c, e, 1);
1925 decode_win_xor_setup(u_long base)
1928 int i, j, z, e = 1, m, window;
1930 if (pm_is_disabled(CPU_PM_CTRL_XOR))
1934 * Disable and clear all XOR windows, revoke protection for all
1938 for (j = 0; j < m; j++, e--) {
1940 /* Number of non-remaped windows */
1941 window = MV_XOR_NON_REMAP - 1;
1943 for (i = 0; i < MV_WIN_XOR_MAX; i++) {
1944 win_xor_br_write(base, i, e, 0);
1945 win_xor_sz_write(base, i, e, 0);
1948 if (win_xor_can_remap(i) == 1)
1949 win_xor_har_write(base, i, e, 0);
1951 for (i = 0; i < MV_XOR_CHAN_MAX; i++) {
1952 win_xor_ctrl_write(base, i, e, 0);
1953 xor_active_dram(base, i, e, &window);
1957 * Remaining targets -- from a statically defined table
1959 for (i = 0; i < xor_wins_no; i++)
1960 if (xor_wins[i].target > 0) {
1961 br = (xor_wins[i].base & 0xffff0000) |
1962 (xor_wins[i].attr << 8) |
1964 sz = ((xor_wins[i].size - 1) & 0xffff0000);
1966 /* Set the first free XOR window */
1967 for (z = 0; z < MV_WIN_XOR_MAX; z++) {
1968 if (xor_ctrl_read(base, z, 0, e) &&
1969 xor_ctrl_read(base, z, 1, e))
1972 /* Configure window */
1973 win_xor_br_write(base, z, e, br);
1974 win_xor_sz_write(base, z, e, sz);
1975 if (win_xor_can_remap(z) &&
1976 xor_wins[z].remap >= 0)
1977 win_xor_har_write(base, z, e,
1980 /* Set protection RW on all channels */
1981 xor_set_prot(base, z, e, 0x3);
1984 xor_ctrl_write(base, z, 0, e, 1);
1985 xor_ctrl_write(base, z, 1, e, 1);
1993 decode_win_xor_valid(void)
1995 const struct decode_win *wintab;
1999 if (xor_wins_no > MV_WIN_XOR_MAX) {
2000 printf("XOR windows: too many entries: %d\n", xor_wins_no);
2003 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
2004 if (ddr_is_active(i))
2007 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) {
2008 printf("XOR windows: too many entries: %d, available: %d\n",
2009 xor_wins_no, MV_WIN_IDMA_MAX - c);
2015 for (i = 0; i < xor_wins_no; i++, wintab++) {
2017 if (wintab->target == 0) {
2018 printf("XOR window#%d: DDR target window is not "
2019 "supposed to be reprogrammed!\n", i);
2023 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
2024 printf("XOR window#%d: not capable of remapping, but "
2025 "val 0x%08x defined\n", i, wintab->remap);
2032 if (s > (0xFFFFFFFF - b + 1)) {
2034 * XXX this boundary check should account for 64bit
2037 printf("XOR window#%d: no space for size 0x%08x at "
2038 "0x%08x\n", i, s, b);
2043 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]);
2045 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps "
2046 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
2048 xor_wins[j].base + xor_wins[j].size - 1);
2057 decode_win_xor_dump(u_long base)
2062 if (pm_is_disabled(CPU_PM_CTRL_XOR))
2065 for (j = 0; j < xor_max_eng(); j++, e--) {
2066 for (i = 0; i < MV_WIN_XOR_MAX; i++) {
2067 printf("XOR window#%d: b 0x%08x, s 0x%08x", i,
2068 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e));
2070 if (win_xor_can_remap(i))
2071 printf(", ha 0x%08x", win_xor_har_read(base, i, e));
2075 for (i = 0; i < MV_XOR_CHAN_MAX; i++)
2076 printf("XOR control#%d: 0x%08x\n", i,
2077 win_xor_ctrl_read(base, i, e));
2082 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */
2084 decode_win_xor_valid(void)
2091 decode_win_xor_setup(u_long base)
2096 decode_win_xor_dump(u_long base)
2101 /**************************************************************************
2102 * SATA windows routines
2103 **************************************************************************/
2105 decode_win_sata_setup(u_long base)
2110 if (pm_is_disabled(CPU_PM_CTRL_SATA))
2113 for (i = 0; i < MV_WIN_SATA_MAX; i++) {
2114 win_sata_cr_write(base, i, 0);
2115 win_sata_br_write(base, i, 0);
2118 for (i = 0; i < MV_WIN_DDR_MAX; i++)
2119 if (ddr_is_active(i)) {
2120 cr = ((ddr_size(i) - 1) & 0xffff0000) |
2121 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
2124 /* Use the first available SATA window */
2125 for (j = 0; j < MV_WIN_SATA_MAX; j++) {
2126 if ((win_sata_cr_read(base, j) & 1) != 0)
2129 win_sata_br_write(base, j, br);
2130 win_sata_cr_write(base, j, cr);
2136 #ifdef SOC_MV_ARMADA38X
2138 * Configure AHCI decoding windows
2141 decode_win_ahci_setup(u_long base)
2143 uint32_t br, cr, sz;
2146 for (i = 0; i < MV_WIN_SATA_MAX; i++) {
2147 win_sata_cr_write(base, i, 0);
2148 win_sata_br_write(base, i, 0);
2149 win_sata_sz_write(base, i, 0);
2152 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
2153 if (ddr_is_active(i)) {
2154 cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
2155 (ddr_target(i) << IO_WIN_TGT_SHIFT) |
2158 sz = (ddr_size(i) - 1) &
2159 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT);
2161 /* Use first available SATA window */
2162 for (j = 0; j < MV_WIN_SATA_MAX; j++) {
2163 if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK)
2166 /* BASE is set to DRAM base (0x00000000) */
2167 win_sata_br_write(base, j, br);
2168 /* CTRL targets DRAM ctrl with 0x0E or 0x0D */
2169 win_sata_cr_write(base, j, cr);
2170 /* SIZE is set to 16MB - max value */
2171 win_sata_sz_write(base, j, sz);
2179 decode_win_ahci_dump(u_long base)
2183 for (i = 0; i < MV_WIN_SATA_MAX; i++)
2184 printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i,
2185 win_sata_cr_read(base, i), win_sata_br_read(base, i),
2186 win_sata_sz_read(base,i));
2191 * Provide dummy functions to satisfy the build
2192 * for SoC's not equipped with AHCI controller
2195 decode_win_ahci_setup(u_long base)
2200 decode_win_ahci_dump(u_long base)
2206 decode_win_sata_valid(void)
2211 if (dev == MV_DEV_88F5281)
2214 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX));
2218 decode_win_sdhci_setup(u_long base)
2223 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) {
2224 win_sdhci_cr_write(base, i, 0);
2225 win_sdhci_br_write(base, i, 0);
2228 for (i = 0; i < MV_WIN_DDR_MAX; i++)
2229 if (ddr_is_active(i)) {
2231 cr = (((ddr_size(i) - 1) &
2232 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) |
2233 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
2234 (ddr_target(i) << IO_WIN_TGT_SHIFT) |
2237 /* Use the first available SDHCI window */
2238 for (j = 0; j < MV_WIN_SDHCI_MAX; j++) {
2239 if (win_sdhci_cr_read(base, j) & IO_WIN_ENA_MASK)
2242 win_sdhci_cr_write(base, j, cr);
2243 win_sdhci_br_write(base, j, br);
2250 decode_win_sdhci_dump(u_long base)
2254 for (i = 0; i < MV_WIN_SDHCI_MAX; i++)
2255 printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i,
2256 win_sdhci_cr_read(base, i), win_sdhci_br_read(base, i));
2260 decode_win_sdhci_valid(void)
2263 #ifdef SOC_MV_ARMADA38X
2264 return (decode_win_can_cover_ddr(MV_WIN_SDHCI_MAX));
2267 /* Satisfy platforms not equipped with this controller. */
2271 /**************************************************************************
2272 * FDT parsing routines.
2273 **************************************************************************/
2276 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples,
2280 pcell_t addr_cells, par_addr_cells, size_cells;
2281 int len, tuple_size, tuples_count;
2283 node = OF_finddevice(nodename);
2287 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
2290 par_addr_cells = fdt_parent_addr_cells(node);
2291 if (par_addr_cells > 2)
2294 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
2297 /* Note the OF_getprop_alloc() cannot be used at this early stage. */
2298 len = OF_getprop(node, "ranges", buf, size);
2301 * XXX this does not handle the empty 'ranges;' case, which is
2302 * legitimate and should be allowed.
2304 tuples_count = len / tuple_size;
2305 if (tuples_count <= 0)
2308 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2)
2311 *tuples = tuples_count;
2312 *tuplesize = tuple_size;
2317 win_cpu_from_dt(void)
2321 int i, entry_size, err, t, tuple_size, tuples;
2322 u_long sram_base, sram_size;
2325 /* Retrieve 'ranges' property of '/localbus' node. */
2326 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges),
2327 &tuples, &tuple_size)) == 0) {
2329 * Fill CPU decode windows table.
2331 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl));
2333 entry_size = tuple_size / sizeof(pcell_t);
2334 cpu_wins_no = tuples;
2337 if (tuples > nitems(cpu_win_tbl)) {
2338 debugf("too many tuples to fit into cpu_win_tbl\n");
2342 for (i = 0, t = 0; t < tuples; i += entry_size, t++) {
2343 cpu_win_tbl[t].target = 1;
2344 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]);
2345 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]);
2346 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]);
2347 cpu_win_tbl[t].remap = ~0;
2348 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x "
2349 "size = 0x%0x remap = 0x%0x\n",
2350 cpu_win_tbl[t].target,
2351 cpu_win_tbl[t].attr, cpu_win_tbl[t].base,
2352 cpu_win_tbl[t].size, cpu_win_tbl[t].remap);
2357 * Retrieve CESA SRAM data.
2359 if ((node = OF_finddevice("sram")) != -1)
2360 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram"))
2363 if ((node = OF_finddevice("/")) == 0)
2366 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0)
2367 /* SRAM block is not always present. */
2370 sram_base = sram_size = 0;
2371 if (fdt_regsize(node, &sram_base, &sram_size) != 0)
2375 if (t >= nitems(cpu_win_tbl)) {
2376 debugf("cannot fit CESA tuple into cpu_win_tbl\n");
2380 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
2381 #ifdef SOC_MV_ARMADA38X
2382 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0);
2384 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
2386 cpu_win_tbl[t].base = sram_base;
2387 cpu_win_tbl[t].size = sram_size;
2388 cpu_win_tbl[t].remap = ~0;
2390 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);
2392 /* Check if there is a second CESA node */
2393 while ((node = OF_peer(node)) != 0) {
2394 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) {
2395 if (fdt_regsize(node, &sram_base, &sram_size) != 0)
2405 if (t >= nitems(cpu_win_tbl)) {
2406 debugf("cannot fit CESA tuple into cpu_win_tbl\n");
2410 /* Configure window for CESA1 */
2411 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
2412 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
2413 cpu_win_tbl[t].base = sram_base;
2414 cpu_win_tbl[t].size = sram_size;
2415 cpu_win_tbl[t].remap = ~0;
2417 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);
2423 fdt_win_process(phandle_t child)
2426 struct soc_node_spec *soc_node;
2427 int addr_cells, size_cells;
2431 for (i = 0; soc_nodes[i].compat != NULL; i++) {
2433 soc_node = &soc_nodes[i];
2435 /* Setup only for enabled devices */
2436 if (ofw_bus_node_status_okay(child) == 0)
2439 if (!ofw_bus_node_is_compatible(child, soc_node->compat))
2442 if (fdt_addrsize_cells(OF_parent(child), &addr_cells,
2446 if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg))
2449 if (OF_getprop(child, "reg", ®, sizeof(reg)) <= 0)
2452 if (addr_cells <= 2)
2453 base = fdt_data_get(®[0], addr_cells);
2455 base = fdt_data_get(®[addr_cells - 2], 2);
2456 size = fdt_data_get(®[addr_cells], size_cells);
2458 base = (base & 0x000fffff) | fdt_immr_va;
2459 if (soc_node->decode_handler != NULL)
2460 soc_node->decode_handler(base);
2464 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL))
2465 soc_node->dump_handler(base);
2473 phandle_t node, child, sb;
2474 phandle_t child_pci;
2478 node = OF_finddevice("/");
2480 panic("fdt_win_setup: no root node");
2483 * Traverse through all children of root and simple-bus nodes.
2484 * For each found device retrieve decode windows data (if applicable).
2486 child = OF_child(node);
2487 while (child != 0) {
2488 /* Lookup for callback and run */
2489 err = fdt_win_process(child);
2493 /* Process Marvell Armada-XP/38x PCIe controllers */
2494 if (ofw_bus_node_is_compatible(child, "marvell,armada-370-pcie")) {
2495 child_pci = OF_child(child);
2496 while (child_pci != 0) {
2497 err = fdt_win_process(child_pci);
2501 child_pci = OF_peer(child_pci);
2506 * Once done with root-level children let's move down to
2507 * simple-bus and its children.
2509 child = OF_peer(child);
2510 if ((child == 0) && (node == OF_finddevice("/"))) {
2511 sb = node = fdt_find_compatible(node, "simple-bus", 0);
2514 child = OF_child(node);
2517 * Next, move one more level down to internal-regs node (if
2518 * it is present) and its children. This node also have
2519 * "simple-bus" compatible.
2521 if ((child == 0) && (node == sb)) {
2522 node = fdt_find_compatible(node, "simple-bus", 0);
2525 child = OF_child(node);
2533 fdt_fixup_busfreq(phandle_t root)
2538 freq = cpu_to_fdt32(get_tclk());
2541 * Fix bus speed in cpu node
2543 if ((sb = OF_finddevice("cpu")) != 0)
2544 if (fdt_is_compatible_strict(sb, "ARM,88VS584"))
2545 OF_setprop(sb, "bus-frequency", (void *)&freq,
2549 * This fixup sets the simple-bus bus-frequency property.
2551 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0)
2552 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq));
2556 fdt_fixup_ranges(phandle_t root)
2559 pcell_t par_addr_cells, addr_cells, size_cells;
2560 pcell_t ranges[3], reg[2], *rangesptr;
2561 int len, tuple_size, tuples_count;
2564 /* Fix-up SoC ranges according to real fdt_immr_pa */
2565 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) {
2566 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 &&
2567 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) {
2568 tuple_size = sizeof(pcell_t) * (par_addr_cells +
2569 addr_cells + size_cells);
2570 len = OF_getprop(node, "ranges", ranges,
2572 tuples_count = len / tuple_size;
2573 /* Unexpected settings are not supported */
2574 if (tuples_count != 1)
2577 rangesptr = &ranges[0];
2578 rangesptr += par_addr_cells;
2579 base = fdt_data_get((void *)rangesptr, addr_cells);
2580 *rangesptr = cpu_to_fdt32(fdt_immr_pa);
2581 if (OF_setprop(node, "ranges", (void *)&ranges[0],
2582 sizeof(ranges)) < 0)
2587 /* Fix-up PCIe reg according to real PCIe registers' PA */
2588 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) {
2589 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
2590 &size_cells) == 0) {
2591 tuple_size = sizeof(pcell_t) * (par_addr_cells +
2593 len = OF_getprop(node, "reg", reg, sizeof(reg));
2594 tuples_count = len / tuple_size;
2595 /* Unexpected settings are not supported */
2596 if (tuples_count != 1)
2599 base = fdt_data_get((void *)®[0], par_addr_cells);
2600 base &= ~0xFF000000;
2601 base |= fdt_immr_pa;
2602 reg[0] = cpu_to_fdt32(base);
2603 if (OF_setprop(node, "reg", (void *)®[0],
2608 /* Fix-up succeeded. May return and continue */
2614 * In case of any error while fixing ranges just hang.
2615 * 1. No message can be displayed yet since console
2616 * is not initialized.
2617 * 2. Going further will cause failure on bus_space_map()
2618 * relying on the wrong ranges or data abort when
2619 * accessing PCIe registers.
2624 struct fdt_fixup_entry fdt_fixup_table[] = {
2625 { "mrvl,DB-88F6281", &fdt_fixup_busfreq },
2626 { "mrvl,DB-78460", &fdt_fixup_busfreq },
2627 { "mrvl,DB-78460", &fdt_fixup_ranges },
2633 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
2637 if (!ofw_bus_node_is_compatible(node, "mrvl,pic") &&
2638 !ofw_bus_node_is_compatible(node, "mrvl,mpic"))
2641 *interrupt = fdt32_to_cpu(intr[0]);
2642 *trig = INTR_TRIGGER_CONFORM;
2643 *pol = INTR_POLARITY_CONFORM;
2648 fdt_pic_decode_t fdt_pic_table[] = {
2649 #ifdef SOC_MV_ARMADA38X
2660 uint32_t sar_low, sar_high;
2662 #if defined(SOC_MV_ARMADAXP)
2663 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
2664 SAMPLE_AT_RESET_HI);
2665 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
2666 SAMPLE_AT_RESET_LO);
2667 #elif defined(SOC_MV_ARMADA38X)
2669 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
2673 * TODO: Add getting proper values for other SoC configurations
2679 return (((uint64_t)sar_high << 32) | sar_low);