2 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD.
5 * Developed by Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
41 #include <sys/reboot.h>
43 #include <dev/fdt/fdt_common.h>
44 #include <dev/ofw/openfirm.h>
45 #include <dev/ofw/ofw_bus_subr.h>
47 #include <machine/bus.h>
48 #include <machine/fdt.h>
49 #include <machine/vmparam.h>
50 #include <machine/intr.h>
52 #include <arm/mv/mvreg.h>
53 #include <arm/mv/mvvar.h>
54 #include <arm/mv/mvwin.h>
57 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory");
65 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \
66 printf(fmt,##args); } while (0)
68 #define debugf(fmt, args...)
77 static int win_eth_can_remap(int i);
79 static int decode_win_cesa_valid(void);
80 static int decode_win_cpu_valid(void);
81 static int decode_win_usb_valid(void);
82 static int decode_win_usb3_valid(void);
83 static int decode_win_eth_valid(void);
84 static int decode_win_pcie_valid(void);
85 static int decode_win_sata_valid(void);
86 static int decode_win_sdhci_valid(void);
88 static int decode_win_idma_valid(void);
89 static int decode_win_xor_valid(void);
91 static void decode_win_cpu_setup(void);
92 #ifdef SOC_MV_ARMADAXP
93 static int decode_win_sdram_fixup(void);
95 static void decode_win_cesa_setup(u_long);
96 static void decode_win_usb_setup(u_long);
97 static void decode_win_usb3_setup(u_long);
98 static void decode_win_eth_setup(u_long);
99 static void decode_win_neta_setup(u_long);
100 static void decode_win_sata_setup(u_long);
101 static void decode_win_ahci_setup(u_long);
102 static void decode_win_sdhci_setup(u_long);
104 static void decode_win_idma_setup(u_long);
105 static void decode_win_xor_setup(u_long);
107 static void decode_win_cesa_dump(u_long);
108 static void decode_win_usb_dump(u_long);
109 static void decode_win_usb3_dump(u_long);
110 static void decode_win_eth_dump(u_long base);
111 static void decode_win_neta_dump(u_long base);
112 static void decode_win_idma_dump(u_long base);
113 static void decode_win_xor_dump(u_long base);
114 static void decode_win_ahci_dump(u_long base);
115 static void decode_win_sdhci_dump(u_long);
116 static void decode_win_pcie_dump(u_long);
118 static int fdt_get_ranges(const char *, void *, int, int *, int *);
119 #ifdef SOC_MV_ARMADA38X
120 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
121 int *trig, int *pol);
124 static int win_cpu_from_dt(void);
125 static int fdt_win_setup(void);
127 static uint32_t dev_mask = 0;
128 static int cpu_wins_no = 0;
129 static int eth_port = 0;
130 static int usb_port = 0;
132 static struct decode_win cpu_win_tbl[MAX_CPU_WIN];
134 const struct decode_win *cpu_wins = cpu_win_tbl;
136 typedef void (*decode_win_setup_t)(u_long);
137 typedef void (*dump_win_t)(u_long);
140 * The power status of device feature is only supported on
141 * Kirkwood and Discovery SoCs.
143 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
144 #define SOC_MV_POWER_STAT_SUPPORTED 1
146 #define SOC_MV_POWER_STAT_SUPPORTED 0
149 struct soc_node_spec {
151 decode_win_setup_t decode_handler;
152 dump_win_t dump_handler;
155 static struct soc_node_spec soc_nodes[] = {
156 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump },
157 { "marvell,armada-370-neta", &decode_win_neta_setup, &decode_win_neta_dump },
158 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
159 { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
160 { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump },
161 { "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_ahci_dump },
162 { "marvell,armada-380-sdhci", &decode_win_sdhci_setup, &decode_win_sdhci_dump },
163 { "mrvl,sata", &decode_win_sata_setup, NULL },
164 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump },
165 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump },
166 { "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump },
167 { "mrvl,pcie", &decode_win_pcie_setup, &decode_win_pcie_dump },
168 { NULL, NULL, NULL },
171 struct fdt_pm_mask_entry {
176 static struct fdt_pm_mask_entry fdt_pm_mask_table[] = {
177 { "mrvl,ge", CPU_PM_CTRL_GE(0) },
178 { "mrvl,ge", CPU_PM_CTRL_GE(1) },
179 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) },
180 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) },
181 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) },
182 { "mrvl,xor", CPU_PM_CTRL_XOR },
183 { "mrvl,sata", CPU_PM_CTRL_SATA },
189 pm_is_disabled(uint32_t mask)
191 #if SOC_MV_POWER_STAT_SUPPORTED
192 return (soc_power_ctrl_get(mask) == mask ? 0 : 1);
199 * Disable device using power management register.
200 * 1 - Device Power On
201 * 0 - Device Power Off
202 * Mask can be set in loader.
204 * loader> set hw.pm-disable-mask=0x2
207 * |-------------------------------|
208 * | Device | Kirkwood | Discovery |
209 * |-------------------------------|
210 * | USB0 | 0x00008 | 0x020000 |
211 * |-------------------------------|
212 * | USB1 | - | 0x040000 |
213 * |-------------------------------|
214 * | USB2 | - | 0x080000 |
215 * |-------------------------------|
216 * | GE0 | 0x00001 | 0x000002 |
217 * |-------------------------------|
218 * | GE1 | - | 0x000004 |
219 * |-------------------------------|
220 * | IDMA | - | 0x100000 |
221 * |-------------------------------|
222 * | XOR | 0x10000 | 0x200000 |
223 * |-------------------------------|
224 * | CESA | 0x20000 | 0x400000 |
225 * |-------------------------------|
226 * | SATA | 0x04000 | 0x004000 |
227 * --------------------------------|
228 * This feature can be used only on Kirkwood and Discovery
232 pm_disable_device(int mask)
237 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
238 printf("Power Management Register: 0%x\n", reg);
241 soc_power_ctrl_set(reg);
242 printf("Device %x is disabled\n", mask);
244 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
245 printf("Power Management Register: 0%x\n", reg);
250 fdt_pm(phandle_t node)
252 uint32_t cpu_pm_ctrl;
256 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL);
257 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) {
258 if (dev_mask & (1 << i))
261 compat = ofw_bus_node_is_compatible(node,
262 fdt_pm_mask_table[i].compat);
263 #if defined(SOC_MV_KIRKWOOD)
264 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) {
265 dev_mask |= (1 << i);
269 dev_mask |= (1 << i);
273 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) {
274 dev_mask |= (1 << i);
278 dev_mask |= (1 << i);
288 read_cpu_ctrl(uint32_t reg)
291 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg));
295 write_cpu_ctrl(uint32_t reg, uint32_t val)
298 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val);
301 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
303 read_cpu_mp_clocks(uint32_t reg)
306 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg));
310 write_cpu_mp_clocks(uint32_t reg, uint32_t val)
313 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val);
317 read_cpu_misc(uint32_t reg)
320 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg));
324 write_cpu_misc(uint32_t reg, uint32_t val)
327 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val);
335 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X)
336 write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
337 write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
339 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
340 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
356 case MV_DEV_88RC8180:
357 case MV_DEV_MV78100_Z0:
359 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
363 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
367 printf("This ARM Core does not support any extra features\n");
374 * Get the power status of device. This feature is only supported on
375 * Kirkwood and Discovery SoCs.
378 soc_power_ctrl_get(uint32_t mask)
381 #if SOC_MV_POWER_STAT_SUPPORTED
382 if (mask != CPU_PM_CTRL_NONE)
383 mask &= read_cpu_ctrl(CPU_PM_CTRL);
392 * Set the power status of device. This feature is only supported on
393 * Kirkwood and Discovery SoCs.
396 soc_power_ctrl_set(uint32_t mask)
399 #if !defined(SOC_MV_ORION)
400 if (mask != CPU_PM_CTRL_NONE)
401 write_cpu_ctrl(CPU_PM_CTRL, mask);
406 soc_id(uint32_t *dev, uint32_t *rev)
410 * Notice: system identifiers are available in the registers range of
411 * PCIE controller, so using this function is only allowed (and
412 * possible) after the internal registers range has been mapped in via
413 * devmap_bootstrap().
415 *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16;
416 *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff;
422 uint32_t d, r, size, mode;
430 printf("(0x%4x:0x%02x) ", d, r);
435 dev = "Marvell 88F5181";
440 dev = "Marvell 88F5182";
445 dev = "Marvell 88F5281";
454 dev = "Marvell 88F6281";
462 case MV_DEV_88RC8180:
463 dev = "Marvell 88RC8180";
465 case MV_DEV_88RC9480:
466 dev = "Marvell 88RC9480";
468 case MV_DEV_88RC9580:
469 dev = "Marvell 88RC9580";
472 dev = "Marvell 88F6781";
477 dev = "Marvell 88F6282";
484 dev = "Marvell 88F6828";
487 dev = "Marvell 88F6820";
490 dev = "Marvell 88F6810";
492 case MV_DEV_MV78100_Z0:
493 dev = "Marvell MV78100 Z0";
496 dev = "Marvell MV78100";
499 dev = "Marvell MV78160";
502 dev = "Marvell MV78260";
505 dev = "Marvell MV78460";
514 printf(" rev %s", rev);
515 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
517 mode = read_cpu_ctrl(CPU_CONFIG);
518 printf(" Instruction cache prefetch %s, data cache prefetch %s\n",
519 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled",
520 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled");
525 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE;
526 printf(" 256KB 4-way set-associative %s unified L2 cache\n",
527 mode ? "write-through" : "write-back");
530 mode = read_cpu_ctrl(CPU_CONTROL);
531 size = mode & CPU_CONTROL_L2_SIZE;
532 mode = mode & CPU_CONTROL_L2_MODE;
533 printf(" %s set-associative %s unified L2 cache\n",
534 size ? "256KB 4-way" : "512KB 8-way",
535 mode ? "write-through" : "write-back");
543 platform_identify(void *dummy)
549 * XXX Board identification e.g. read out from FPGA or similar should
553 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify,
558 mv_enter_debugger(void *dummy)
561 if (boothowto & RB_KDB)
562 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
564 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL);
574 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask);
577 pm_disable_device(mask);
579 /* Retrieve data about physical addresses from device tree. */
580 if ((err = win_cpu_from_dt()) != 0)
583 /* Retrieve our ID: some windows facilities vary between SoC models */
586 #ifdef SOC_MV_ARMADAXP
587 if ((err = decode_win_sdram_fixup()) != 0)
591 if (!decode_win_cpu_valid() || !decode_win_usb_valid() ||
592 !decode_win_eth_valid() || !decode_win_idma_valid() ||
593 !decode_win_pcie_valid() || !decode_win_sata_valid() ||
594 !decode_win_xor_valid() || !decode_win_usb3_valid() ||
595 !decode_win_sdhci_valid() || !decode_win_cesa_valid())
598 decode_win_cpu_setup();
600 soc_dump_decode_win();
604 if ((err = fdt_win_setup()) != 0)
610 /**************************************************************************
611 * Decode windows registers accessors
612 **************************************************************************/
613 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
614 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
615 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
616 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
617 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
618 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
619 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
620 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
622 WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL)
623 WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE)
624 WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL)
625 WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE)
627 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL)
628 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE)
629 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL)
630 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE)
632 #ifdef SOC_MV_ARMADA38X
633 WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL)
634 WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE)
635 WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL)
636 WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE)
639 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
640 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
641 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
642 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)
643 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)
644 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)
646 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE)
647 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE)
648 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP)
649 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL)
650 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE)
651 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE)
652 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP)
653 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL)
655 WIN_REG_BASE_RD(win_eth, bare, 0x290)
656 WIN_REG_BASE_RD(win_eth, epap, 0x294)
657 WIN_REG_BASE_WR(win_eth, bare, 0x290)
658 WIN_REG_BASE_WR(win_eth, epap, 0x294)
660 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL);
661 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE);
662 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP);
663 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL);
664 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE);
665 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP);
666 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE);
667 WIN_REG_BASE_IDX_RD(pcie_bar, brh, MV_PCIE_BAR_BASE_H);
668 WIN_REG_BASE_IDX_RD(pcie_bar, cr, MV_PCIE_BAR_CTRL);
669 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE);
670 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H);
671 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL);
673 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE)
674 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE)
675 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP)
676 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP)
677 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE)
678 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE)
679 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP)
680 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP)
681 WIN_REG_BASE_RD(win_idma, bare, 0xa80)
682 WIN_REG_BASE_WR(win_idma, bare, 0xa80)
684 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL);
685 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE);
686 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL);
687 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE);
688 #if defined(SOC_MV_ARMADA38X)
689 WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE);
690 WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE);
693 WIN_REG_BASE_IDX_RD(win_sdhci, cr, MV_WIN_SDHCI_CTRL);
694 WIN_REG_BASE_IDX_RD(win_sdhci, br, MV_WIN_SDHCI_BASE);
695 WIN_REG_BASE_IDX_WR(win_sdhci, cr, MV_WIN_SDHCI_CTRL);
696 WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE);
699 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
700 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
701 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
702 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
705 * On 88F6781 (Dove) SoC DDR Controller is accessed through
706 * single MBUS <-> AXI bridge. In this case we provide emulated
707 * ddr_br_read() and ddr_sz_read() functions to keep compatibility
708 * with common decoding windows setup code.
711 static inline uint32_t ddr_br_read(int i)
715 /* Read Memory Address Map Register for CS i */
716 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0);
718 /* Return CS i base address */
719 return (mmap & 0xFF000000);
722 static inline uint32_t ddr_sz_read(int i)
726 /* Read Memory Address Map Register for CS i */
727 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0);
729 /* Extract size of CS space in 64kB units */
730 size = (1 << ((mmap >> 16) & 0x0F));
732 /* Return CS size and enable/disable status */
733 return (((size - 1) << 16) | (mmap & 0x01));
737 /**************************************************************************
738 * Decode windows helper routines
739 **************************************************************************/
741 soc_dump_decode_win(void)
748 for (i = 0; i < MV_WIN_CPU_MAX; i++) {
749 printf("CPU window#%d: c 0x%08x, b 0x%08x", i,
753 if (win_cpu_can_remap(i))
754 printf(", rl 0x%08x, rh 0x%08x",
755 win_cpu_remap_l_read(i),
756 win_cpu_remap_h_read(i));
760 printf("Internal regs base: 0x%08x\n",
761 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0));
763 for (i = 0; i < MV_WIN_DDR_MAX; i++)
764 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i,
765 ddr_br_read(i), ddr_sz_read(i));
768 /**************************************************************************
769 * CPU windows routines
770 **************************************************************************/
772 win_cpu_can_remap(int i)
778 /* Depending on the SoC certain windows have remap capability */
779 if ((dev == MV_DEV_88F5182 && i < 2) ||
780 (dev == MV_DEV_88F5281 && i < 4) ||
781 (dev == MV_DEV_88F6281 && i < 4) ||
782 (dev == MV_DEV_88F6282 && i < 4) ||
783 (dev == MV_DEV_88F6828 && i < 20) ||
784 (dev == MV_DEV_88F6820 && i < 20) ||
785 (dev == MV_DEV_88F6810 && i < 20) ||
786 (dev == MV_DEV_88RC8180 && i < 2) ||
787 (dev == MV_DEV_88F6781 && i < 4) ||
788 (dev == MV_DEV_MV78100_Z0 && i < 8) ||
789 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8))
795 /* XXX This should check for overlapping remap fields too.. */
797 decode_win_overlap(int win, int win_no, const struct decode_win *wintab)
799 const struct decode_win *tab;
804 for (i = 0; i < win_no; i++, tab++) {
809 if ((tab->base + tab->size - 1) < (wintab + win)->base)
812 else if (((wintab + win)->base + (wintab + win)->size - 1) <
823 decode_win_cpu_valid(void)
828 if (cpu_wins_no > MV_WIN_CPU_MAX) {
829 printf("CPU windows: too many entries: %d\n", cpu_wins_no);
834 for (i = 0; i < cpu_wins_no; i++) {
836 if (cpu_wins[i].target == 0) {
837 printf("CPU window#%d: DDR target window is not "
838 "supposed to be reprogrammed!\n", i);
842 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) {
843 printf("CPU window#%d: not capable of remapping, but "
844 "val 0x%08x defined\n", i, cpu_wins[i].remap);
848 s = cpu_wins[i].size;
849 b = cpu_wins[i].base;
851 if (s > (0xFFFFFFFF - b + 1)) {
853 * XXX this boundary check should account for 64bit
856 printf("CPU window#%d: no space for size 0x%08x at "
857 "0x%08x\n", i, s, b);
862 if (b != rounddown2(b, s)) {
863 printf("CPU window#%d: address 0x%08x is not aligned "
864 "to 0x%08x\n", i, b, s);
869 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]);
871 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps "
872 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
874 cpu_wins[j].base + cpu_wins[j].size - 1);
883 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
890 win = MV_WIN_CPU_MAX - 1;
897 while ((win >= 0) && (win < MV_WIN_CPU_MAX)) {
898 cr = win_cpu_cr_read(win);
899 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0)
901 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) |
902 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) ==
903 ((attr << MV_WIN_CPU_ATTR_SHIFT) |
904 (target << MV_WIN_CPU_TARGET_SHIFT)))
908 if ((win < 0) || (win >= MV_WIN_CPU_MAX) ||
909 ((remap != ~0) && (win_cpu_can_remap(win) == 0)))
912 br = base & 0xffff0000;
913 win_cpu_br_write(win, br);
915 if (win_cpu_can_remap(win)) {
917 win_cpu_remap_l_write(win, remap & 0xffff0000);
918 win_cpu_remap_h_write(win, 0);
921 * Remap function is not used for a given window
922 * (capable of remapping) - set remap field with the
923 * same value as base.
925 win_cpu_remap_l_write(win, base & 0xffff0000);
926 win_cpu_remap_h_write(win, 0);
930 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) |
931 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT;
932 win_cpu_cr_write(win, cr);
938 decode_win_cpu_setup(void)
942 /* Disable all CPU windows */
943 for (i = 0; i < MV_WIN_CPU_MAX; i++) {
944 win_cpu_cr_write(i, 0);
945 win_cpu_br_write(i, 0);
946 if (win_cpu_can_remap(i)) {
947 win_cpu_remap_l_write(i, 0);
948 win_cpu_remap_h_write(i, 0);
952 for (i = 0; i < cpu_wins_no; i++)
953 if (cpu_wins[i].target > 0)
954 decode_win_cpu_set(cpu_wins[i].target,
955 cpu_wins[i].attr, cpu_wins[i].base,
956 cpu_wins[i].size, cpu_wins[i].remap);
960 #ifdef SOC_MV_ARMADAXP
962 decode_win_sdram_fixup(void)
964 struct mem_region mr[FDT_MEM_REGIONS];
965 uint8_t window_valid[MV_WIN_DDR_MAX];
966 int mr_cnt, err, i, j;
967 uint32_t valid_win_num = 0;
969 /* Grab physical memory regions information from device tree. */
970 err = fdt_get_mem_regions(mr, &mr_cnt, NULL);
974 for (i = 0; i < MV_WIN_DDR_MAX; i++)
977 /* Try to match entries from device tree with settings from u-boot */
978 for (i = 0; i < mr_cnt; i++) {
979 for (j = 0; j < MV_WIN_DDR_MAX; j++) {
980 if (ddr_is_active(j) &&
981 (ddr_base(j) == mr[i].mr_start) &&
982 (ddr_size(j) == mr[i].mr_size)) {
989 if (mr_cnt != valid_win_num)
992 /* Destroy windows without corresponding device tree entry */
993 for (j = 0; j < MV_WIN_DDR_MAX; j++) {
994 if (ddr_is_active(j) && (window_valid[j] != 1)) {
995 printf("Disabling SDRAM decoding window: %d\n", j);
1004 * Check if we're able to cover all active DDR banks.
1007 decode_win_can_cover_ddr(int max)
1012 for (i = 0; i < MV_WIN_DDR_MAX; i++)
1013 if (ddr_is_active(i))
1017 printf("Unable to cover all active DDR banks: "
1018 "%d, available windows: %d\n", c, max);
1025 /**************************************************************************
1026 * DDR windows routines
1027 **************************************************************************/
1029 ddr_is_active(int i)
1032 if (ddr_sz_read(i) & 0x1)
1050 return (ddr_br_read(i) & 0xff000000);
1057 return ((ddr_sz_read(i) | 0x00ffffff) + 1);
1066 if (dev == MV_DEV_88RC8180)
1067 return ((ddr_sz_read(i) & 0xf0) >> 4);
1068 if (dev == MV_DEV_88F6781)
1071 return (i == 0 ? 0xe :
1074 (i == 3 ? 0x7 : 0xff))));
1083 if (dev == MV_DEV_88RC8180) {
1084 i = (ddr_sz_read(i) & 0xf0) >> 4;
1085 return (i == 0xe ? 0xc :
1088 (i == 0x7 ? 0xf : 0xc))));
1092 * On SOCs other than 88RC8180 Mbus unit ID for
1093 * DDR SDRAM controller is always 0x0.
1098 /**************************************************************************
1099 * CESA windows routines
1100 **************************************************************************/
1102 decode_win_cesa_valid(void)
1105 return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX));
1109 decode_win_cesa_dump(u_long base)
1113 for (i = 0; i < MV_WIN_CESA_MAX; i++)
1114 printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i,
1115 win_cesa_cr_read(base, i), win_cesa_br_read(base, i));
1119 * Set CESA decode windows.
1122 decode_win_cesa_setup(u_long base)
1128 for (i = 0; i < MV_WIN_CESA_MAX; i++) {
1129 win_cesa_cr_write(base, i, 0);
1130 win_cesa_br_write(base, i, 0);
1133 /* Only access to active DRAM banks is required */
1134 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1135 if (ddr_is_active(i)) {
1139 #ifdef SOC_MV_ARMADA38X
1141 * Armada 38x SoC's equipped with 4GB DRAM
1142 * suffer freeze during CESA operation, if
1143 * MBUS window opened at given DRAM CS reaches
1144 * end of the address space. Apply a workaround
1145 * by setting the window size to the closest possible
1146 * value, i.e. divide it by 2.
1148 if (size + ddr_base(i) == 0x100000000ULL)
1152 cr = (((size - 1) & 0xffff0000) |
1153 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
1154 (ddr_target(i) << IO_WIN_TGT_SHIFT) |
1157 /* Set the first free CESA window */
1158 for (j = 0; j < MV_WIN_CESA_MAX; j++) {
1159 if (win_cesa_cr_read(base, j) & 0x1)
1162 win_cesa_br_write(base, j, br);
1163 win_cesa_cr_write(base, j, cr);
1170 /**************************************************************************
1171 * USB windows routines
1172 **************************************************************************/
1174 decode_win_usb_valid(void)
1177 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX));
1181 decode_win_usb_dump(u_long base)
1185 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1)))
1188 for (i = 0; i < MV_WIN_USB_MAX; i++)
1189 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i,
1190 win_usb_cr_read(base, i), win_usb_br_read(base, i));
1194 * Set USB decode windows.
1197 decode_win_usb_setup(u_long base)
1202 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port)))
1207 for (i = 0; i < MV_WIN_USB_MAX; i++) {
1208 win_usb_cr_write(base, i, 0);
1209 win_usb_br_write(base, i, 0);
1212 /* Only access to active DRAM banks is required */
1213 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1214 if (ddr_is_active(i)) {
1217 * XXX for 6281 we should handle Mbus write
1218 * burst limit field in the ctrl reg
1220 cr = (((ddr_size(i) - 1) & 0xffff0000) |
1221 (ddr_attr(i) << 8) |
1222 (ddr_target(i) << 4) | 1);
1224 /* Set the first free USB window */
1225 for (j = 0; j < MV_WIN_USB_MAX; j++) {
1226 if (win_usb_cr_read(base, j) & 0x1)
1229 win_usb_br_write(base, j, br);
1230 win_usb_cr_write(base, j, cr);
1237 /**************************************************************************
1238 * USB3 windows routines
1239 **************************************************************************/
1240 #ifdef SOC_MV_ARMADA38X
1242 decode_win_usb3_valid(void)
1245 return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX));
1249 decode_win_usb3_dump(u_long base)
1253 for (i = 0; i < MV_WIN_USB3_MAX; i++)
1254 printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i,
1255 win_usb3_cr_read(base, i), win_usb3_br_read(base, i));
1259 * Set USB3 decode windows
1262 decode_win_usb3_setup(u_long base)
1267 for (i = 0; i < MV_WIN_USB3_MAX; i++) {
1268 win_usb3_cr_write(base, i, 0);
1269 win_usb3_br_write(base, i, 0);
1272 /* Only access to active DRAM banks is required */
1273 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1274 if (ddr_is_active(i)) {
1276 cr = (((ddr_size(i) - 1) &
1277 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) |
1278 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
1279 (ddr_target(i) << IO_WIN_TGT_SHIFT) |
1282 /* Set the first free USB3.0 window */
1283 for (j = 0; j < MV_WIN_USB3_MAX; j++) {
1284 if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK)
1287 win_usb3_br_write(base, j, br);
1288 win_usb3_cr_write(base, j, cr);
1296 * Provide dummy functions to satisfy the build
1297 * for SoCs not equipped with USB3
1300 decode_win_usb3_valid(void)
1307 decode_win_usb3_setup(u_long base)
1312 decode_win_usb3_dump(u_long base)
1316 /**************************************************************************
1317 * ETH windows routines
1318 **************************************************************************/
1321 win_eth_can_remap(int i)
1324 /* ETH encode windows 0-3 have remap capability */
1332 eth_bare_read(uint32_t base, int i)
1336 v = win_eth_bare_read(base);
1343 eth_bare_write(uint32_t base, int i, int val)
1347 v = win_eth_bare_read(base);
1350 win_eth_bare_write(base, v);
1354 eth_epap_write(uint32_t base, int i, int val)
1358 v = win_eth_epap_read(base);
1359 v &= ~(0x3 << (i * 2));
1360 v |= (val << (i * 2));
1361 win_eth_epap_write(base, v);
1365 decode_win_eth_dump(u_long base)
1369 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1)))
1372 for (i = 0; i < MV_WIN_ETH_MAX; i++) {
1373 printf("ETH window#%d: b 0x%08x, s 0x%08x", i,
1374 win_eth_br_read(base, i),
1375 win_eth_sz_read(base, i));
1377 if (win_eth_can_remap(i))
1378 printf(", ha 0x%08x",
1379 win_eth_har_read(base, i));
1383 printf("ETH windows: bare 0x%08x, epap 0x%08x\n",
1384 win_eth_bare_read(base),
1385 win_eth_epap_read(base));
1388 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n)
1391 decode_win_eth_setup(u_long base)
1396 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port)))
1401 /* Disable, clear and revoke protection for all ETH windows */
1402 for (i = 0; i < MV_WIN_ETH_MAX; i++) {
1404 eth_bare_write(base, i, 1);
1405 eth_epap_write(base, i, 0);
1406 win_eth_br_write(base, i, 0);
1407 win_eth_sz_write(base, i, 0);
1408 if (win_eth_can_remap(i))
1409 win_eth_har_write(base, i, 0);
1412 /* Only access to active DRAM banks is required */
1413 for (i = 0; i < MV_WIN_DDR_MAX; i++)
1414 if (ddr_is_active(i)) {
1416 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i);
1417 sz = ((ddr_size(i) - 1) & 0xffff0000);
1419 /* Set the first free ETH window */
1420 for (j = 0; j < MV_WIN_ETH_MAX; j++) {
1421 if (eth_bare_read(base, j) == 0)
1424 win_eth_br_write(base, j, br);
1425 win_eth_sz_write(base, j, sz);
1427 /* XXX remapping ETH windows not supported */
1429 /* Set protection RW */
1430 eth_epap_write(base, j, 0x3);
1433 eth_bare_write(base, j, 0);
1440 decode_win_neta_dump(u_long base)
1443 decode_win_eth_dump(base + MV_WIN_NETA_OFFSET);
1447 decode_win_neta_setup(u_long base)
1450 decode_win_eth_setup(base + MV_WIN_NETA_OFFSET);
1454 decode_win_eth_valid(void)
1457 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX));
1460 /**************************************************************************
1461 * PCIE windows routines
1462 **************************************************************************/
1464 decode_win_pcie_dump(u_long base)
1468 printf("PCIE windows base 0x%08lx\n", base);
1469 for (i = 0; i < MV_WIN_PCIE_MAX; i++)
1470 printf("PCIE window#%d: cr 0x%08x br 0x%08x remap 0x%08x\n",
1471 i, win_pcie_cr_read(base, i),
1472 win_pcie_br_read(base, i), win_pcie_remap_read(base, i));
1474 for (i = 0; i < MV_PCIE_BAR_MAX; i++)
1475 printf("PCIE bar#%d: cr 0x%08x br 0x%08x brh 0x%08x\n",
1476 i, pcie_bar_cr_read(base, i),
1477 pcie_bar_br_read(base, i), pcie_bar_brh_read(base, i));
1481 decode_win_pcie_setup(u_long base)
1483 uint32_t size = 0, ddrbase = ~0;
1487 for (i = 0; i < MV_PCIE_BAR_MAX; i++) {
1488 pcie_bar_br_write(base, i,
1489 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
1491 pcie_bar_brh_write(base, i, 0);
1493 pcie_bar_cr_write(base, i, 0);
1496 for (i = 0; i < MV_WIN_PCIE_MAX; i++) {
1497 win_pcie_cr_write(base, i, 0);
1498 win_pcie_br_write(base, i, 0);
1499 win_pcie_remap_write(base, i, 0);
1502 /* On End-Point only set BAR size to 1MB regardless of DDR size */
1503 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL)
1504 & MV_PCIE_ROOT_CMPLX) == 0) {
1505 pcie_bar_cr_write(base, 1, 0xf0000 | 1);
1509 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1510 if (ddr_is_active(i)) {
1511 /* Map DDR to BAR 1 */
1512 cr = (ddr_size(i) - 1) & 0xffff0000;
1513 size += ddr_size(i) & 0xffff0000;
1514 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
1519 /* Use the first available PCIE window */
1520 for (j = 0; j < MV_WIN_PCIE_MAX; j++) {
1521 if (win_pcie_cr_read(base, j) != 0)
1524 win_pcie_br_write(base, j, br);
1525 win_pcie_cr_write(base, j, cr);
1532 * Upper 16 bits in BAR register is interpreted as BAR size
1533 * (in 64 kB units) plus 64kB, so subtract 0x10000
1534 * form value passed to register to get correct value.
1537 pcie_bar_cr_write(base, 1, size | 1);
1538 pcie_bar_br_write(base, 1, ddrbase |
1539 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
1540 pcie_bar_br_write(base, 0, fdt_immr_pa |
1541 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
1545 decode_win_pcie_valid(void)
1548 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX));
1551 /**************************************************************************
1552 * IDMA windows routines
1553 **************************************************************************/
1554 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY)
1556 idma_bare_read(u_long base, int i)
1560 v = win_idma_bare_read(base);
1567 idma_bare_write(u_long base, int i, int val)
1571 v = win_idma_bare_read(base);
1574 win_idma_bare_write(base, v);
1578 * Sets channel protection 'val' for window 'w' on channel 'c'
1581 idma_cap_write(u_long base, int c, int w, int val)
1585 v = win_idma_cap_read(base, c);
1586 v &= ~(0x3 << (w * 2));
1587 v |= (val << (w * 2));
1588 win_idma_cap_write(base, c, v);
1592 * Set protection 'val' on all channels for window 'w'
1595 idma_set_prot(u_long base, int w, int val)
1599 for (c = 0; c < MV_IDMA_CHAN_MAX; c++)
1600 idma_cap_write(base, c, w, val);
1604 win_idma_can_remap(int i)
1607 /* IDMA decode windows 0-3 have remap capability */
1615 decode_win_idma_setup(u_long base)
1620 if (pm_is_disabled(CPU_PM_CTRL_IDMA))
1623 * Disable and clear all IDMA windows, revoke protection for all channels
1625 for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
1627 idma_bare_write(base, i, 1);
1628 win_idma_br_write(base, i, 0);
1629 win_idma_sz_write(base, i, 0);
1630 if (win_idma_can_remap(i) == 1)
1631 win_idma_har_write(base, i, 0);
1633 for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
1634 win_idma_cap_write(base, i, 0);
1637 * Set up access to all active DRAM banks
1639 for (i = 0; i < MV_WIN_DDR_MAX; i++)
1640 if (ddr_is_active(i)) {
1641 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
1642 sz = ((ddr_size(i) - 1) & 0xffff0000);
1644 /* Place DDR entries in non-remapped windows */
1645 for (j = 0; j < MV_WIN_IDMA_MAX; j++)
1646 if (win_idma_can_remap(j) != 1 &&
1647 idma_bare_read(base, j) == 1) {
1649 /* Configure window */
1650 win_idma_br_write(base, j, br);
1651 win_idma_sz_write(base, j, sz);
1653 /* Set protection RW on all channels */
1654 idma_set_prot(base, j, 0x3);
1657 idma_bare_write(base, j, 0);
1663 * Remaining targets -- from statically defined table
1665 for (i = 0; i < idma_wins_no; i++)
1666 if (idma_wins[i].target > 0) {
1667 br = (idma_wins[i].base & 0xffff0000) |
1668 (idma_wins[i].attr << 8) | idma_wins[i].target;
1669 sz = ((idma_wins[i].size - 1) & 0xffff0000);
1671 /* Set the first free IDMA window */
1672 for (j = 0; j < MV_WIN_IDMA_MAX; j++) {
1673 if (idma_bare_read(base, j) == 0)
1676 /* Configure window */
1677 win_idma_br_write(base, j, br);
1678 win_idma_sz_write(base, j, sz);
1679 if (win_idma_can_remap(j) &&
1680 idma_wins[j].remap >= 0)
1681 win_idma_har_write(base, j,
1682 idma_wins[j].remap);
1684 /* Set protection RW on all channels */
1685 idma_set_prot(base, j, 0x3);
1688 idma_bare_write(base, j, 0);
1695 decode_win_idma_valid(void)
1697 const struct decode_win *wintab;
1701 if (idma_wins_no > MV_WIN_IDMA_MAX) {
1702 printf("IDMA windows: too many entries: %d\n", idma_wins_no);
1705 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
1706 if (ddr_is_active(i))
1709 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) {
1710 printf("IDMA windows: too many entries: %d, available: %d\n",
1711 idma_wins_no, MV_WIN_IDMA_MAX - c);
1717 for (i = 0; i < idma_wins_no; i++, wintab++) {
1719 if (wintab->target == 0) {
1720 printf("IDMA window#%d: DDR target window is not "
1721 "supposed to be reprogrammed!\n", i);
1725 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
1726 printf("IDMA window#%d: not capable of remapping, but "
1727 "val 0x%08x defined\n", i, wintab->remap);
1734 if (s > (0xFFFFFFFF - b + 1)) {
1735 /* XXX this boundary check should account for 64bit and
1737 printf("IDMA window#%d: no space for size 0x%08x at "
1738 "0x%08x\n", i, s, b);
1743 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]);
1745 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps "
1746 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
1748 idma_wins[j].base + idma_wins[j].size - 1);
1757 decode_win_idma_dump(u_long base)
1761 if (pm_is_disabled(CPU_PM_CTRL_IDMA))
1764 for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
1765 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i,
1766 win_idma_br_read(base, i), win_idma_sz_read(base, i));
1768 if (win_idma_can_remap(i))
1769 printf(", ha 0x%08x", win_idma_har_read(base, i));
1773 for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
1774 printf("IDMA channel#%d: ap 0x%08x\n", i,
1775 win_idma_cap_read(base, i));
1776 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base));
1780 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */
1782 decode_win_idma_valid(void)
1789 decode_win_idma_setup(u_long base)
1794 decode_win_idma_dump(u_long base)
1799 /**************************************************************************
1800 * XOR windows routines
1801 **************************************************************************/
1802 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
1804 xor_ctrl_read(u_long base, int i, int c, int e)
1807 v = win_xor_ctrl_read(base, c, e);
1814 xor_ctrl_write(u_long base, int i, int c, int e, int val)
1818 v = win_xor_ctrl_read(base, c, e);
1821 win_xor_ctrl_write(base, c, e, v);
1825 * Set channel protection 'val' for window 'w' on channel 'c'
1828 xor_chan_write(u_long base, int c, int e, int w, int val)
1832 v = win_xor_ctrl_read(base, c, e);
1833 v &= ~(0x3 << (w * 2 + 16));
1834 v |= (val << (w * 2 + 16));
1835 win_xor_ctrl_write(base, c, e, v);
1839 * Set protection 'val' on all channels for window 'w' on engine 'e'
1842 xor_set_prot(u_long base, int w, int e, int val)
1846 for (c = 0; c < MV_XOR_CHAN_MAX; c++)
1847 xor_chan_write(base, c, e, w, val);
1851 win_xor_can_remap(int i)
1854 /* XOR decode windows 0-3 have remap capability */
1868 case MV_DEV_88F6281:
1869 case MV_DEV_88F6282:
1870 case MV_DEV_MV78130:
1871 case MV_DEV_MV78160:
1872 case MV_DEV_MV78230:
1873 case MV_DEV_MV78260:
1874 case MV_DEV_MV78460:
1876 case MV_DEV_MV78100:
1877 case MV_DEV_MV78100_Z0:
1885 xor_active_dram(u_long base, int c, int e, int *window)
1891 * Set up access to all active DRAM banks
1894 for (i = 0; i < m; i++)
1895 if (ddr_is_active(i)) {
1896 br = ddr_base(i) | (ddr_attr(i) << 8) |
1898 sz = ((ddr_size(i) - 1) & 0xffff0000);
1900 /* Place DDR entries in non-remapped windows */
1901 for (w = 0; w < MV_WIN_XOR_MAX; w++)
1902 if (win_xor_can_remap(w) != 1 &&
1903 (xor_ctrl_read(base, w, c, e) == 0) &&
1905 /* Configure window */
1906 win_xor_br_write(base, w, e, br);
1907 win_xor_sz_write(base, w, e, sz);
1909 /* Set protection RW on all channels */
1910 xor_set_prot(base, w, e, 0x3);
1913 xor_ctrl_write(base, w, c, e, 1);
1921 decode_win_xor_setup(u_long base)
1924 int i, j, z, e = 1, m, window;
1926 if (pm_is_disabled(CPU_PM_CTRL_XOR))
1930 * Disable and clear all XOR windows, revoke protection for all
1934 for (j = 0; j < m; j++, e--) {
1936 /* Number of non-remaped windows */
1937 window = MV_XOR_NON_REMAP - 1;
1939 for (i = 0; i < MV_WIN_XOR_MAX; i++) {
1940 win_xor_br_write(base, i, e, 0);
1941 win_xor_sz_write(base, i, e, 0);
1944 if (win_xor_can_remap(i) == 1)
1945 win_xor_har_write(base, i, e, 0);
1947 for (i = 0; i < MV_XOR_CHAN_MAX; i++) {
1948 win_xor_ctrl_write(base, i, e, 0);
1949 xor_active_dram(base, i, e, &window);
1953 * Remaining targets -- from a statically defined table
1955 for (i = 0; i < xor_wins_no; i++)
1956 if (xor_wins[i].target > 0) {
1957 br = (xor_wins[i].base & 0xffff0000) |
1958 (xor_wins[i].attr << 8) |
1960 sz = ((xor_wins[i].size - 1) & 0xffff0000);
1962 /* Set the first free XOR window */
1963 for (z = 0; z < MV_WIN_XOR_MAX; z++) {
1964 if (xor_ctrl_read(base, z, 0, e) &&
1965 xor_ctrl_read(base, z, 1, e))
1968 /* Configure window */
1969 win_xor_br_write(base, z, e, br);
1970 win_xor_sz_write(base, z, e, sz);
1971 if (win_xor_can_remap(z) &&
1972 xor_wins[z].remap >= 0)
1973 win_xor_har_write(base, z, e,
1976 /* Set protection RW on all channels */
1977 xor_set_prot(base, z, e, 0x3);
1980 xor_ctrl_write(base, z, 0, e, 1);
1981 xor_ctrl_write(base, z, 1, e, 1);
1989 decode_win_xor_valid(void)
1991 const struct decode_win *wintab;
1995 if (xor_wins_no > MV_WIN_XOR_MAX) {
1996 printf("XOR windows: too many entries: %d\n", xor_wins_no);
1999 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
2000 if (ddr_is_active(i))
2003 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) {
2004 printf("XOR windows: too many entries: %d, available: %d\n",
2005 xor_wins_no, MV_WIN_IDMA_MAX - c);
2011 for (i = 0; i < xor_wins_no; i++, wintab++) {
2013 if (wintab->target == 0) {
2014 printf("XOR window#%d: DDR target window is not "
2015 "supposed to be reprogrammed!\n", i);
2019 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
2020 printf("XOR window#%d: not capable of remapping, but "
2021 "val 0x%08x defined\n", i, wintab->remap);
2028 if (s > (0xFFFFFFFF - b + 1)) {
2030 * XXX this boundary check should account for 64bit
2033 printf("XOR window#%d: no space for size 0x%08x at "
2034 "0x%08x\n", i, s, b);
2039 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]);
2041 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps "
2042 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
2044 xor_wins[j].base + xor_wins[j].size - 1);
2053 decode_win_xor_dump(u_long base)
2058 if (pm_is_disabled(CPU_PM_CTRL_XOR))
2061 for (j = 0; j < xor_max_eng(); j++, e--) {
2062 for (i = 0; i < MV_WIN_XOR_MAX; i++) {
2063 printf("XOR window#%d: b 0x%08x, s 0x%08x", i,
2064 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e));
2066 if (win_xor_can_remap(i))
2067 printf(", ha 0x%08x", win_xor_har_read(base, i, e));
2071 for (i = 0; i < MV_XOR_CHAN_MAX; i++)
2072 printf("XOR control#%d: 0x%08x\n", i,
2073 win_xor_ctrl_read(base, i, e));
2078 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */
2080 decode_win_xor_valid(void)
2087 decode_win_xor_setup(u_long base)
2092 decode_win_xor_dump(u_long base)
2097 /**************************************************************************
2098 * SATA windows routines
2099 **************************************************************************/
2101 decode_win_sata_setup(u_long base)
2106 if (pm_is_disabled(CPU_PM_CTRL_SATA))
2109 for (i = 0; i < MV_WIN_SATA_MAX; i++) {
2110 win_sata_cr_write(base, i, 0);
2111 win_sata_br_write(base, i, 0);
2114 for (i = 0; i < MV_WIN_DDR_MAX; i++)
2115 if (ddr_is_active(i)) {
2116 cr = ((ddr_size(i) - 1) & 0xffff0000) |
2117 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
2120 /* Use the first available SATA window */
2121 for (j = 0; j < MV_WIN_SATA_MAX; j++) {
2122 if ((win_sata_cr_read(base, j) & 1) != 0)
2125 win_sata_br_write(base, j, br);
2126 win_sata_cr_write(base, j, cr);
2132 #ifdef SOC_MV_ARMADA38X
2134 * Configure AHCI decoding windows
2137 decode_win_ahci_setup(u_long base)
2139 uint32_t br, cr, sz;
2142 for (i = 0; i < MV_WIN_SATA_MAX; i++) {
2143 win_sata_cr_write(base, i, 0);
2144 win_sata_br_write(base, i, 0);
2145 win_sata_sz_write(base, i, 0);
2148 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
2149 if (ddr_is_active(i)) {
2150 cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
2151 (ddr_target(i) << IO_WIN_TGT_SHIFT) |
2154 sz = (ddr_size(i) - 1) &
2155 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT);
2157 /* Use first available SATA window */
2158 for (j = 0; j < MV_WIN_SATA_MAX; j++) {
2159 if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK)
2162 /* BASE is set to DRAM base (0x00000000) */
2163 win_sata_br_write(base, j, br);
2164 /* CTRL targets DRAM ctrl with 0x0E or 0x0D */
2165 win_sata_cr_write(base, j, cr);
2166 /* SIZE is set to 16MB - max value */
2167 win_sata_sz_write(base, j, sz);
2175 decode_win_ahci_dump(u_long base)
2179 for (i = 0; i < MV_WIN_SATA_MAX; i++)
2180 printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i,
2181 win_sata_cr_read(base, i), win_sata_br_read(base, i),
2182 win_sata_sz_read(base,i));
2187 * Provide dummy functions to satisfy the build
2188 * for SoC's not equipped with AHCI controller
2191 decode_win_ahci_setup(u_long base)
2196 decode_win_ahci_dump(u_long base)
2202 decode_win_sata_valid(void)
2207 if (dev == MV_DEV_88F5281)
2210 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX));
2214 decode_win_sdhci_setup(u_long base)
2219 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) {
2220 win_sdhci_cr_write(base, i, 0);
2221 win_sdhci_br_write(base, i, 0);
2224 for (i = 0; i < MV_WIN_DDR_MAX; i++)
2225 if (ddr_is_active(i)) {
2227 cr = (((ddr_size(i) - 1) &
2228 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) |
2229 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
2230 (ddr_target(i) << IO_WIN_TGT_SHIFT) |
2233 /* Use the first available SDHCI window */
2234 for (j = 0; j < MV_WIN_SDHCI_MAX; j++) {
2235 if (win_sdhci_cr_read(base, j) & IO_WIN_ENA_MASK)
2238 win_sdhci_cr_write(base, j, cr);
2239 win_sdhci_br_write(base, j, br);
2246 decode_win_sdhci_dump(u_long base)
2250 for (i = 0; i < MV_WIN_SDHCI_MAX; i++)
2251 printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i,
2252 win_sdhci_cr_read(base, i), win_sdhci_br_read(base, i));
2256 decode_win_sdhci_valid(void)
2259 #ifdef SOC_MV_ARMADA38X
2260 return (decode_win_can_cover_ddr(MV_WIN_SDHCI_MAX));
2263 /* Satisfy platforms not equipped with this controller. */
2267 /**************************************************************************
2268 * FDT parsing routines.
2269 **************************************************************************/
2272 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples,
2276 pcell_t addr_cells, par_addr_cells, size_cells;
2277 int len, tuple_size, tuples_count;
2279 node = OF_finddevice(nodename);
2283 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
2286 par_addr_cells = fdt_parent_addr_cells(node);
2287 if (par_addr_cells > 2)
2290 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
2293 /* Note the OF_getprop_alloc() cannot be used at this early stage. */
2294 len = OF_getprop(node, "ranges", buf, size);
2297 * XXX this does not handle the empty 'ranges;' case, which is
2298 * legitimate and should be allowed.
2300 tuples_count = len / tuple_size;
2301 if (tuples_count <= 0)
2304 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2)
2307 *tuples = tuples_count;
2308 *tuplesize = tuple_size;
2313 win_cpu_from_dt(void)
2317 int i, entry_size, err, t, tuple_size, tuples;
2318 u_long sram_base, sram_size;
2321 /* Retrieve 'ranges' property of '/localbus' node. */
2322 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges),
2323 &tuples, &tuple_size)) == 0) {
2325 * Fill CPU decode windows table.
2327 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl));
2329 entry_size = tuple_size / sizeof(pcell_t);
2330 cpu_wins_no = tuples;
2333 if (tuples > nitems(cpu_win_tbl)) {
2334 debugf("too many tuples to fit into cpu_win_tbl\n");
2338 for (i = 0, t = 0; t < tuples; i += entry_size, t++) {
2339 cpu_win_tbl[t].target = 1;
2340 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]);
2341 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]);
2342 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]);
2343 cpu_win_tbl[t].remap = ~0;
2344 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x "
2345 "size = 0x%0x remap = 0x%0x\n",
2346 cpu_win_tbl[t].target,
2347 cpu_win_tbl[t].attr, cpu_win_tbl[t].base,
2348 cpu_win_tbl[t].size, cpu_win_tbl[t].remap);
2353 * Retrieve CESA SRAM data.
2355 if ((node = OF_finddevice("sram")) != -1)
2356 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram"))
2359 if ((node = OF_finddevice("/")) == 0)
2362 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0)
2363 /* SRAM block is not always present. */
2366 sram_base = sram_size = 0;
2367 if (fdt_regsize(node, &sram_base, &sram_size) != 0)
2371 if (t >= nitems(cpu_win_tbl)) {
2372 debugf("cannot fit CESA tuple into cpu_win_tbl\n");
2376 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
2377 #ifdef SOC_MV_ARMADA38X
2378 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0);
2380 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
2382 cpu_win_tbl[t].base = sram_base;
2383 cpu_win_tbl[t].size = sram_size;
2384 cpu_win_tbl[t].remap = ~0;
2386 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);
2388 /* Check if there is a second CESA node */
2389 while ((node = OF_peer(node)) != 0) {
2390 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) {
2391 if (fdt_regsize(node, &sram_base, &sram_size) != 0)
2401 if (t >= nitems(cpu_win_tbl)) {
2402 debugf("cannot fit CESA tuple into cpu_win_tbl\n");
2406 /* Configure window for CESA1 */
2407 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
2408 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
2409 cpu_win_tbl[t].base = sram_base;
2410 cpu_win_tbl[t].size = sram_size;
2411 cpu_win_tbl[t].remap = ~0;
2413 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);
2419 fdt_win_process(phandle_t child)
2422 struct soc_node_spec *soc_node;
2423 int addr_cells, size_cells;
2427 for (i = 0; soc_nodes[i].compat != NULL; i++) {
2429 soc_node = &soc_nodes[i];
2431 /* Setup only for enabled devices */
2432 if (ofw_bus_node_status_okay(child) == 0)
2435 if (!ofw_bus_node_is_compatible(child, soc_node->compat))
2438 if (fdt_addrsize_cells(OF_parent(child), &addr_cells,
2442 if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg))
2445 if (OF_getprop(child, "reg", ®, sizeof(reg)) <= 0)
2448 if (addr_cells <= 2)
2449 base = fdt_data_get(®[0], addr_cells);
2451 base = fdt_data_get(®[addr_cells - 2], 2);
2452 size = fdt_data_get(®[addr_cells], size_cells);
2454 base = (base & 0x000fffff) | fdt_immr_va;
2455 if (soc_node->decode_handler != NULL)
2456 soc_node->decode_handler(base);
2460 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL))
2461 soc_node->dump_handler(base);
2469 phandle_t node, child, sb;
2470 phandle_t child_pci;
2474 node = OF_finddevice("/");
2476 panic("fdt_win_setup: no root node");
2479 * Traverse through all children of root and simple-bus nodes.
2480 * For each found device retrieve decode windows data (if applicable).
2482 child = OF_child(node);
2483 while (child != 0) {
2484 /* Lookup for callback and run */
2485 err = fdt_win_process(child);
2489 /* Process Marvell Armada-XP/38x PCIe controllers */
2490 if (ofw_bus_node_is_compatible(child, "marvell,armada-370-pcie")) {
2491 child_pci = OF_child(child);
2492 while (child_pci != 0) {
2493 err = fdt_win_process(child_pci);
2497 child_pci = OF_peer(child_pci);
2502 * Once done with root-level children let's move down to
2503 * simple-bus and its children.
2505 child = OF_peer(child);
2506 if ((child == 0) && (node == OF_finddevice("/"))) {
2507 sb = node = fdt_find_compatible(node, "simple-bus", 0);
2510 child = OF_child(node);
2513 * Next, move one more level down to internal-regs node (if
2514 * it is present) and its children. This node also have
2515 * "simple-bus" compatible.
2517 if ((child == 0) && (node == sb)) {
2518 node = fdt_find_compatible(node, "simple-bus", 0);
2521 child = OF_child(node);
2529 fdt_fixup_busfreq(phandle_t root)
2534 freq = cpu_to_fdt32(get_tclk());
2537 * Fix bus speed in cpu node
2539 if ((sb = OF_finddevice("cpu")) != 0)
2540 if (fdt_is_compatible_strict(sb, "ARM,88VS584"))
2541 OF_setprop(sb, "bus-frequency", (void *)&freq,
2545 * This fixup sets the simple-bus bus-frequency property.
2547 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0)
2548 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq));
2552 fdt_fixup_ranges(phandle_t root)
2555 pcell_t par_addr_cells, addr_cells, size_cells;
2556 pcell_t ranges[3], reg[2], *rangesptr;
2557 int len, tuple_size, tuples_count;
2560 /* Fix-up SoC ranges according to real fdt_immr_pa */
2561 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) {
2562 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 &&
2563 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) {
2564 tuple_size = sizeof(pcell_t) * (par_addr_cells +
2565 addr_cells + size_cells);
2566 len = OF_getprop(node, "ranges", ranges,
2568 tuples_count = len / tuple_size;
2569 /* Unexpected settings are not supported */
2570 if (tuples_count != 1)
2573 rangesptr = &ranges[0];
2574 rangesptr += par_addr_cells;
2575 base = fdt_data_get((void *)rangesptr, addr_cells);
2576 *rangesptr = cpu_to_fdt32(fdt_immr_pa);
2577 if (OF_setprop(node, "ranges", (void *)&ranges[0],
2578 sizeof(ranges)) < 0)
2583 /* Fix-up PCIe reg according to real PCIe registers' PA */
2584 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) {
2585 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
2586 &size_cells) == 0) {
2587 tuple_size = sizeof(pcell_t) * (par_addr_cells +
2589 len = OF_getprop(node, "reg", reg, sizeof(reg));
2590 tuples_count = len / tuple_size;
2591 /* Unexpected settings are not supported */
2592 if (tuples_count != 1)
2595 base = fdt_data_get((void *)®[0], par_addr_cells);
2596 base &= ~0xFF000000;
2597 base |= fdt_immr_pa;
2598 reg[0] = cpu_to_fdt32(base);
2599 if (OF_setprop(node, "reg", (void *)®[0],
2604 /* Fix-up succeeded. May return and continue */
2610 * In case of any error while fixing ranges just hang.
2611 * 1. No message can be displayed yet since console
2612 * is not initialized.
2613 * 2. Going further will cause failure on bus_space_map()
2614 * relying on the wrong ranges or data abort when
2615 * accessing PCIe registers.
2620 struct fdt_fixup_entry fdt_fixup_table[] = {
2621 { "mrvl,DB-88F6281", &fdt_fixup_busfreq },
2622 { "mrvl,DB-78460", &fdt_fixup_busfreq },
2623 { "mrvl,DB-78460", &fdt_fixup_ranges },
2629 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
2633 if (!ofw_bus_node_is_compatible(node, "mrvl,pic") &&
2634 !ofw_bus_node_is_compatible(node, "mrvl,mpic"))
2637 *interrupt = fdt32_to_cpu(intr[0]);
2638 *trig = INTR_TRIGGER_CONFORM;
2639 *pol = INTR_POLARITY_CONFORM;
2644 fdt_pic_decode_t fdt_pic_table[] = {
2645 #ifdef SOC_MV_ARMADA38X
2656 uint32_t sar_low, sar_high;
2658 #if defined(SOC_MV_ARMADAXP)
2659 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
2660 SAMPLE_AT_RESET_HI);
2661 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
2662 SAMPLE_AT_RESET_LO);
2663 #elif defined(SOC_MV_ARMADA38X)
2665 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
2669 * TODO: Add getting proper values for other SoC configurations
2675 return (((uint64_t)sar_high << 32) | sar_low);