2 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD.
5 * Developed by Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
41 #include <sys/reboot.h>
43 #include <dev/fdt/fdt_common.h>
44 #include <dev/ofw/openfirm.h>
45 #include <dev/ofw/ofw_bus_subr.h>
47 #include <machine/bus.h>
48 #include <machine/fdt.h>
49 #include <machine/vmparam.h>
50 #include <machine/intr.h>
52 #include <arm/mv/mvreg.h>
53 #include <arm/mv/mvvar.h>
54 #include <arm/mv/mvwin.h>
57 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory");
65 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \
66 printf(fmt,##args); } while (0)
68 #define debugf(fmt, args...)
77 static int win_eth_can_remap(int i);
80 static int decode_win_cpu_valid(void);
82 static int decode_win_usb_valid(void);
83 static int decode_win_usb3_valid(void);
84 static int decode_win_eth_valid(void);
85 static int decode_win_pcie_valid(void);
86 static int decode_win_sata_valid(void);
88 static int decode_win_idma_valid(void);
89 static int decode_win_xor_valid(void);
92 static void decode_win_cpu_setup(void);
94 #ifdef SOC_MV_ARMADAXP
95 static int decode_win_sdram_fixup(void);
97 static void decode_win_usb_setup(u_long);
98 static void decode_win_usb3_setup(u_long);
99 static void decode_win_eth_setup(u_long);
100 static void decode_win_sata_setup(u_long);
102 static void decode_win_idma_setup(u_long);
103 static void decode_win_xor_setup(u_long);
105 static void decode_win_usb_dump(u_long);
106 static void decode_win_usb3_dump(u_long);
107 static void decode_win_eth_dump(u_long base);
108 static void decode_win_idma_dump(u_long base);
109 static void decode_win_xor_dump(u_long base);
111 static int fdt_get_ranges(const char *, void *, int, int *, int *);
112 #ifdef SOC_MV_ARMADA38X
113 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
114 int *trig, int *pol);
117 static int win_cpu_from_dt(void);
118 static int fdt_win_setup(void);
120 static uint32_t dev_mask = 0;
121 static int cpu_wins_no = 0;
122 static int eth_port = 0;
123 static int usb_port = 0;
125 static struct decode_win cpu_win_tbl[MAX_CPU_WIN];
127 const struct decode_win *cpu_wins = cpu_win_tbl;
129 typedef void (*decode_win_setup_t)(u_long);
130 typedef void (*dump_win_t)(u_long);
132 struct soc_node_spec {
134 decode_win_setup_t decode_handler;
135 dump_win_t dump_handler;
138 static struct soc_node_spec soc_nodes[] = {
139 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump },
140 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
141 { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump },
142 { "mrvl,sata", &decode_win_sata_setup, NULL },
143 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump },
144 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump },
145 { "mrvl,pcie", &decode_win_pcie_setup, NULL },
146 { NULL, NULL, NULL },
149 struct fdt_pm_mask_entry fdt_pm_mask_table[] = {
150 { "mrvl,ge", CPU_PM_CTRL_GE(0) },
151 { "mrvl,ge", CPU_PM_CTRL_GE(1) },
152 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) },
153 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) },
154 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) },
155 { "mrvl,xor", CPU_PM_CTRL_XOR },
156 { "mrvl,sata", CPU_PM_CTRL_SATA },
162 pm_is_disabled(uint32_t mask)
164 #if defined(SOC_MV_KIRKWOOD)
165 return (soc_power_ctrl_get(mask) == mask);
167 return (soc_power_ctrl_get(mask) == mask ? 0 : 1);
172 * Disable device using power management register.
173 * 1 - Device Power On
174 * 0 - Device Power Off
175 * Mask can be set in loader.
177 * loader> set hw.pm-disable-mask=0x2
180 * |-------------------------------|
181 * | Device | Kirkwood | Discovery |
182 * |-------------------------------|
183 * | USB0 | 0x00008 | 0x020000 |
184 * |-------------------------------|
185 * | USB1 | - | 0x040000 |
186 * |-------------------------------|
187 * | USB2 | - | 0x080000 |
188 * |-------------------------------|
189 * | GE0 | 0x00001 | 0x000002 |
190 * |-------------------------------|
191 * | GE1 | - | 0x000004 |
192 * |-------------------------------|
193 * | IDMA | - | 0x100000 |
194 * |-------------------------------|
195 * | XOR | 0x10000 | 0x200000 |
196 * |-------------------------------|
197 * | CESA | 0x20000 | 0x400000 |
198 * |-------------------------------|
199 * | SATA | 0x04000 | 0x004000 |
200 * --------------------------------|
201 * This feature can be used only on Kirkwood and Discovery
205 pm_disable_device(int mask)
210 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
211 printf("Power Management Register: 0%x\n", reg);
214 soc_power_ctrl_set(reg);
215 printf("Device %x is disabled\n", mask);
217 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
218 printf("Power Management Register: 0%x\n", reg);
223 fdt_pm(phandle_t node)
225 uint32_t cpu_pm_ctrl;
229 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL);
230 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) {
231 if (dev_mask & (1 << i))
234 compat = ofw_bus_node_is_compatible(node,
235 fdt_pm_mask_table[i].compat);
236 #if defined(SOC_MV_KIRKWOOD)
237 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) {
238 dev_mask |= (1 << i);
242 dev_mask |= (1 << i);
246 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) {
247 dev_mask |= (1 << i);
251 dev_mask |= (1 << i);
261 read_cpu_ctrl(uint32_t reg)
264 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg));
268 write_cpu_ctrl(uint32_t reg, uint32_t val)
271 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val);
274 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
276 read_cpu_mp_clocks(uint32_t reg)
279 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg));
283 write_cpu_mp_clocks(uint32_t reg, uint32_t val)
286 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val);
290 read_cpu_misc(uint32_t reg)
293 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg));
297 write_cpu_misc(uint32_t reg, uint32_t val)
300 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val);
308 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X)
309 write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
310 write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
312 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
313 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
329 case MV_DEV_88RC8180:
330 case MV_DEV_MV78100_Z0:
332 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
336 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
340 printf("This ARM Core does not support any extra features\n");
347 * Get the power status of device. This feature is only supported on
348 * Kirkwood and Discovery SoCs.
351 soc_power_ctrl_get(uint32_t mask)
354 #if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS) && !defined(SOC_MV_FREY)
355 if (mask != CPU_PM_CTRL_NONE)
356 mask &= read_cpu_ctrl(CPU_PM_CTRL);
365 * Set the power status of device. This feature is only supported on
366 * Kirkwood and Discovery SoCs.
369 soc_power_ctrl_set(uint32_t mask)
372 #if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS)
373 if (mask != CPU_PM_CTRL_NONE)
374 write_cpu_ctrl(CPU_PM_CTRL, mask);
379 soc_id(uint32_t *dev, uint32_t *rev)
383 * Notice: system identifiers are available in the registers range of
384 * PCIE controller, so using this function is only allowed (and
385 * possible) after the internal registers range has been mapped in via
386 * devmap_bootstrap().
388 *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16;
389 *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff;
395 uint32_t d, r, size, mode;
403 printf("(0x%4x:0x%02x) ", d, r);
408 dev = "Marvell 88F5181";
413 dev = "Marvell 88F5182";
418 dev = "Marvell 88F5281";
427 dev = "Marvell 88F6281";
435 case MV_DEV_88RC8180:
436 dev = "Marvell 88RC8180";
438 case MV_DEV_88RC9480:
439 dev = "Marvell 88RC9480";
441 case MV_DEV_88RC9580:
442 dev = "Marvell 88RC9580";
445 dev = "Marvell 88F6781";
450 dev = "Marvell 88F6282";
457 dev = "Marvell 88F6828";
460 dev = "Marvell 88F6820";
463 dev = "Marvell 88F6810";
465 case MV_DEV_MV78100_Z0:
466 dev = "Marvell MV78100 Z0";
469 dev = "Marvell MV78100";
472 dev = "Marvell MV78160";
475 dev = "Marvell MV78260";
478 dev = "Marvell MV78460";
487 printf(" rev %s", rev);
488 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
490 mode = read_cpu_ctrl(CPU_CONFIG);
491 printf(" Instruction cache prefetch %s, data cache prefetch %s\n",
492 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled",
493 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled");
498 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE;
499 printf(" 256KB 4-way set-associative %s unified L2 cache\n",
500 mode ? "write-through" : "write-back");
503 mode = read_cpu_ctrl(CPU_CONTROL);
504 size = mode & CPU_CONTROL_L2_SIZE;
505 mode = mode & CPU_CONTROL_L2_MODE;
506 printf(" %s set-associative %s unified L2 cache\n",
507 size ? "256KB 4-way" : "512KB 8-way",
508 mode ? "write-through" : "write-back");
516 platform_identify(void *dummy)
522 * XXX Board identification e.g. read out from FPGA or similar should
526 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify,
531 mv_enter_debugger(void *dummy)
534 if (boothowto & RB_KDB)
535 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
537 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL);
547 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask);
550 pm_disable_device(mask);
552 /* Retrieve data about physical addresses from device tree. */
553 if ((err = win_cpu_from_dt()) != 0)
556 /* Retrieve our ID: some windows facilities vary between SoC models */
559 #ifdef SOC_MV_ARMADAXP
560 if ((err = decode_win_sdram_fixup()) != 0)
565 if (!decode_win_cpu_valid() || !decode_win_usb_valid() ||
566 !decode_win_eth_valid() || !decode_win_idma_valid() ||
567 !decode_win_pcie_valid() || !decode_win_sata_valid() ||
568 !decode_win_xor_valid() || !decode_win_usb3_valid())
571 decode_win_cpu_setup();
573 if (!decode_win_usb_valid() ||
574 !decode_win_eth_valid() || !decode_win_idma_valid() ||
575 !decode_win_pcie_valid() || !decode_win_sata_valid() ||
576 !decode_win_xor_valid() || !decode_win_usb3_valid())
580 soc_dump_decode_win();
584 if ((err = fdt_win_setup()) != 0)
590 /**************************************************************************
591 * Decode windows registers accessors
592 **************************************************************************/
593 #if !defined(SOC_MV_FREY)
594 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
595 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
596 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
597 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
598 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
599 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
600 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
601 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
604 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL)
605 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE)
606 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL)
607 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE)
609 #ifdef SOC_MV_ARMADA38X
610 WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL)
611 WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE)
612 WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL)
613 WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE)
616 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
617 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
618 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
619 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)
620 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)
621 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)
623 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE)
624 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE)
625 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP)
626 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL)
627 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE)
628 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE)
629 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP)
630 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL)
632 WIN_REG_BASE_RD(win_eth, bare, 0x290)
633 WIN_REG_BASE_RD(win_eth, epap, 0x294)
634 WIN_REG_BASE_WR(win_eth, bare, 0x290)
635 WIN_REG_BASE_WR(win_eth, epap, 0x294)
637 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL);
638 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE);
639 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP);
640 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL);
641 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE);
642 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP);
643 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE);
644 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE);
645 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H);
646 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL);
648 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE)
649 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE)
650 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP)
651 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP)
652 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE)
653 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE)
654 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP)
655 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP)
656 WIN_REG_BASE_RD(win_idma, bare, 0xa80)
657 WIN_REG_BASE_WR(win_idma, bare, 0xa80)
659 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL);
660 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE);
661 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL);
662 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE);
664 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
665 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
666 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
667 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
670 * On 88F6781 (Dove) SoC DDR Controller is accessed through
671 * single MBUS <-> AXI bridge. In this case we provide emulated
672 * ddr_br_read() and ddr_sz_read() functions to keep compatibility
673 * with common decoding windows setup code.
676 static inline uint32_t ddr_br_read(int i)
680 /* Read Memory Address Map Register for CS i */
681 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0);
683 /* Return CS i base address */
684 return (mmap & 0xFF000000);
687 static inline uint32_t ddr_sz_read(int i)
691 /* Read Memory Address Map Register for CS i */
692 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0);
694 /* Extract size of CS space in 64kB units */
695 size = (1 << ((mmap >> 16) & 0x0F));
697 /* Return CS size and enable/disable status */
698 return (((size - 1) << 16) | (mmap & 0x01));
702 #if !defined(SOC_MV_FREY)
703 /**************************************************************************
704 * Decode windows helper routines
705 **************************************************************************/
707 soc_dump_decode_win(void)
714 for (i = 0; i < MV_WIN_CPU_MAX; i++) {
715 printf("CPU window#%d: c 0x%08x, b 0x%08x", i,
719 if (win_cpu_can_remap(i))
720 printf(", rl 0x%08x, rh 0x%08x",
721 win_cpu_remap_l_read(i),
722 win_cpu_remap_h_read(i));
726 printf("Internal regs base: 0x%08x\n",
727 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0));
729 for (i = 0; i < MV_WIN_DDR_MAX; i++)
730 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i,
731 ddr_br_read(i), ddr_sz_read(i));
734 /**************************************************************************
735 * CPU windows routines
736 **************************************************************************/
738 win_cpu_can_remap(int i)
744 /* Depending on the SoC certain windows have remap capability */
745 if ((dev == MV_DEV_88F5182 && i < 2) ||
746 (dev == MV_DEV_88F5281 && i < 4) ||
747 (dev == MV_DEV_88F6281 && i < 4) ||
748 (dev == MV_DEV_88F6282 && i < 4) ||
749 (dev == MV_DEV_88F6828 && i < 20) ||
750 (dev == MV_DEV_88F6820 && i < 20) ||
751 (dev == MV_DEV_88F6810 && i < 20) ||
752 (dev == MV_DEV_88RC8180 && i < 2) ||
753 (dev == MV_DEV_88F6781 && i < 4) ||
754 (dev == MV_DEV_MV78100_Z0 && i < 8) ||
755 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8))
761 /* XXX This should check for overlapping remap fields too.. */
763 decode_win_overlap(int win, int win_no, const struct decode_win *wintab)
765 const struct decode_win *tab;
770 for (i = 0; i < win_no; i++, tab++) {
775 if ((tab->base + tab->size - 1) < (wintab + win)->base)
778 else if (((wintab + win)->base + (wintab + win)->size - 1) <
789 decode_win_cpu_valid(void)
794 if (cpu_wins_no > MV_WIN_CPU_MAX) {
795 printf("CPU windows: too many entries: %d\n", cpu_wins_no);
800 for (i = 0; i < cpu_wins_no; i++) {
802 if (cpu_wins[i].target == 0) {
803 printf("CPU window#%d: DDR target window is not "
804 "supposed to be reprogrammed!\n", i);
808 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) {
809 printf("CPU window#%d: not capable of remapping, but "
810 "val 0x%08x defined\n", i, cpu_wins[i].remap);
814 s = cpu_wins[i].size;
815 b = cpu_wins[i].base;
817 if (s > (0xFFFFFFFF - b + 1)) {
819 * XXX this boundary check should account for 64bit
822 printf("CPU window#%d: no space for size 0x%08x at "
823 "0x%08x\n", i, s, b);
828 if (b != rounddown2(b, s)) {
829 printf("CPU window#%d: address 0x%08x is not aligned "
830 "to 0x%08x\n", i, b, s);
835 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]);
837 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps "
838 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
840 cpu_wins[j].base + cpu_wins[j].size - 1);
849 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
856 win = MV_WIN_CPU_MAX - 1;
863 while ((win >= 0) && (win < MV_WIN_CPU_MAX)) {
864 cr = win_cpu_cr_read(win);
865 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0)
867 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) |
868 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) ==
869 ((attr << MV_WIN_CPU_ATTR_SHIFT) |
870 (target << MV_WIN_CPU_TARGET_SHIFT)))
874 if ((win < 0) || (win >= MV_WIN_CPU_MAX) ||
875 ((remap != ~0) && (win_cpu_can_remap(win) == 0)))
878 br = base & 0xffff0000;
879 win_cpu_br_write(win, br);
881 if (win_cpu_can_remap(win)) {
883 win_cpu_remap_l_write(win, remap & 0xffff0000);
884 win_cpu_remap_h_write(win, 0);
887 * Remap function is not used for a given window
888 * (capable of remapping) - set remap field with the
889 * same value as base.
891 win_cpu_remap_l_write(win, base & 0xffff0000);
892 win_cpu_remap_h_write(win, 0);
896 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) |
897 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT;
898 win_cpu_cr_write(win, cr);
904 decode_win_cpu_setup(void)
908 /* Disable all CPU windows */
909 for (i = 0; i < MV_WIN_CPU_MAX; i++) {
910 win_cpu_cr_write(i, 0);
911 win_cpu_br_write(i, 0);
912 if (win_cpu_can_remap(i)) {
913 win_cpu_remap_l_write(i, 0);
914 win_cpu_remap_h_write(i, 0);
918 for (i = 0; i < cpu_wins_no; i++)
919 if (cpu_wins[i].target > 0)
920 decode_win_cpu_set(cpu_wins[i].target,
921 cpu_wins[i].attr, cpu_wins[i].base,
922 cpu_wins[i].size, cpu_wins[i].remap);
927 #ifdef SOC_MV_ARMADAXP
929 decode_win_sdram_fixup(void)
931 struct mem_region mr[FDT_MEM_REGIONS];
932 uint8_t window_valid[MV_WIN_DDR_MAX];
933 int mr_cnt, err, i, j;
934 uint32_t valid_win_num = 0;
936 /* Grab physical memory regions information from device tree. */
937 err = fdt_get_mem_regions(mr, &mr_cnt, NULL);
941 for (i = 0; i < MV_WIN_DDR_MAX; i++)
944 /* Try to match entries from device tree with settings from u-boot */
945 for (i = 0; i < mr_cnt; i++) {
946 for (j = 0; j < MV_WIN_DDR_MAX; j++) {
947 if (ddr_is_active(j) &&
948 (ddr_base(j) == mr[i].mr_start) &&
949 (ddr_size(j) == mr[i].mr_size)) {
956 if (mr_cnt != valid_win_num)
959 /* Destroy windows without corresponding device tree entry */
960 for (j = 0; j < MV_WIN_DDR_MAX; j++) {
961 if (ddr_is_active(j) && (window_valid[j] != 1)) {
962 printf("Disabling SDRAM decoding window: %d\n", j);
971 * Check if we're able to cover all active DDR banks.
974 decode_win_can_cover_ddr(int max)
979 for (i = 0; i < MV_WIN_DDR_MAX; i++)
980 if (ddr_is_active(i))
984 printf("Unable to cover all active DDR banks: "
985 "%d, available windows: %d\n", c, max);
992 /**************************************************************************
993 * DDR windows routines
994 **************************************************************************/
999 if (ddr_sz_read(i) & 0x1)
1017 return (ddr_br_read(i) & 0xff000000);
1024 return ((ddr_sz_read(i) | 0x00ffffff) + 1);
1033 if (dev == MV_DEV_88RC8180)
1034 return ((ddr_sz_read(i) & 0xf0) >> 4);
1035 if (dev == MV_DEV_88F6781)
1038 return (i == 0 ? 0xe :
1041 (i == 3 ? 0x7 : 0xff))));
1050 if (dev == MV_DEV_88RC8180) {
1051 i = (ddr_sz_read(i) & 0xf0) >> 4;
1052 return (i == 0xe ? 0xc :
1055 (i == 0x7 ? 0xf : 0xc))));
1059 * On SOCs other than 88RC8180 Mbus unit ID for
1060 * DDR SDRAM controller is always 0x0.
1065 /**************************************************************************
1066 * USB windows routines
1067 **************************************************************************/
1069 decode_win_usb_valid(void)
1072 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX));
1076 decode_win_usb_dump(u_long base)
1080 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1)))
1083 for (i = 0; i < MV_WIN_USB_MAX; i++)
1084 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i,
1085 win_usb_cr_read(base, i), win_usb_br_read(base, i));
1089 * Set USB decode windows.
1092 decode_win_usb_setup(u_long base)
1098 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port)))
1103 for (i = 0; i < MV_WIN_USB_MAX; i++) {
1104 win_usb_cr_write(base, i, 0);
1105 win_usb_br_write(base, i, 0);
1108 /* Only access to active DRAM banks is required */
1109 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1110 if (ddr_is_active(i)) {
1113 * XXX for 6281 we should handle Mbus write
1114 * burst limit field in the ctrl reg
1116 cr = (((ddr_size(i) - 1) & 0xffff0000) |
1117 (ddr_attr(i) << 8) |
1118 (ddr_target(i) << 4) | 1);
1120 /* Set the first free USB window */
1121 for (j = 0; j < MV_WIN_USB_MAX; j++) {
1122 if (win_usb_cr_read(base, j) & 0x1)
1125 win_usb_br_write(base, j, br);
1126 win_usb_cr_write(base, j, cr);
1133 /**************************************************************************
1134 * USB3 windows routines
1135 **************************************************************************/
1136 #ifdef SOC_MV_ARMADA38X
1138 decode_win_usb3_valid(void)
1141 return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX));
1145 decode_win_usb3_dump(u_long base)
1149 for (i = 0; i < MV_WIN_USB3_MAX; i++)
1150 printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i,
1151 win_usb3_cr_read(base, i), win_usb3_br_read(base, i));
1155 * Set USB3 decode windows
1158 decode_win_usb3_setup(u_long base)
1163 for (i = 0; i < MV_WIN_USB3_MAX; i++) {
1164 win_usb3_cr_write(base, i, 0);
1165 win_usb3_br_write(base, i, 0);
1168 /* Only access to active DRAM banks is required */
1169 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1170 if (ddr_is_active(i)) {
1172 cr = (((ddr_size(i) - 1) &
1173 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) |
1174 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
1175 (ddr_target(i) << IO_WIN_TGT_SHIFT) |
1178 /* Set the first free USB3.0 window */
1179 for (j = 0; j < MV_WIN_USB3_MAX; j++) {
1180 if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK)
1183 win_usb3_br_write(base, j, br);
1184 win_usb3_cr_write(base, j, cr);
1192 * Provide dummy functions to satisfy the build
1193 * for SoCs not equipped with USB3
1196 decode_win_usb3_valid(void)
1203 decode_win_usb3_setup(u_long base)
1208 decode_win_usb3_dump(u_long base)
1212 /**************************************************************************
1213 * ETH windows routines
1214 **************************************************************************/
1217 win_eth_can_remap(int i)
1220 /* ETH encode windows 0-3 have remap capability */
1228 eth_bare_read(uint32_t base, int i)
1232 v = win_eth_bare_read(base);
1239 eth_bare_write(uint32_t base, int i, int val)
1243 v = win_eth_bare_read(base);
1246 win_eth_bare_write(base, v);
1250 eth_epap_write(uint32_t base, int i, int val)
1254 v = win_eth_epap_read(base);
1255 v &= ~(0x3 << (i * 2));
1256 v |= (val << (i * 2));
1257 win_eth_epap_write(base, v);
1261 decode_win_eth_dump(u_long base)
1265 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1)))
1268 for (i = 0; i < MV_WIN_ETH_MAX; i++) {
1269 printf("ETH window#%d: b 0x%08x, s 0x%08x", i,
1270 win_eth_br_read(base, i),
1271 win_eth_sz_read(base, i));
1273 if (win_eth_can_remap(i))
1274 printf(", ha 0x%08x",
1275 win_eth_har_read(base, i));
1279 printf("ETH windows: bare 0x%08x, epap 0x%08x\n",
1280 win_eth_bare_read(base),
1281 win_eth_epap_read(base));
1284 #if defined(SOC_MV_LOKIPLUS)
1285 #define MV_WIN_ETH_DDR_TRGT(n) 0
1287 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n)
1291 decode_win_eth_setup(u_long base)
1296 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port)))
1301 /* Disable, clear and revoke protection for all ETH windows */
1302 for (i = 0; i < MV_WIN_ETH_MAX; i++) {
1304 eth_bare_write(base, i, 1);
1305 eth_epap_write(base, i, 0);
1306 win_eth_br_write(base, i, 0);
1307 win_eth_sz_write(base, i, 0);
1308 if (win_eth_can_remap(i))
1309 win_eth_har_write(base, i, 0);
1312 /* Only access to active DRAM banks is required */
1313 for (i = 0; i < MV_WIN_DDR_MAX; i++)
1314 if (ddr_is_active(i)) {
1316 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i);
1317 sz = ((ddr_size(i) - 1) & 0xffff0000);
1319 /* Set the first free ETH window */
1320 for (j = 0; j < MV_WIN_ETH_MAX; j++) {
1321 if (eth_bare_read(base, j) == 0)
1324 win_eth_br_write(base, j, br);
1325 win_eth_sz_write(base, j, sz);
1327 /* XXX remapping ETH windows not supported */
1329 /* Set protection RW */
1330 eth_epap_write(base, j, 0x3);
1333 eth_bare_write(base, j, 0);
1340 decode_win_eth_valid(void)
1343 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX));
1346 /**************************************************************************
1347 * PCIE windows routines
1348 **************************************************************************/
1351 decode_win_pcie_setup(u_long base)
1353 uint32_t size = 0, ddrbase = ~0;
1357 for (i = 0; i < MV_PCIE_BAR_MAX; i++) {
1358 pcie_bar_br_write(base, i,
1359 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
1361 pcie_bar_brh_write(base, i, 0);
1363 pcie_bar_cr_write(base, i, 0);
1366 for (i = 0; i < MV_WIN_PCIE_MAX; i++) {
1367 win_pcie_cr_write(base, i, 0);
1368 win_pcie_br_write(base, i, 0);
1369 win_pcie_remap_write(base, i, 0);
1372 /* On End-Point only set BAR size to 1MB regardless of DDR size */
1373 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL)
1374 & MV_PCIE_ROOT_CMPLX) == 0) {
1375 pcie_bar_cr_write(base, 1, 0xf0000 | 1);
1379 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1380 if (ddr_is_active(i)) {
1381 /* Map DDR to BAR 1 */
1382 cr = (ddr_size(i) - 1) & 0xffff0000;
1383 size += ddr_size(i) & 0xffff0000;
1384 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
1389 /* Use the first available PCIE window */
1390 for (j = 0; j < MV_WIN_PCIE_MAX; j++) {
1391 if (win_pcie_cr_read(base, j) != 0)
1394 win_pcie_br_write(base, j, br);
1395 win_pcie_cr_write(base, j, cr);
1402 * Upper 16 bits in BAR register is interpreted as BAR size
1403 * (in 64 kB units) plus 64kB, so subtract 0x10000
1404 * form value passed to register to get correct value.
1407 pcie_bar_cr_write(base, 1, size | 1);
1408 pcie_bar_br_write(base, 1, ddrbase |
1409 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
1410 pcie_bar_br_write(base, 0, fdt_immr_pa |
1411 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
1415 decode_win_pcie_valid(void)
1418 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX));
1421 /**************************************************************************
1422 * IDMA windows routines
1423 **************************************************************************/
1424 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY)
1426 idma_bare_read(u_long base, int i)
1430 v = win_idma_bare_read(base);
1437 idma_bare_write(u_long base, int i, int val)
1441 v = win_idma_bare_read(base);
1444 win_idma_bare_write(base, v);
1448 * Sets channel protection 'val' for window 'w' on channel 'c'
1451 idma_cap_write(u_long base, int c, int w, int val)
1455 v = win_idma_cap_read(base, c);
1456 v &= ~(0x3 << (w * 2));
1457 v |= (val << (w * 2));
1458 win_idma_cap_write(base, c, v);
1462 * Set protection 'val' on all channels for window 'w'
1465 idma_set_prot(u_long base, int w, int val)
1469 for (c = 0; c < MV_IDMA_CHAN_MAX; c++)
1470 idma_cap_write(base, c, w, val);
1474 win_idma_can_remap(int i)
1477 /* IDMA decode windows 0-3 have remap capability */
1485 decode_win_idma_setup(u_long base)
1490 if (pm_is_disabled(CPU_PM_CTRL_IDMA))
1493 * Disable and clear all IDMA windows, revoke protection for all channels
1495 for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
1497 idma_bare_write(base, i, 1);
1498 win_idma_br_write(base, i, 0);
1499 win_idma_sz_write(base, i, 0);
1500 if (win_idma_can_remap(i) == 1)
1501 win_idma_har_write(base, i, 0);
1503 for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
1504 win_idma_cap_write(base, i, 0);
1507 * Set up access to all active DRAM banks
1509 for (i = 0; i < MV_WIN_DDR_MAX; i++)
1510 if (ddr_is_active(i)) {
1511 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
1512 sz = ((ddr_size(i) - 1) & 0xffff0000);
1514 /* Place DDR entries in non-remapped windows */
1515 for (j = 0; j < MV_WIN_IDMA_MAX; j++)
1516 if (win_idma_can_remap(j) != 1 &&
1517 idma_bare_read(base, j) == 1) {
1519 /* Configure window */
1520 win_idma_br_write(base, j, br);
1521 win_idma_sz_write(base, j, sz);
1523 /* Set protection RW on all channels */
1524 idma_set_prot(base, j, 0x3);
1527 idma_bare_write(base, j, 0);
1533 * Remaining targets -- from statically defined table
1535 for (i = 0; i < idma_wins_no; i++)
1536 if (idma_wins[i].target > 0) {
1537 br = (idma_wins[i].base & 0xffff0000) |
1538 (idma_wins[i].attr << 8) | idma_wins[i].target;
1539 sz = ((idma_wins[i].size - 1) & 0xffff0000);
1541 /* Set the first free IDMA window */
1542 for (j = 0; j < MV_WIN_IDMA_MAX; j++) {
1543 if (idma_bare_read(base, j) == 0)
1546 /* Configure window */
1547 win_idma_br_write(base, j, br);
1548 win_idma_sz_write(base, j, sz);
1549 if (win_idma_can_remap(j) &&
1550 idma_wins[j].remap >= 0)
1551 win_idma_har_write(base, j,
1552 idma_wins[j].remap);
1554 /* Set protection RW on all channels */
1555 idma_set_prot(base, j, 0x3);
1558 idma_bare_write(base, j, 0);
1565 decode_win_idma_valid(void)
1567 const struct decode_win *wintab;
1571 if (idma_wins_no > MV_WIN_IDMA_MAX) {
1572 printf("IDMA windows: too many entries: %d\n", idma_wins_no);
1575 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
1576 if (ddr_is_active(i))
1579 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) {
1580 printf("IDMA windows: too many entries: %d, available: %d\n",
1581 idma_wins_no, MV_WIN_IDMA_MAX - c);
1587 for (i = 0; i < idma_wins_no; i++, wintab++) {
1589 if (wintab->target == 0) {
1590 printf("IDMA window#%d: DDR target window is not "
1591 "supposed to be reprogrammed!\n", i);
1595 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
1596 printf("IDMA window#%d: not capable of remapping, but "
1597 "val 0x%08x defined\n", i, wintab->remap);
1604 if (s > (0xFFFFFFFF - b + 1)) {
1605 /* XXX this boundary check should account for 64bit and
1607 printf("IDMA window#%d: no space for size 0x%08x at "
1608 "0x%08x\n", i, s, b);
1613 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]);
1615 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps "
1616 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
1618 idma_wins[j].base + idma_wins[j].size - 1);
1627 decode_win_idma_dump(u_long base)
1631 if (pm_is_disabled(CPU_PM_CTRL_IDMA))
1634 for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
1635 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i,
1636 win_idma_br_read(base, i), win_idma_sz_read(base, i));
1638 if (win_idma_can_remap(i))
1639 printf(", ha 0x%08x", win_idma_har_read(base, i));
1643 for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
1644 printf("IDMA channel#%d: ap 0x%08x\n", i,
1645 win_idma_cap_read(base, i));
1646 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base));
1650 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */
1652 decode_win_idma_valid(void)
1659 decode_win_idma_setup(u_long base)
1664 decode_win_idma_dump(u_long base)
1669 /**************************************************************************
1670 * XOR windows routines
1671 **************************************************************************/
1672 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
1674 xor_ctrl_read(u_long base, int i, int c, int e)
1677 v = win_xor_ctrl_read(base, c, e);
1684 xor_ctrl_write(u_long base, int i, int c, int e, int val)
1688 v = win_xor_ctrl_read(base, c, e);
1691 win_xor_ctrl_write(base, c, e, v);
1695 * Set channel protection 'val' for window 'w' on channel 'c'
1698 xor_chan_write(u_long base, int c, int e, int w, int val)
1702 v = win_xor_ctrl_read(base, c, e);
1703 v &= ~(0x3 << (w * 2 + 16));
1704 v |= (val << (w * 2 + 16));
1705 win_xor_ctrl_write(base, c, e, v);
1709 * Set protection 'val' on all channels for window 'w' on engine 'e'
1712 xor_set_prot(u_long base, int w, int e, int val)
1716 for (c = 0; c < MV_XOR_CHAN_MAX; c++)
1717 xor_chan_write(base, c, e, w, val);
1721 win_xor_can_remap(int i)
1724 /* XOR decode windows 0-3 have remap capability */
1738 case MV_DEV_88F6281:
1739 case MV_DEV_88F6282:
1740 case MV_DEV_MV78130:
1741 case MV_DEV_MV78160:
1742 case MV_DEV_MV78230:
1743 case MV_DEV_MV78260:
1744 case MV_DEV_MV78460:
1746 case MV_DEV_MV78100:
1747 case MV_DEV_MV78100_Z0:
1755 xor_active_dram(u_long base, int c, int e, int *window)
1761 * Set up access to all active DRAM banks
1764 for (i = 0; i < m; i++)
1765 if (ddr_is_active(i)) {
1766 br = ddr_base(i) | (ddr_attr(i) << 8) |
1768 sz = ((ddr_size(i) - 1) & 0xffff0000);
1770 /* Place DDR entries in non-remapped windows */
1771 for (w = 0; w < MV_WIN_XOR_MAX; w++)
1772 if (win_xor_can_remap(w) != 1 &&
1773 (xor_ctrl_read(base, w, c, e) == 0) &&
1775 /* Configure window */
1776 win_xor_br_write(base, w, e, br);
1777 win_xor_sz_write(base, w, e, sz);
1779 /* Set protection RW on all channels */
1780 xor_set_prot(base, w, e, 0x3);
1783 xor_ctrl_write(base, w, c, e, 1);
1791 decode_win_xor_setup(u_long base)
1794 int i, j, z, e = 1, m, window;
1796 if (pm_is_disabled(CPU_PM_CTRL_XOR))
1800 * Disable and clear all XOR windows, revoke protection for all
1804 for (j = 0; j < m; j++, e--) {
1806 /* Number of non-remaped windows */
1807 window = MV_XOR_NON_REMAP - 1;
1809 for (i = 0; i < MV_WIN_XOR_MAX; i++) {
1810 win_xor_br_write(base, i, e, 0);
1811 win_xor_sz_write(base, i, e, 0);
1814 if (win_xor_can_remap(i) == 1)
1815 win_xor_har_write(base, i, e, 0);
1817 for (i = 0; i < MV_XOR_CHAN_MAX; i++) {
1818 win_xor_ctrl_write(base, i, e, 0);
1819 xor_active_dram(base, i, e, &window);
1823 * Remaining targets -- from a statically defined table
1825 for (i = 0; i < xor_wins_no; i++)
1826 if (xor_wins[i].target > 0) {
1827 br = (xor_wins[i].base & 0xffff0000) |
1828 (xor_wins[i].attr << 8) |
1830 sz = ((xor_wins[i].size - 1) & 0xffff0000);
1832 /* Set the first free XOR window */
1833 for (z = 0; z < MV_WIN_XOR_MAX; z++) {
1834 if (xor_ctrl_read(base, z, 0, e) &&
1835 xor_ctrl_read(base, z, 1, e))
1838 /* Configure window */
1839 win_xor_br_write(base, z, e, br);
1840 win_xor_sz_write(base, z, e, sz);
1841 if (win_xor_can_remap(z) &&
1842 xor_wins[z].remap >= 0)
1843 win_xor_har_write(base, z, e,
1846 /* Set protection RW on all channels */
1847 xor_set_prot(base, z, e, 0x3);
1850 xor_ctrl_write(base, z, 0, e, 1);
1851 xor_ctrl_write(base, z, 1, e, 1);
1859 decode_win_xor_valid(void)
1861 const struct decode_win *wintab;
1865 if (xor_wins_no > MV_WIN_XOR_MAX) {
1866 printf("XOR windows: too many entries: %d\n", xor_wins_no);
1869 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
1870 if (ddr_is_active(i))
1873 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) {
1874 printf("XOR windows: too many entries: %d, available: %d\n",
1875 xor_wins_no, MV_WIN_IDMA_MAX - c);
1881 for (i = 0; i < xor_wins_no; i++, wintab++) {
1883 if (wintab->target == 0) {
1884 printf("XOR window#%d: DDR target window is not "
1885 "supposed to be reprogrammed!\n", i);
1889 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
1890 printf("XOR window#%d: not capable of remapping, but "
1891 "val 0x%08x defined\n", i, wintab->remap);
1898 if (s > (0xFFFFFFFF - b + 1)) {
1900 * XXX this boundary check should account for 64bit
1903 printf("XOR window#%d: no space for size 0x%08x at "
1904 "0x%08x\n", i, s, b);
1909 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]);
1911 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps "
1912 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
1914 xor_wins[j].base + xor_wins[j].size - 1);
1923 decode_win_xor_dump(u_long base)
1928 if (pm_is_disabled(CPU_PM_CTRL_XOR))
1931 for (j = 0; j < xor_max_eng(); j++, e--) {
1932 for (i = 0; i < MV_WIN_XOR_MAX; i++) {
1933 printf("XOR window#%d: b 0x%08x, s 0x%08x", i,
1934 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e));
1936 if (win_xor_can_remap(i))
1937 printf(", ha 0x%08x", win_xor_har_read(base, i, e));
1941 for (i = 0; i < MV_XOR_CHAN_MAX; i++)
1942 printf("XOR control#%d: 0x%08x\n", i,
1943 win_xor_ctrl_read(base, i, e));
1948 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */
1950 decode_win_xor_valid(void)
1957 decode_win_xor_setup(u_long base)
1962 decode_win_xor_dump(u_long base)
1967 /**************************************************************************
1968 * SATA windows routines
1969 **************************************************************************/
1971 decode_win_sata_setup(u_long base)
1976 if (pm_is_disabled(CPU_PM_CTRL_SATA))
1979 for (i = 0; i < MV_WIN_SATA_MAX; i++) {
1980 win_sata_cr_write(base, i, 0);
1981 win_sata_br_write(base, i, 0);
1984 for (i = 0; i < MV_WIN_DDR_MAX; i++)
1985 if (ddr_is_active(i)) {
1986 cr = ((ddr_size(i) - 1) & 0xffff0000) |
1987 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
1990 /* Use the first available SATA window */
1991 for (j = 0; j < MV_WIN_SATA_MAX; j++) {
1992 if ((win_sata_cr_read(base, j) & 1) != 0)
1995 win_sata_br_write(base, j, br);
1996 win_sata_cr_write(base, j, cr);
2003 decode_win_sata_valid(void)
2008 if (dev == MV_DEV_88F5281)
2011 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX));
2014 /**************************************************************************
2015 * FDT parsing routines.
2016 **************************************************************************/
2019 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples,
2023 pcell_t addr_cells, par_addr_cells, size_cells;
2024 int len, tuple_size, tuples_count;
2026 node = OF_finddevice(nodename);
2030 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
2033 par_addr_cells = fdt_parent_addr_cells(node);
2034 if (par_addr_cells > 2)
2037 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
2040 /* Note the OF_getprop_alloc() cannot be used at this early stage. */
2041 len = OF_getprop(node, "ranges", buf, size);
2044 * XXX this does not handle the empty 'ranges;' case, which is
2045 * legitimate and should be allowed.
2047 tuples_count = len / tuple_size;
2048 if (tuples_count <= 0)
2051 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2)
2054 *tuples = tuples_count;
2055 *tuplesize = tuple_size;
2060 win_cpu_from_dt(void)
2064 int i, entry_size, err, t, tuple_size, tuples;
2065 u_long sram_base, sram_size;
2068 /* Retrieve 'ranges' property of '/localbus' node. */
2069 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges),
2070 &tuples, &tuple_size)) == 0) {
2072 * Fill CPU decode windows table.
2074 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl));
2076 entry_size = tuple_size / sizeof(pcell_t);
2077 cpu_wins_no = tuples;
2079 for (i = 0, t = 0; t < tuples; i += entry_size, t++) {
2080 cpu_win_tbl[t].target = 1;
2081 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]);
2082 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]);
2083 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]);
2084 cpu_win_tbl[t].remap = ~0;
2085 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x "
2086 "size = 0x%0x remap = 0x%0x\n",
2087 cpu_win_tbl[t].target,
2088 cpu_win_tbl[t].attr, cpu_win_tbl[t].base,
2089 cpu_win_tbl[t].size, cpu_win_tbl[t].remap);
2094 * Retrieve CESA SRAM data.
2096 if ((node = OF_finddevice("sram")) != -1)
2097 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram"))
2100 if ((node = OF_finddevice("/")) == 0)
2103 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0)
2104 /* SRAM block is not always present. */
2107 sram_base = sram_size = 0;
2108 if (fdt_regsize(node, &sram_base, &sram_size) != 0)
2111 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
2112 #ifdef SOC_MV_ARMADA38X
2113 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0);
2115 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
2117 cpu_win_tbl[t].base = sram_base;
2118 cpu_win_tbl[t].size = sram_size;
2119 cpu_win_tbl[t].remap = ~0;
2121 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);
2123 /* Check if there is a second CESA node */
2124 while ((node = OF_peer(node)) != 0) {
2125 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) {
2126 if (fdt_regsize(node, &sram_base, &sram_size) != 0)
2136 if (t >= nitems(cpu_win_tbl)) {
2137 debugf("cannot fit CESA tuple into cpu_win_tbl\n");
2141 /* Configure window for CESA1 */
2142 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
2143 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
2144 cpu_win_tbl[t].base = sram_base;
2145 cpu_win_tbl[t].size = sram_size;
2146 cpu_win_tbl[t].remap = ~0;
2148 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);
2156 phandle_t node, child;
2157 struct soc_node_spec *soc_node;
2161 node = OF_finddevice("/");
2163 panic("fdt_win_setup: no root node");
2166 * Traverse through all children of root and simple-bus nodes.
2167 * For each found device retrieve decode windows data (if applicable).
2169 child = OF_child(node);
2170 while (child != 0) {
2171 for (i = 0; soc_nodes[i].compat != NULL; i++) {
2173 soc_node = &soc_nodes[i];
2175 if (!ofw_bus_node_is_compatible(child,soc_node->compat))
2178 err = fdt_regsize(child, &base, &size);
2182 base = (base & 0x000fffff) | fdt_immr_va;
2183 if (soc_node->decode_handler != NULL)
2184 soc_node->decode_handler(base);
2188 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL))
2189 soc_node->dump_handler(base);
2193 * Once done with root-level children let's move down to
2194 * simple-bus and its children.
2196 child = OF_peer(child);
2197 if ((child == 0) && (node == OF_finddevice("/"))) {
2198 node = fdt_find_compatible(node, "simple-bus", 0);
2201 child = OF_child(node);
2204 * Next, move one more level down to internal-regs node (if
2205 * it is present) and its children. This node also have
2206 * "simple-bus" compatible.
2208 if ((child == 0) && (node == OF_finddevice("simple-bus"))) {
2209 node = fdt_find_compatible(node, "simple-bus", 0);
2212 child = OF_child(node);
2220 fdt_fixup_busfreq(phandle_t root)
2225 freq = cpu_to_fdt32(get_tclk());
2228 * Fix bus speed in cpu node
2230 if ((sb = OF_finddevice("cpu")) != 0)
2231 if (fdt_is_compatible_strict(sb, "ARM,88VS584"))
2232 OF_setprop(sb, "bus-frequency", (void *)&freq,
2236 * This fixup sets the simple-bus bus-frequency property.
2238 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0)
2239 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq));
2243 fdt_fixup_ranges(phandle_t root)
2246 pcell_t par_addr_cells, addr_cells, size_cells;
2247 pcell_t ranges[3], reg[2], *rangesptr;
2248 int len, tuple_size, tuples_count;
2251 /* Fix-up SoC ranges according to real fdt_immr_pa */
2252 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) {
2253 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 &&
2254 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) {
2255 tuple_size = sizeof(pcell_t) * (par_addr_cells +
2256 addr_cells + size_cells);
2257 len = OF_getprop(node, "ranges", ranges,
2259 tuples_count = len / tuple_size;
2260 /* Unexpected settings are not supported */
2261 if (tuples_count != 1)
2264 rangesptr = &ranges[0];
2265 rangesptr += par_addr_cells;
2266 base = fdt_data_get((void *)rangesptr, addr_cells);
2267 *rangesptr = cpu_to_fdt32(fdt_immr_pa);
2268 if (OF_setprop(node, "ranges", (void *)&ranges[0],
2269 sizeof(ranges)) < 0)
2274 /* Fix-up PCIe reg according to real PCIe registers' PA */
2275 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) {
2276 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
2277 &size_cells) == 0) {
2278 tuple_size = sizeof(pcell_t) * (par_addr_cells +
2280 len = OF_getprop(node, "reg", reg, sizeof(reg));
2281 tuples_count = len / tuple_size;
2282 /* Unexpected settings are not supported */
2283 if (tuples_count != 1)
2286 base = fdt_data_get((void *)®[0], par_addr_cells);
2287 base &= ~0xFF000000;
2288 base |= fdt_immr_pa;
2289 reg[0] = cpu_to_fdt32(base);
2290 if (OF_setprop(node, "reg", (void *)®[0],
2295 /* Fix-up succeeded. May return and continue */
2301 * In case of any error while fixing ranges just hang.
2302 * 1. No message can be displayed yet since console
2303 * is not initialized.
2304 * 2. Going further will cause failure on bus_space_map()
2305 * relying on the wrong ranges or data abort when
2306 * accessing PCIe registers.
2311 struct fdt_fixup_entry fdt_fixup_table[] = {
2312 { "mrvl,DB-88F6281", &fdt_fixup_busfreq },
2313 { "mrvl,DB-78460", &fdt_fixup_busfreq },
2314 { "mrvl,DB-78460", &fdt_fixup_ranges },
2320 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
2324 if (!ofw_bus_node_is_compatible(node, "mrvl,pic") &&
2325 !ofw_bus_node_is_compatible(node, "mrvl,mpic"))
2328 *interrupt = fdt32_to_cpu(intr[0]);
2329 *trig = INTR_TRIGGER_CONFORM;
2330 *pol = INTR_POLARITY_CONFORM;
2335 fdt_pic_decode_t fdt_pic_table[] = {
2336 #ifdef SOC_MV_ARMADA38X
2347 uint32_t sar_low, sar_high;
2349 #if defined(SOC_MV_ARMADAXP)
2350 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
2351 SAMPLE_AT_RESET_HI);
2352 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
2353 SAMPLE_AT_RESET_LO);
2354 #elif defined(SOC_MV_ARMADA38X)
2356 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
2360 * TODO: Add getting proper values for other SoC configurations
2366 return (((uint64_t)sar_high << 32) | sar_low);