2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
41 #include <sys/mutex.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/intr.h>
47 #include <dev/fdt/simplebus.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/extres/clk/clk_fixed.h>
53 #include <dev/extres/clk/clk_gate.h>
55 #include <arm/mv/mv_cp110_clock.h>
57 #include "clkdev_if.h"
60 static struct clk_fixed_def cp110_clk_pll_0 = {
61 .clkdef.id = CP110_PLL_0,
65 static const char *clk_parents_0[] = {"cp110-pll0-0"};
66 static const char *clk_parents_1[] = {"cp110-pll0-1"};
68 static struct clk_fixed_def cp110_clk_ppv2_core = {
69 .clkdef.id = CP110_PPV2_CORE,
70 .clkdef.parent_cnt = 1,
75 static struct clk_fixed_def cp110_clk_x2core = {
76 .clkdef.id = CP110_X2CORE,
77 .clkdef.parent_cnt = 1,
82 static const char *core_parents_0[] = {"cp110-x2core-0"};
83 static const char *core_parents_1[] = {"cp110-x2core-1"};
85 static struct clk_fixed_def cp110_clk_core = {
86 .clkdef.id = CP110_CORE,
87 .clkdef.parent_cnt = 1,
92 static struct clk_fixed_def cp110_clk_sdio = {
93 .clkdef.id = CP110_SDIO,
94 .clkdef.parent_cnt = 1,
101 static struct cp110_gate cp110_gates[] = {
102 CCU_GATE(CP110_GATE_AUDIO, "cp110-gate-audio", 0)
103 CCU_GATE(CP110_GATE_COMM_UNIT, "cp110-gate-comm_unit", 1)
104 /* CCU_GATE(CP110_GATE_NAND, "cp110-gate-nand", 2) */
105 CCU_GATE(CP110_GATE_PPV2, "cp110-gate-ppv2", 3)
106 CCU_GATE(CP110_GATE_SDIO, "cp110-gate-sdio", 4)
107 CCU_GATE(CP110_GATE_MG, "cp110-gate-mg", 5)
108 CCU_GATE(CP110_GATE_MG_CORE, "cp110-gate-mg_core", 6)
109 CCU_GATE(CP110_GATE_XOR1, "cp110-gate-xor1", 7)
110 CCU_GATE(CP110_GATE_XOR0, "cp110-gate-xor0", 8)
111 CCU_GATE(CP110_GATE_GOP_DP, "cp110-gate-gop_dp", 9)
112 CCU_GATE(CP110_GATE_PCIE_X1_0, "cp110-gate-pcie_x10", 11)
113 CCU_GATE(CP110_GATE_PCIE_X1_1, "cp110-gate-pcie_x11", 12)
114 CCU_GATE(CP110_GATE_PCIE_X4, "cp110-gate-pcie_x4", 13)
115 CCU_GATE(CP110_GATE_PCIE_XOR, "cp110-gate-pcie_xor", 14)
116 CCU_GATE(CP110_GATE_SATA, "cp110-gate-sata", 15)
117 CCU_GATE(CP110_GATE_SATA_USB, "cp110-gate-sata_usb", 16)
118 CCU_GATE(CP110_GATE_MAIN, "cp110-gate-main", 17)
119 CCU_GATE(CP110_GATE_SDMMC_GOP, "cp110-gate-sdmmc_gop", 18)
120 CCU_GATE(CP110_GATE_SLOW_IO, "cp110-gate-slow_io", 21)
121 CCU_GATE(CP110_GATE_USB3H0, "cp110-gate-usb3h0", 22)
122 CCU_GATE(CP110_GATE_USB3H1, "cp110-gate-usb3h1", 23)
123 CCU_GATE(CP110_GATE_USB3DEV, "cp110-gate-usb3dev", 24)
124 CCU_GATE(CP110_GATE_EIP150, "cp110-gate-eip150", 25)
125 CCU_GATE(CP110_GATE_EIP197, "cp110-gate-eip197", 26)
128 struct mv_cp110_clock_softc {
129 struct simplebus_softc simplebus_sc;
131 struct resource *res;
135 static struct resource_spec mv_cp110_clock_res_spec[] = {
136 { SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE },
140 static struct ofw_compat_data compat_data[] = {
141 {"marvell,cp110-clock", 1},
145 #define RD4(sc, reg) bus_read_4((sc)->res, (reg))
146 #define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
149 mv_cp110_clock_name(device_t dev, const char *name)
151 char *clkname = NULL;
154 unit = device_get_unit(dev);
155 if (asprintf(&clkname, M_DEVBUF, "%s-%d", name, unit) <= 0)
156 panic("Cannot generate unique clock name for %s\n", name);
161 mv_cp110_clock_probe(device_t dev)
164 if (!ofw_bus_status_okay(dev))
167 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
170 device_set_desc(dev, "Marvell CP110 Clock Controller");
171 return (BUS_PROBE_DEFAULT);
175 cp110_ofw_map(struct clkdom *clkdom, uint32_t ncells,
176 phandle_t *cells, struct clknode **clk)
185 id += CP110_MAX_CLOCK;
187 *clk = clknode_find_by_id(clkdom, id);
193 mv_cp110_clock_attach(device_t dev)
195 struct mv_cp110_clock_softc *sc;
196 struct clkdom *clkdom;
197 struct clk_gate_def def;
201 sc = device_get_softc(dev);
204 if (bus_alloc_resources(dev, mv_cp110_clock_res_spec, &sc->res) != 0) {
205 device_printf(dev, "cannot allocate resources for device\n");
209 unit = device_get_unit(dev);
211 device_printf(dev, "Bogus cp110-system-controller unit %d\n", unit);
215 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
217 clkdom = clkdom_create(dev);
218 clkdom_set_ofw_mapper(clkdom, cp110_ofw_map);
220 pll0_name = mv_cp110_clock_name(dev, "cp110-pll0");
221 cp110_clk_pll_0.clkdef.name = pll0_name;
222 clknode_fixed_register(clkdom, &cp110_clk_pll_0);
224 cp110_clk_ppv2_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-ppv2");
225 cp110_clk_ppv2_core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1;
226 clknode_fixed_register(clkdom, &cp110_clk_ppv2_core);
228 cp110_clk_x2core.clkdef.name = mv_cp110_clock_name(dev, "cp110-x2core");
229 cp110_clk_x2core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1;
230 clknode_fixed_register(clkdom, &cp110_clk_x2core);
232 cp110_clk_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-core");
233 cp110_clk_core.clkdef.parent_names = (unit == 0) ? core_parents_0 : core_parents_1;
234 clknode_fixed_register(clkdom, &cp110_clk_core);
238 cp110_clk_sdio.clkdef.name = mv_cp110_clock_name(dev, "cp110-sdio");
239 cp110_clk_sdio.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1;
240 clknode_fixed_register(clkdom, &cp110_clk_sdio);
242 for (i = 0; i < nitems(cp110_gates); i++) {
243 if (cp110_gates[i].name == NULL)
246 memset(&def, 0, sizeof(def));
247 def.clkdef.id = CP110_MAX_CLOCK + i;
248 def.clkdef.name = mv_cp110_clock_name(dev, cp110_gates[i].name);
249 def.clkdef.parent_cnt = 1;
250 def.offset = CP110_CLOCK_GATING_OFFSET;
251 def.shift = cp110_gates[i].shift;
258 case CP110_GATE_GOP_DP:
259 case CP110_GATE_PPV2:
260 def.clkdef.parent_names = &cp110_clk_ppv2_core.clkdef.name;
262 case CP110_GATE_SDIO:
263 def.clkdef.parent_names = &cp110_clk_sdio.clkdef.name;
265 case CP110_GATE_MAIN:
266 case CP110_GATE_PCIE_XOR:
267 case CP110_GATE_PCIE_X4:
268 case CP110_GATE_EIP150:
269 case CP110_GATE_EIP197:
270 def.clkdef.parent_names = &cp110_clk_x2core.clkdef.name;
273 def.clkdef.parent_names = &cp110_clk_core.clkdef.name;
277 clknode_gate_register(clkdom, &def);
280 clkdom_finit(clkdom);
289 mv_cp110_clock_detach(device_t dev)
296 mv_cp110_clock_write_4(device_t dev, bus_addr_t addr, uint32_t val)
298 struct mv_cp110_clock_softc *sc;
300 sc = device_get_softc(dev);
306 mv_cp110_clock_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
308 struct mv_cp110_clock_softc *sc;
310 sc = device_get_softc(dev);
312 *val = RD4(sc, addr);
317 mv_cp110_clock_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set)
319 struct mv_cp110_clock_softc *sc;
322 sc = device_get_softc(dev);
333 mv_cp110_clock_device_lock(device_t dev)
335 struct mv_cp110_clock_softc *sc;
337 sc = device_get_softc(dev);
342 mv_cp110_clock_device_unlock(device_t dev)
344 struct mv_cp110_clock_softc *sc;
346 sc = device_get_softc(dev);
347 mtx_unlock(&sc->mtx);
350 static device_method_t mv_cp110_clock_methods[] = {
351 /* Device interface */
352 DEVMETHOD(device_probe, mv_cp110_clock_probe),
353 DEVMETHOD(device_attach, mv_cp110_clock_attach),
354 DEVMETHOD(device_detach, mv_cp110_clock_detach),
356 /* clkdev interface */
357 DEVMETHOD(clkdev_write_4, mv_cp110_clock_write_4),
358 DEVMETHOD(clkdev_read_4, mv_cp110_clock_read_4),
359 DEVMETHOD(clkdev_modify_4, mv_cp110_clock_modify_4),
360 DEVMETHOD(clkdev_device_lock, mv_cp110_clock_device_lock),
361 DEVMETHOD(clkdev_device_unlock, mv_cp110_clock_device_unlock),
366 static devclass_t mv_cp110_clock_devclass;
368 static driver_t mv_cp110_clock_driver = {
370 mv_cp110_clock_methods,
371 sizeof(struct mv_cp110_clock_softc),
374 EARLY_DRIVER_MODULE(mv_cp110_clock, simplebus, mv_cp110_clock_driver,
375 mv_cp110_clock_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE);