2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
41 #include <sys/mutex.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/intr.h>
47 #include <dev/fdt/simplebus.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
52 #include <gnu/dts/include/dt-bindings/interrupt-controller/irq.h>
55 #define ICU_GRP_NSR 0x0
56 #define ICU_GRP_SR 0x1
57 #define ICU_GRP_SEI 0x4
58 #define ICU_GRP_REI 0x5
60 #define ICU_SETSPI_NSR_AL 0x10
61 #define ICU_SETSPI_NSR_AH 0x14
62 #define ICU_CLRSPI_NSR_AL 0x18
63 #define ICU_CLRSPI_NSR_AH 0x1c
64 #define ICU_INT_CFG(x) (0x100 + (x) * 4)
65 #define ICU_INT_ENABLE (1 << 24)
66 #define ICU_INT_EDGE (1 << 28)
67 #define ICU_INT_GROUP_SHIFT 29
68 #define ICU_INT_MASK 0x3ff
70 #define MV_CP110_ICU_MAX_NIRQS 207
72 struct mv_cp110_icu_softc {
76 struct intr_map_data_fdt *parent_map_data;
79 static struct resource_spec mv_cp110_icu_res_spec[] = {
80 { SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE },
84 static struct ofw_compat_data compat_data[] = {
85 {"marvell,cp110-icu-nsr", 1},
86 {"marvell,cp110-icu-sei", 2},
90 #define RD4(sc, reg) bus_read_4((sc)->res, (reg))
91 #define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
94 mv_cp110_icu_probe(device_t dev)
97 if (!ofw_bus_status_okay(dev))
100 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
103 device_set_desc(dev, "Marvell Interrupt Consolidation Unit");
104 return (BUS_PROBE_DEFAULT);
108 mv_cp110_icu_attach(device_t dev)
110 struct mv_cp110_icu_softc *sc;
111 phandle_t node, msi_parent;
113 sc = device_get_softc(dev);
115 node = ofw_bus_get_node(dev);
117 if (OF_getencprop(node, "msi-parent", &msi_parent,
118 sizeof(phandle_t)) <= 0) {
119 device_printf(dev, "cannot find msi-parent property\n");
123 if ((sc->parent = OF_device_from_xref(msi_parent)) == NULL) {
124 device_printf(dev, "cannot find msi-parent device\n");
127 if (bus_alloc_resources(dev, mv_cp110_icu_res_spec, &sc->res) != 0) {
128 device_printf(dev, "cannot allocate resources for device\n");
132 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) {
133 device_printf(dev, "Cannot register ICU\n");
137 /* Allocate GICP compatible mapping entry (2 cells) */
138 sc->parent_map_data = (struct intr_map_data_fdt *)intr_alloc_map_data(
139 INTR_MAP_DATA_FDT, sizeof(struct intr_map_data_fdt) +
140 + 3 * sizeof(phandle_t), M_WAITOK | M_ZERO);
144 bus_release_resources(dev, mv_cp110_icu_res_spec, &sc->res);
148 static struct intr_map_data *
149 mv_cp110_icu_convert_map_data(struct mv_cp110_icu_softc *sc, struct intr_map_data *data)
151 struct intr_map_data_fdt *daf;
152 uint32_t reg, irq_no, irq_type;
154 daf = (struct intr_map_data_fdt *)data;
155 if (daf->ncells != 2)
157 irq_no = daf->cells[0];
158 irq_type = daf->cells[1];
159 if (irq_no >= MV_CP110_ICU_MAX_NIRQS)
161 if (irq_type != IRQ_TYPE_LEVEL_HIGH &&
162 irq_type != IRQ_TYPE_EDGE_RISING)
165 /* We rely on fact that ICU->GIC mapping is preset by bootstrap. */
166 reg = RD4(sc, ICU_INT_CFG(irq_no));
168 /* Construct GICP compatible mapping. */
169 sc->parent_map_data->ncells = 2;
170 sc->parent_map_data->cells[0] = reg & ICU_INT_MASK;
171 sc->parent_map_data->cells[1] = irq_type;
173 return ((struct intr_map_data *)sc->parent_map_data);
178 mv_cp110_icu_detach(device_t dev)
185 mv_cp110_icu_activate_intr(device_t dev, struct intr_irqsrc *isrc,
186 struct resource *res, struct intr_map_data *data)
188 struct mv_cp110_icu_softc *sc;
190 sc = device_get_softc(dev);
191 data = mv_cp110_icu_convert_map_data(sc, data);
194 return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data));
198 mv_cp110_icu_enable_intr(device_t dev, struct intr_irqsrc *isrc)
200 struct mv_cp110_icu_softc *sc;
201 sc = device_get_softc(dev);
203 PIC_ENABLE_INTR(sc->parent, isrc);
207 mv_cp110_icu_disable_intr(device_t dev, struct intr_irqsrc *isrc)
209 struct mv_cp110_icu_softc *sc;
211 sc = device_get_softc(dev);
213 PIC_DISABLE_INTR(sc->parent, isrc);
219 mv_cp110_icu_map_intr(device_t dev, struct intr_map_data *data,
220 struct intr_irqsrc **isrcp)
222 struct mv_cp110_icu_softc *sc;
223 struct intr_map_data_fdt *daf;
224 uint32_t reg, irq_no, irq_type;
227 sc = device_get_softc(dev);
229 if (data->type != INTR_MAP_DATA_FDT)
233 daf = (struct intr_map_data_fdt *)data;
234 if (daf->ncells != 2)
236 irq_no = daf->cells[0];
237 irq_type = daf->cells[1];
238 data = mv_cp110_icu_convert_map_data(sc, data);
242 reg = RD4(sc, ICU_INT_CFG(irq_no));
243 reg |= ICU_INT_ENABLE;
244 if (irq_type == IRQ_TYPE_LEVEL_HIGH)
245 reg &= ~ICU_INT_EDGE;
248 WR4(sc, ICU_INT_CFG(irq_no), reg);
250 ret = PIC_MAP_INTR(sc->parent, data, isrcp);
251 (*isrcp)->isrc_dev = sc->dev;
256 mv_cp110_icu_deactivate_intr(device_t dev, struct intr_irqsrc *isrc,
257 struct resource *res, struct intr_map_data *data)
259 struct mv_cp110_icu_softc *sc;
261 sc = device_get_softc(dev);
262 data = mv_cp110_icu_convert_map_data(sc, data);
266 return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data));
270 mv_cp110_icu_setup_intr(device_t dev, struct intr_irqsrc *isrc,
271 struct resource *res, struct intr_map_data *data)
273 struct mv_cp110_icu_softc *sc;
275 sc = device_get_softc(dev);
276 data = mv_cp110_icu_convert_map_data(sc, data);
280 return (PIC_SETUP_INTR(sc->parent, isrc, res, data));
284 mv_cp110_icu_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
285 struct resource *res, struct intr_map_data *data)
287 struct mv_cp110_icu_softc *sc;
289 sc = device_get_softc(dev);
290 data = mv_cp110_icu_convert_map_data(sc, data);
294 return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data));
298 mv_cp110_icu_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
300 struct mv_cp110_icu_softc *sc;
302 sc = device_get_softc(dev);
304 PIC_PRE_ITHREAD(sc->parent, isrc);
308 mv_cp110_icu_post_ithread(device_t dev, struct intr_irqsrc *isrc)
310 struct mv_cp110_icu_softc *sc;
312 sc = device_get_softc(dev);
314 PIC_POST_ITHREAD(sc->parent, isrc);
318 mv_cp110_icu_post_filter(device_t dev, struct intr_irqsrc *isrc)
320 struct mv_cp110_icu_softc *sc;
322 sc = device_get_softc(dev);
324 PIC_POST_FILTER(sc->parent, isrc);
327 static device_method_t mv_cp110_icu_methods[] = {
328 /* Device interface */
329 DEVMETHOD(device_probe, mv_cp110_icu_probe),
330 DEVMETHOD(device_attach, mv_cp110_icu_attach),
331 DEVMETHOD(device_detach, mv_cp110_icu_detach),
333 /* Interrupt controller interface */
334 DEVMETHOD(pic_activate_intr, mv_cp110_icu_activate_intr),
335 DEVMETHOD(pic_disable_intr, mv_cp110_icu_disable_intr),
336 DEVMETHOD(pic_enable_intr, mv_cp110_icu_enable_intr),
337 DEVMETHOD(pic_map_intr, mv_cp110_icu_map_intr),
338 DEVMETHOD(pic_deactivate_intr, mv_cp110_icu_deactivate_intr),
339 DEVMETHOD(pic_setup_intr, mv_cp110_icu_setup_intr),
340 DEVMETHOD(pic_teardown_intr, mv_cp110_icu_teardown_intr),
341 DEVMETHOD(pic_post_filter, mv_cp110_icu_post_filter),
342 DEVMETHOD(pic_post_ithread, mv_cp110_icu_post_ithread),
343 DEVMETHOD(pic_pre_ithread, mv_cp110_icu_pre_ithread),
348 static devclass_t mv_cp110_icu_devclass;
350 static driver_t mv_cp110_icu_driver = {
352 mv_cp110_icu_methods,
353 sizeof(struct mv_cp110_icu_softc),
356 EARLY_DRIVER_MODULE(mv_cp110_icu, mv_cp110_icu_bus, mv_cp110_icu_driver,
357 mv_cp110_icu_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST);