2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
41 #include <sys/mutex.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/intr.h>
47 #include <dev/fdt/simplebus.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dt-bindings/interrupt-controller/irq.h>
57 #define ICU_TYPE_NSR 1
58 #define ICU_TYPE_SEI 2
60 #define ICU_GRP_NSR 0x0
61 #define ICU_GRP_SR 0x1
62 #define ICU_GRP_SEI 0x4
63 #define ICU_GRP_REI 0x5
65 #define ICU_SETSPI_NSR_AL 0x10
66 #define ICU_SETSPI_NSR_AH 0x14
67 #define ICU_CLRSPI_NSR_AL 0x18
68 #define ICU_CLRSPI_NSR_AH 0x1c
69 #define ICU_SETSPI_SEI_AL 0x50
70 #define ICU_SETSPI_SEI_AH 0x54
71 #define ICU_INT_CFG(x) (0x100 + (x) * 4)
72 #define ICU_INT_ENABLE (1 << 24)
73 #define ICU_INT_EDGE (1 << 28)
74 #define ICU_INT_GROUP_SHIFT 29
75 #define ICU_INT_MASK 0x3ff
77 #define ICU_INT_SATA0 109
78 #define ICU_INT_SATA1 107
80 #define MV_CP110_ICU_MAX_NIRQS 207
82 #define MV_CP110_ICU_CLRSPI_OFFSET 0x8
84 struct mv_cp110_icu_softc {
88 struct intr_map_data_fdt *parent_map_data;
93 static struct resource_spec mv_cp110_icu_res_spec[] = {
94 { SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE },
98 static struct ofw_compat_data compat_data[] = {
99 {"marvell,cp110-icu-nsr", ICU_TYPE_NSR},
100 {"marvell,cp110-icu-sei", ICU_TYPE_SEI},
104 #define RD4(sc, reg) bus_read_4((sc)->res, (reg))
105 #define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
108 mv_cp110_icu_probe(device_t dev)
111 if (!ofw_bus_status_okay(dev))
114 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
117 device_set_desc(dev, "Marvell Interrupt Consolidation Unit");
118 return (BUS_PROBE_DEFAULT);
122 mv_cp110_icu_attach(device_t dev)
124 struct mv_cp110_icu_softc *sc;
125 phandle_t node, msi_parent;
126 uint32_t reg, icu_grp;
129 sc = device_get_softc(dev);
131 node = ofw_bus_get_node(dev);
132 sc->type = (int)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
133 sc->initialized = false;
135 if (OF_getencprop(node, "msi-parent", &msi_parent,
136 sizeof(phandle_t)) <= 0) {
137 device_printf(dev, "cannot find msi-parent property\n");
141 if ((sc->parent = OF_device_from_xref(msi_parent)) == NULL) {
142 device_printf(dev, "cannot find msi-parent device\n");
145 if (bus_alloc_resources(dev, mv_cp110_icu_res_spec, &sc->res) != 0) {
146 device_printf(dev, "cannot allocate resources for device\n");
150 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) {
151 device_printf(dev, "Cannot register ICU\n");
155 /* Allocate GICP/SEI compatible mapping entry (2 cells) */
156 sc->parent_map_data = (struct intr_map_data_fdt *)intr_alloc_map_data(
157 INTR_MAP_DATA_FDT, sizeof(struct intr_map_data_fdt) +
158 + 3 * sizeof(phandle_t), M_WAITOK | M_ZERO);
160 /* Clear any previous mapping done by firmware. */
161 for (i = 0; i < MV_CP110_ICU_MAX_NIRQS; i++) {
162 reg = RD4(sc, ICU_INT_CFG(i));
163 icu_grp = reg >> ICU_INT_GROUP_SHIFT;
165 if (icu_grp == ICU_GRP_NSR || icu_grp == ICU_GRP_SEI)
166 WR4(sc, ICU_INT_CFG(i), 0);
172 bus_release_resources(dev, mv_cp110_icu_res_spec, &sc->res);
176 static struct intr_map_data *
177 mv_cp110_icu_convert_map_data(struct mv_cp110_icu_softc *sc, struct intr_map_data *data)
179 struct intr_map_data_fdt *daf;
180 uint32_t reg, irq_no, irq_type;
182 daf = (struct intr_map_data_fdt *)data;
183 if (daf->ncells != 2)
186 irq_no = daf->cells[0];
187 if (irq_no >= MV_CP110_ICU_MAX_NIRQS)
190 irq_type = daf->cells[1];
191 if (irq_type != IRQ_TYPE_LEVEL_HIGH &&
192 irq_type != IRQ_TYPE_EDGE_RISING)
195 /* ICU -> GICP/SEI mapping is set in mv_cp110_icu_map_intr. */
196 reg = RD4(sc, ICU_INT_CFG(irq_no));
198 /* Construct GICP compatible mapping. */
199 sc->parent_map_data->ncells = 2;
200 sc->parent_map_data->cells[0] = reg & ICU_INT_MASK;
201 sc->parent_map_data->cells[1] = irq_type;
203 return ((struct intr_map_data *)sc->parent_map_data);
207 mv_cp110_icu_detach(device_t dev)
214 mv_cp110_icu_activate_intr(device_t dev, struct intr_irqsrc *isrc,
215 struct resource *res, struct intr_map_data *data)
217 struct mv_cp110_icu_softc *sc;
219 sc = device_get_softc(dev);
220 data = mv_cp110_icu_convert_map_data(sc, data);
223 return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data));
227 mv_cp110_icu_enable_intr(device_t dev, struct intr_irqsrc *isrc)
229 struct mv_cp110_icu_softc *sc;
230 sc = device_get_softc(dev);
232 PIC_ENABLE_INTR(sc->parent, isrc);
236 mv_cp110_icu_disable_intr(device_t dev, struct intr_irqsrc *isrc)
238 struct mv_cp110_icu_softc *sc;
240 sc = device_get_softc(dev);
242 PIC_DISABLE_INTR(sc->parent, isrc);
246 mv_cp110_icu_init(struct mv_cp110_icu_softc *sc, uint64_t addr)
254 WR4(sc, ICU_SETSPI_NSR_AL, addr & UINT32_MAX);
255 WR4(sc, ICU_SETSPI_NSR_AH, (addr >> 32) & UINT32_MAX);
256 addr += MV_CP110_ICU_CLRSPI_OFFSET;
257 WR4(sc, ICU_CLRSPI_NSR_AL, addr & UINT32_MAX);
258 WR4(sc, ICU_CLRSPI_NSR_AH, (addr >> 32) & UINT32_MAX);
261 WR4(sc, ICU_SETSPI_SEI_AL, addr & UINT32_MAX);
262 WR4(sc, ICU_SETSPI_SEI_AH, (addr >> 32) & UINT32_MAX);
265 panic("Unkown ICU type.");
268 sc->initialized = true;
272 mv_cp110_icu_map_intr(device_t dev, struct intr_map_data *data,
273 struct intr_irqsrc **isrcp)
275 struct mv_cp110_icu_softc *sc;
276 struct intr_map_data_fdt *daf;
277 uint32_t vector, irq_no, irq_type;
281 sc = device_get_softc(dev);
283 if (data->type != INTR_MAP_DATA_FDT)
287 daf = (struct intr_map_data_fdt *)data;
288 if (daf->ncells != 2)
291 irq_no = daf->cells[0];
292 if (irq_no >= MV_CP110_ICU_MAX_NIRQS)
295 irq_type = daf->cells[1];
296 if (irq_type != IRQ_TYPE_LEVEL_HIGH &&
297 irq_type != IRQ_TYPE_EDGE_RISING)
301 * Allocate MSI vector.
302 * We don't use intr_alloc_msi wrapper, since it registers a new irq
303 * in the kernel. In our case irq was already added by the ofw code.
305 ret = MSI_ALLOC_MSI(sc->parent, dev, 1, 1, NULL, isrcp);
309 ret = MSI_MAP_MSI(sc->parent, dev, *isrcp, &addr, &vector);
313 mv_cp110_icu_init(sc, addr);
314 vector |= ICU_INT_ENABLE;
316 if (sc->type == ICU_TYPE_NSR)
317 vector |= ICU_GRP_NSR << ICU_INT_GROUP_SHIFT;
319 vector |= ICU_GRP_SEI << ICU_INT_GROUP_SHIFT;
321 if (irq_type & IRQ_TYPE_EDGE_BOTH)
322 vector |= ICU_INT_EDGE;
324 WR4(sc, ICU_INT_CFG(irq_no), vector);
327 * SATA controller has two ports, each gets its own interrupt.
328 * The problem is that only one irq is described in dts.
329 * Also ahci_generic driver supports only one irq per controller.
330 * As a workaround map both interrupts when one of them is allocated.
331 * This allows us to use both SATA ports.
333 if (irq_no == ICU_INT_SATA0)
334 WR4(sc, ICU_INT_CFG(ICU_INT_SATA1), vector);
335 if (irq_no == ICU_INT_SATA1)
336 WR4(sc, ICU_INT_CFG(ICU_INT_SATA0), vector);
338 (*isrcp)->isrc_dev = sc->dev;
343 MSI_RELEASE_MSI(sc->parent, dev, 1, isrcp);
349 mv_cp110_icu_deactivate_intr(device_t dev, struct intr_irqsrc *isrc,
350 struct resource *res, struct intr_map_data *data)
352 struct mv_cp110_icu_softc *sc;
353 struct intr_map_data_fdt *daf;
356 if (data->type != INTR_MAP_DATA_FDT)
359 sc = device_get_softc(dev);
360 daf = (struct intr_map_data_fdt *)data;
361 if (daf->ncells != 2)
364 irq_no = daf->cells[0];
365 data = mv_cp110_icu_convert_map_data(sc, data);
369 /* Clear the mapping. */
370 WR4(sc, ICU_INT_CFG(irq_no), 0);
372 ret = PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data);
376 return (MSI_RELEASE_MSI(sc->parent, dev, 1, &isrc));
380 mv_cp110_icu_setup_intr(device_t dev, struct intr_irqsrc *isrc,
381 struct resource *res, struct intr_map_data *data)
383 struct mv_cp110_icu_softc *sc;
385 sc = device_get_softc(dev);
386 data = mv_cp110_icu_convert_map_data(sc, data);
390 return (PIC_SETUP_INTR(sc->parent, isrc, res, data));
394 mv_cp110_icu_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
395 struct resource *res, struct intr_map_data *data)
397 struct mv_cp110_icu_softc *sc;
399 sc = device_get_softc(dev);
400 data = mv_cp110_icu_convert_map_data(sc, data);
404 return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data));
408 mv_cp110_icu_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
410 struct mv_cp110_icu_softc *sc;
412 sc = device_get_softc(dev);
414 PIC_PRE_ITHREAD(sc->parent, isrc);
418 mv_cp110_icu_post_ithread(device_t dev, struct intr_irqsrc *isrc)
420 struct mv_cp110_icu_softc *sc;
422 sc = device_get_softc(dev);
424 PIC_POST_ITHREAD(sc->parent, isrc);
428 mv_cp110_icu_post_filter(device_t dev, struct intr_irqsrc *isrc)
430 struct mv_cp110_icu_softc *sc;
432 sc = device_get_softc(dev);
434 PIC_POST_FILTER(sc->parent, isrc);
437 static device_method_t mv_cp110_icu_methods[] = {
438 /* Device interface */
439 DEVMETHOD(device_probe, mv_cp110_icu_probe),
440 DEVMETHOD(device_attach, mv_cp110_icu_attach),
441 DEVMETHOD(device_detach, mv_cp110_icu_detach),
443 /* Interrupt controller interface */
444 DEVMETHOD(pic_activate_intr, mv_cp110_icu_activate_intr),
445 DEVMETHOD(pic_disable_intr, mv_cp110_icu_disable_intr),
446 DEVMETHOD(pic_enable_intr, mv_cp110_icu_enable_intr),
447 DEVMETHOD(pic_map_intr, mv_cp110_icu_map_intr),
448 DEVMETHOD(pic_deactivate_intr, mv_cp110_icu_deactivate_intr),
449 DEVMETHOD(pic_setup_intr, mv_cp110_icu_setup_intr),
450 DEVMETHOD(pic_teardown_intr, mv_cp110_icu_teardown_intr),
451 DEVMETHOD(pic_post_filter, mv_cp110_icu_post_filter),
452 DEVMETHOD(pic_post_ithread, mv_cp110_icu_post_ithread),
453 DEVMETHOD(pic_pre_ithread, mv_cp110_icu_pre_ithread),
458 static driver_t mv_cp110_icu_driver = {
460 mv_cp110_icu_methods,
461 sizeof(struct mv_cp110_icu_softc),
464 EARLY_DRIVER_MODULE(mv_cp110_icu, mv_cp110_icu_bus, mv_cp110_icu_driver, 0, 0,
465 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST);