2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
6 * This code is derived from software written for Brini by Mark Brinicombe
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
39 #include "opt_platform.h"
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #define _ARM32_BUS_DMA_PRIVATE
45 #include <sys/param.h>
46 #include <sys/systm.h>
48 #include <sys/devmap.h>
53 #include <machine/bus.h>
54 #include <machine/fdt.h>
55 #include <machine/machdep.h>
56 #include <machine/platform.h>
59 #include <machine/cpu-v4.h>
61 #include <machine/cpu-v6.h>
64 #include <arm/mv/mvreg.h> /* XXX */
65 #include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */
66 #include <arm/mv/mvwin.h>
68 #include <dev/fdt/fdt_common.h>
69 #include <dev/ofw/ofw_bus_subr.h>
71 static int platform_mpp_init(void);
72 #if defined(SOC_MV_ARMADAXP)
73 void armadaxp_init_coher_fabric(void);
74 void armadaxp_l2_init(void);
76 #if defined(SOC_MV_ARMADA38X)
77 int armada38x_win_set_iosync_barrier(void);
78 int armada38x_scu_enable(void);
79 int armada38x_open_bootrom_win(void);
80 int armada38x_mbus_optimization(void);
83 #define MPP_PIN_MAX 68
84 #define MPP_PIN_CELLS 2
85 #define MPP_PINS_PER_REG 8
86 #define MPP_SEL(pin,func) (((func) & 0xf) << \
87 (((pin) % MPP_PINS_PER_REG) * 4))
90 platform_mpp_init(void)
92 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS];
94 uint32_t ctrl_val, ctrl_offset;
98 pcell_t pin_cells, *pinmap_ptr, pin_count;
100 int par_addr_cells, par_size_cells;
101 int tuple_size, tuples, rv, pins, i, j;
102 int mpp_pin, mpp_function;
105 * Try to access the MPP node directly i.e. through /aliases/mpp.
107 if ((node = OF_finddevice("mpp")) != -1)
108 if (ofw_bus_node_is_compatible(node, "mrvl,mpp"))
111 * Find the node the long way.
113 if ((node = OF_finddevice("/")) == -1)
116 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0)
119 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0)
121 * No MPP node. Fall back to how MPP got set by the
122 * first-stage loader and try to continue booting.
127 * Process 'reg' prop.
129 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
130 &par_size_cells)) != 0)
133 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells);
134 len = OF_getprop(node, "reg", reg, sizeof(reg));
135 tuples = len / tuple_size;
140 * Get address/size. XXX we assume only the first 'reg' tuple is used.
142 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells,
146 start += fdt_immr_va;
149 * Process 'pin-count' and 'pin-map' props.
151 if (OF_getencprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0)
153 if (pin_count > MPP_PIN_MAX)
156 if (OF_getencprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0)
157 pin_cells = MPP_PIN_CELLS;
158 if (pin_cells > MPP_PIN_CELLS)
160 tuple_size = sizeof(pcell_t) * pin_cells;
162 bzero(pinmap, sizeof(pinmap));
163 len = OF_getencprop(node, "pin-map", pinmap, sizeof(pinmap));
166 if (len % tuple_size)
168 pins = len / tuple_size;
169 if (pins > pin_count)
172 * Fill out a "mpp[pin] => function" table. All pins unspecified in
173 * the 'pin-map' property are defaulted to 0 function i.e. GPIO.
175 bzero(mpp, sizeof(mpp));
177 for (i = 0; i < pins; i++) {
178 mpp_pin = *pinmap_ptr;
179 mpp_function = *(pinmap_ptr + 1);
180 mpp[mpp_pin] = mpp_function;
181 pinmap_ptr += pin_cells;
185 * Prepare and program MPP control register values.
188 for (i = 0; i < pin_count;) {
191 for (j = 0; j < MPP_PINS_PER_REG; j++) {
192 if (i + j == pin_count - 1)
194 ctrl_val |= MPP_SEL(i + j, mpp[i + j]);
196 i += MPP_PINS_PER_REG;
197 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset,
200 #if defined(SOC_MV_ORION)
202 * Third MPP reg on Orion SoC is placed
203 * non-linearly (with different offset).
205 if (i == (2 * MPP_PINS_PER_REG))
216 platform_lastaddr(void)
219 return (fdt_immr_va);
223 platform_probe_and_attach(void)
226 if (fdt_immr_addr(MV_BASE) != 0)
231 platform_gpio_init(void)
235 * Re-initialise MPP. It is important to call this prior to using
236 * console as the physical connection can be routed via MPP.
238 if (platform_mpp_init() != 0)
243 platform_late_init(void)
246 * Re-initialise decode windows
248 if (soc_decode_win() != 0)
249 printf("WARNING: could not re-initialise decode windows! "
250 "Running with existing settings...\n");
251 #if defined(SOC_MV_ARMADAXP)
253 /* For SMP case it should be initialized after APs are booted */
254 armadaxp_init_coher_fabric();
259 #if defined(SOC_MV_ARMADA38X)
260 /* Set IO Sync Barrier bit for all Mbus devices */
261 if (armada38x_win_set_iosync_barrier() != 0)
262 printf("WARNING: could not map CPU Subsystem registers\n");
263 if (armada38x_mbus_optimization() != 0)
264 printf("WARNING: could not enable mbus optimization\n");
265 if (armada38x_scu_enable() != 0)
266 printf("WARNING: could not enable SCU\n");
268 /* Open window to bootROM memory - needed for SMP */
269 if (armada38x_open_bootrom_win() != 0)
270 printf("WARNING: could not open window to bootROM\n");
275 #define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2)
276 static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
281 platform_sram_devmap(struct devmap_entry *map)
283 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
284 phandle_t child, root;
289 if ((child = OF_finddevice("/sram")) != 0)
290 if (ofw_bus_node_is_compatible(child, "mrvl,cesa-sram") ||
291 ofw_bus_node_is_compatible(child, "mrvl,scratchpad"))
294 if ((root = OF_finddevice("/")) == 0)
297 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 &&
298 (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0)
302 if (fdt_regsize(child, &base, &size) != 0)
305 map->pd_va = MV_CESA_SRAM_BASE; /* XXX */
317 * Supply a default do-nothing implementation of mv_pci_devmap() via a weak
318 * alias. Many Marvell platforms don't support a PCI interface, but to support
319 * those that do, we end up with a reference to this function below, in
320 * platform_devmap_init(). If "device pci" appears in the kernel config, the
321 * real implementation of this function in arm/mv/mv_pci.c overrides the weak
322 * alias defined here.
324 int mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap,
325 vm_offset_t io_va, vm_offset_t mem_va);
327 mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap,
328 vm_offset_t io_va, vm_offset_t mem_va)
333 __weak_reference(mv_default_fdt_pci_devmap, mv_pci_devmap);
336 * XXX: When device entry in devmap has pd_size smaller than section size,
337 * system will freeze during initialization
341 * Construct devmap table with DT-derived config data.
344 platform_devmap_init(void)
346 phandle_t root, child;
351 devmap_register_table(&fdt_devmap[0]);
353 #ifdef SOC_MV_ARMADAXP
354 vm_paddr_t cur_immr_pa;
357 * Acquire SoC registers' base passed by u-boot and fill devmap
358 * accordingly. DTB is going to be modified basing on this data
361 __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa));
362 cur_immr_pa = (cur_immr_pa << 13) & 0xff000000;
363 if (cur_immr_pa != 0)
364 fdt_immr_pa = cur_immr_pa;
369 fdt_devmap[i].pd_va = fdt_immr_va;
370 fdt_devmap[i].pd_pa = fdt_immr_pa;
371 fdt_devmap[i].pd_size = fdt_immr_size;
377 if (i < FDT_DEVMAP_MAX)
378 if (platform_sram_devmap(&fdt_devmap[i]) == 0)
383 * PCI range(s) and localbus.
385 if ((root = OF_finddevice("/")) == -1)
387 for (child = OF_child(root); child != 0; child = OF_peer(child)) {
388 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) {
390 * Check space: each PCI node will consume 2 devmap
393 if (i + 1 >= FDT_DEVMAP_MAX)
397 * XXX this should account for PCI and multiple ranges
400 if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE,
401 MV_PCI_VA_MEM_BASE) != 0)
406 if (ofw_bus_node_is_compatible(child, "mrvl,lbc")) {
407 /* Check available space */
408 if (OF_getencprop(child, "bank-count", &bank_count,
409 sizeof(bank_count)) <= 0)
410 /* If no property, use default value */
413 if ((i + bank_count) >= FDT_DEVMAP_MAX)
416 /* Add all localbus ranges to device map */
419 if (fdt_localbus_devmap(child, &fdt_devmap[i],
420 (int)bank_count, &num_mapped) != 0)
431 struct arm32_dma_range *
432 bus_dma_get_range(void)
439 bus_dma_get_range_nb(void)
446 #if defined(CPU_MV_PJ4B)
450 DB_SHOW_COMMAND(cp15, db_show_cp15)
454 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg));
455 db_printf("Cpu ID: 0x%08x\n", reg);
456 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg));
457 db_printf("Current Cache Lvl ID: 0x%08x\n",reg);
459 reg = cp15_sctlr_get();
460 db_printf("Ctrl: 0x%08x\n",reg);
461 reg = cp15_actlr_get();
462 db_printf("Aux Ctrl: 0x%08x\n",reg);
464 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg));
465 db_printf("Processor Feat 0: 0x%08x\n", reg);
466 __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg));
467 db_printf("Processor Feat 1: 0x%08x\n", reg);
468 __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg));
469 db_printf("Debug Feat 0: 0x%08x\n", reg);
470 __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg));
471 db_printf("Auxiliary Feat 0: 0x%08x\n", reg);
472 __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg));
473 db_printf("Memory Model Feat 0: 0x%08x\n", reg);
474 __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg));
475 db_printf("Memory Model Feat 1: 0x%08x\n", reg);
476 __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg));
477 db_printf("Memory Model Feat 2: 0x%08x\n", reg);
478 __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg));
479 db_printf("Memory Model Feat 3: 0x%08x\n", reg);
481 __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg));
482 db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg);
483 __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg));
484 db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg);
486 __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg));
487 db_printf("CPU ID code extension: 0x%08x\n",reg);
490 DB_SHOW_COMMAND(vtop, db_show_vtop)
495 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr));
496 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg));
497 db_printf("Physical address reg: 0x%08x\n",reg);
499 db_printf("show vtop <virt_addr>\n");
502 #endif /* CPU_MV_PJ4B */