2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
6 * This code is derived from software written for Brini by Mark Brinicombe
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
39 #include "opt_platform.h"
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #define _ARM32_BUS_DMA_PRIVATE
45 #include <sys/param.h>
46 #include <sys/systm.h>
52 #include <machine/bus.h>
53 #include <machine/devmap.h>
54 #include <machine/fdt.h>
55 #include <machine/machdep.h>
56 #include <machine/platform.h>
58 #include <arm/mv/mvreg.h> /* XXX */
59 #include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */
60 #include <arm/mv/mvwin.h>
62 #include <dev/fdt/fdt_common.h>
64 static int platform_mpp_init(void);
65 #if defined(SOC_MV_ARMADAXP)
66 void armadaxp_init_coher_fabric(void);
67 void armadaxp_l2_init(void);
70 #define MPP_PIN_MAX 68
71 #define MPP_PIN_CELLS 2
72 #define MPP_PINS_PER_REG 8
73 #define MPP_SEL(pin,func) (((func) & 0xf) << \
74 (((pin) % MPP_PINS_PER_REG) * 4))
77 platform_mpp_init(void)
79 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS];
81 uint32_t ctrl_val, ctrl_offset;
85 pcell_t pin_cells, *pinmap_ptr, pin_count;
87 int par_addr_cells, par_size_cells;
88 int tuple_size, tuples, rv, pins, i, j;
89 int mpp_pin, mpp_function;
92 * Try to access the MPP node directly i.e. through /aliases/mpp.
94 if ((node = OF_finddevice("mpp")) != -1)
95 if (fdt_is_compatible(node, "mrvl,mpp"))
98 * Find the node the long way.
100 if ((node = OF_finddevice("/")) == -1)
103 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0)
106 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0)
108 * No MPP node. Fall back to how MPP got set by the
109 * first-stage loader and try to continue booting.
114 * Process 'reg' prop.
116 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
117 &par_size_cells)) != 0)
120 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells);
121 len = OF_getprop(node, "reg", reg, sizeof(reg));
122 tuples = len / tuple_size;
127 * Get address/size. XXX we assume only the first 'reg' tuple is used.
129 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells,
133 start += fdt_immr_va;
136 * Process 'pin-count' and 'pin-map' props.
138 if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0)
140 pin_count = fdt32_to_cpu(pin_count);
141 if (pin_count > MPP_PIN_MAX)
144 if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0)
145 pin_cells = MPP_PIN_CELLS;
146 pin_cells = fdt32_to_cpu(pin_cells);
147 if (pin_cells > MPP_PIN_CELLS)
149 tuple_size = sizeof(pcell_t) * pin_cells;
151 bzero(pinmap, sizeof(pinmap));
152 len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap));
155 if (len % tuple_size)
157 pins = len / tuple_size;
158 if (pins > pin_count)
161 * Fill out a "mpp[pin] => function" table. All pins unspecified in
162 * the 'pin-map' property are defaulted to 0 function i.e. GPIO.
164 bzero(mpp, sizeof(mpp));
166 for (i = 0; i < pins; i++) {
167 mpp_pin = fdt32_to_cpu(*pinmap_ptr);
168 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1));
169 mpp[mpp_pin] = mpp_function;
170 pinmap_ptr += pin_cells;
174 * Prepare and program MPP control register values.
177 for (i = 0; i < pin_count;) {
180 for (j = 0; j < MPP_PINS_PER_REG; j++) {
181 if (i + j == pin_count - 1)
183 ctrl_val |= MPP_SEL(i + j, mpp[i + j]);
185 i += MPP_PINS_PER_REG;
186 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset,
189 #if defined(SOC_MV_ORION)
191 * Third MPP reg on Orion SoC is placed
192 * non-linearly (with different offset).
194 if (i == (2 * MPP_PINS_PER_REG))
205 platform_lastaddr(void)
208 return (fdt_immr_va);
212 platform_probe_and_attach(void)
215 if (fdt_immr_addr(MV_BASE) != 0)
220 platform_gpio_init(void)
224 * Re-initialise MPP. It is important to call this prior to using
225 * console as the physical connection can be routed via MPP.
227 if (platform_mpp_init() != 0)
232 platform_late_init(void)
235 * Re-initialise decode windows
237 #if !defined(SOC_MV_FREY)
238 if (soc_decode_win() != 0)
239 printf("WARNING: could not re-initialise decode windows! "
240 "Running with existing settings...\n");
242 /* Disable watchdog and timers */
243 write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0);
245 #if defined(SOC_MV_ARMADAXP)
247 /* For SMP case it should be initialized after APs are booted */
248 armadaxp_init_coher_fabric();
254 #define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2)
255 static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
260 platform_sram_devmap(struct arm_devmap_entry *map)
262 #if !defined(SOC_MV_ARMADAXP)
263 phandle_t child, root;
268 if ((child = OF_finddevice("/sram")) != 0)
269 if (fdt_is_compatible(child, "mrvl,cesa-sram") ||
270 fdt_is_compatible(child, "mrvl,scratchpad"))
273 if ((root = OF_finddevice("/")) == 0)
276 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 &&
277 (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0)
281 if (fdt_regsize(child, &base, &size) != 0)
284 map->pd_va = MV_CESA_SRAM_BASE; /* XXX */
287 map->pd_prot = VM_PROT_READ | VM_PROT_WRITE;
288 map->pd_cache = PTE_DEVICE;
298 * Supply a default do-nothing implementation of mv_pci_devmap() via a weak
299 * alias. Many Marvell platforms don't support a PCI interface, but to support
300 * those that do, we end up with a reference to this function below, in
301 * platform_devmap_init(). If "device pci" appears in the kernel config, the
302 * real implementation of this function in arm/mv/mv_pci.c overrides the weak
303 * alias defined here.
305 int mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap,
306 vm_offset_t io_va, vm_offset_t mem_va);
308 mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap,
309 vm_offset_t io_va, vm_offset_t mem_va)
314 __weak_reference(mv_default_fdt_pci_devmap, mv_pci_devmap);
317 * XXX: When device entry in devmap has pd_size smaller than section size,
318 * system will freeze during initialization
322 * Construct pmap_devmap[] with DT-derived config data.
325 platform_devmap_init(void)
327 phandle_t root, child;
332 arm_devmap_register_table(&fdt_devmap[0]);
334 #ifdef SOC_MV_ARMADAXP
335 vm_paddr_t cur_immr_pa;
338 * Acquire SoC registers' base passed by u-boot and fill devmap
339 * accordingly. DTB is going to be modified basing on this data
342 __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa));
343 cur_immr_pa = (cur_immr_pa << 13) & 0xff000000;
344 if (cur_immr_pa != 0)
345 fdt_immr_pa = cur_immr_pa;
350 fdt_devmap[i].pd_va = fdt_immr_va;
351 fdt_devmap[i].pd_pa = fdt_immr_pa;
352 fdt_devmap[i].pd_size = fdt_immr_size;
353 fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
354 fdt_devmap[i].pd_cache = PTE_DEVICE;
360 if (i < FDT_DEVMAP_MAX)
361 if (platform_sram_devmap(&fdt_devmap[i]) == 0)
366 * PCI range(s) and localbus.
368 if ((root = OF_finddevice("/")) == -1)
370 for (child = OF_child(root); child != 0; child = OF_peer(child)) {
371 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) {
373 * Check space: each PCI node will consume 2 devmap
376 if (i + 1 >= FDT_DEVMAP_MAX)
380 * XXX this should account for PCI and multiple ranges
383 if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE,
384 MV_PCI_VA_MEM_BASE) != 0)
389 if (fdt_is_compatible(child, "mrvl,lbc")) {
390 /* Check available space */
391 if (OF_getprop(child, "bank-count", (void *)&bank_count,
392 sizeof(bank_count)) <= 0)
393 /* If no property, use default value */
396 bank_count = fdt32_to_cpu(bank_count);
398 if ((i + bank_count) >= FDT_DEVMAP_MAX)
401 /* Add all localbus ranges to device map */
404 if (fdt_localbus_devmap(child, &fdt_devmap[i],
405 (int)bank_count, &num_mapped) != 0)
415 struct arm32_dma_range *
416 bus_dma_get_range(void)
423 bus_dma_get_range_nb(void)
429 #if defined(CPU_MV_PJ4B)
433 DB_SHOW_COMMAND(cp15, db_show_cp15)
437 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg));
438 db_printf("Cpu ID: 0x%08x\n", reg);
439 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg));
440 db_printf("Current Cache Lvl ID: 0x%08x\n",reg);
442 __asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg));
443 db_printf("Ctrl: 0x%08x\n",reg);
444 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg));
445 db_printf("Aux Ctrl: 0x%08x\n",reg);
447 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg));
448 db_printf("Processor Feat 0: 0x%08x\n", reg);
449 __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg));
450 db_printf("Processor Feat 1: 0x%08x\n", reg);
451 __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg));
452 db_printf("Debug Feat 0: 0x%08x\n", reg);
453 __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg));
454 db_printf("Auxiliary Feat 0: 0x%08x\n", reg);
455 __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg));
456 db_printf("Memory Model Feat 0: 0x%08x\n", reg);
457 __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg));
458 db_printf("Memory Model Feat 1: 0x%08x\n", reg);
459 __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg));
460 db_printf("Memory Model Feat 2: 0x%08x\n", reg);
461 __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg));
462 db_printf("Memory Model Feat 3: 0x%08x\n", reg);
464 __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg));
465 db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg);
466 __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg));
467 db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg);
469 __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg));
470 db_printf("CPU ID code extension: 0x%08x\n",reg);
473 DB_SHOW_COMMAND(vtop, db_show_vtop)
478 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr));
479 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg));
480 db_printf("Physical address reg: 0x%08x\n",reg);
482 db_printf("show vtop <virt_addr>\n");
485 #endif /* CPU_MV_PJ4B */