2 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
3 * Copyright (c) 2010 The FreeBSD Foundation
4 * Copyright (c) 2010-2015 Semihalf
7 * Developed by Semihalf.
9 * Portions of this software were developed by Semihalf
10 * under sponsorship from the FreeBSD Foundation.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of MARVELL nor the names of contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * Marvell integrated PCI/PCI-Express controller driver.
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/kernel.h>
48 #include <sys/malloc.h>
49 #include <sys/module.h>
50 #include <sys/mutex.h>
51 #include <sys/queue.h>
54 #include <sys/endian.h>
55 #include <sys/devmap.h>
57 #include <machine/fdt.h>
58 #include <machine/intr.h>
63 #include <dev/fdt/fdt_common.h>
64 #include <dev/ofw/ofw_bus.h>
65 #include <dev/ofw/ofw_bus_subr.h>
66 #include <dev/ofw/ofw_pci.h>
67 #include <dev/pci/pcivar.h>
68 #include <dev/pci/pcireg.h>
69 #include <dev/pci/pcib_private.h>
71 #include "ofw_bus_if.h"
74 #include <machine/resource.h>
75 #include <machine/bus.h>
77 #include <arm/mv/mvreg.h>
78 #include <arm/mv/mvvar.h>
79 #include <arm/mv/mvwin.h>
82 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
84 #define debugf(fmt, args...)
88 * Code and data related to fdt-based PCI configuration.
90 * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was
91 * always Marvell-specific so that was deleted and the code now lives here.
100 #define FDT_RANGES_CELLS ((3 + 3 + 2) * 2)
103 mv_pci_range_dump(struct mv_pci_range *range)
107 printf(" base_pci = 0x%08lx\n", range->base_pci);
108 printf(" base_par = 0x%08lx\n", range->base_parent);
109 printf(" len = 0x%08lx\n", range->len);
114 mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space,
115 struct mv_pci_range *mem_space)
117 pcell_t ranges[FDT_RANGES_CELLS];
118 struct mv_pci_range *pci_space;
119 pcell_t addr_cells, size_cells, par_addr_cells;
121 pcell_t cell0, cell1, cell2;
122 int tuple_size, tuples, i, rv, offset_cells, len;
125 * Retrieve 'ranges' property.
127 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
129 if (addr_cells != 3 || size_cells != 2)
132 par_addr_cells = fdt_parent_addr_cells(node);
133 if (par_addr_cells > 3)
136 len = OF_getproplen(node, "ranges");
137 if (len > sizeof(ranges))
140 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
143 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
145 tuples = len / tuple_size;
148 * Initialize the ranges so that we don't have to worry about
149 * having them all defined in the FDT. In particular, it is
150 * perfectly fine not to want I/O space on PCI buses.
152 bzero(io_space, sizeof(*io_space));
153 bzero(mem_space, sizeof(*mem_space));
155 rangesptr = &ranges[0];
157 for (i = 0; i < tuples; i++) {
158 cell0 = fdt_data_get((void *)rangesptr, 1);
160 cell1 = fdt_data_get((void *)rangesptr, 1);
162 cell2 = fdt_data_get((void *)rangesptr, 1);
165 if (cell0 & 0x02000000) {
166 pci_space = mem_space;
167 } else if (cell0 & 0x01000000) {
168 pci_space = io_space;
174 if (par_addr_cells == 3) {
176 * This is a PCI subnode 'ranges'. Skip cell0 and
177 * cell1 of this entry and only use cell2.
180 rangesptr += offset_cells;
183 if ((par_addr_cells - offset_cells) > 2) {
187 pci_space->base_parent = fdt_data_get((void *)rangesptr,
188 par_addr_cells - offset_cells);
189 rangesptr += par_addr_cells - offset_cells;
191 if (size_cells > 2) {
195 pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
196 rangesptr += size_cells;
198 pci_space->base_pci = cell2;
206 mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space,
207 struct mv_pci_range *mem_space)
211 debugf("Processing PCI node: %x\n", node);
212 if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) {
213 debugf("could not decode parent PCI node 'ranges'\n");
217 debugf("Post fixup dump:\n");
218 mv_pci_range_dump(io_space);
219 mv_pci_range_dump(mem_space);
224 mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va,
227 struct mv_pci_range io_space, mem_space;
230 if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0)
233 devmap->pd_va = (io_va ? io_va : io_space.base_parent);
234 devmap->pd_pa = io_space.base_parent;
235 devmap->pd_size = io_space.len;
238 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent);
239 devmap->pd_pa = mem_space.base_parent;
240 devmap->pd_size = mem_space.len;
245 * Code and data related to the Marvell pcib driver.
248 #define PCI_CFG_ENA (1U << 31)
249 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
250 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
251 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8)
252 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc)
254 #define PCI_REG_CFG_ADDR 0x0C78
255 #define PCI_REG_CFG_DATA 0x0C7C
257 #define PCIE_REG_CFG_ADDR 0x18F8
258 #define PCIE_REG_CFG_DATA 0x18FC
259 #define PCIE_REG_CONTROL 0x1A00
260 #define PCIE_CTRL_LINK1X 0x00000001
261 #define PCIE_REG_STATUS 0x1A04
262 #define PCIE_REG_IRQ_MASK 0x1910
264 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1)
265 #define PCIE_CONTROL_HOT_RESET (1 << 24)
267 #define PCIE_LINK_TIMEOUT 1000000
269 #define PCIE_STATUS_LINK_DOWN 1
270 #define PCIE_STATUS_DEV_OFFS 16
272 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */
273 #define PCI_MIN_IO_ALLOC 4
274 #define PCI_MIN_MEM_ALLOC 16
276 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t))
278 struct mv_pcib_softc {
281 struct rman sc_mem_rman;
282 bus_addr_t sc_mem_base;
283 bus_addr_t sc_mem_size;
284 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE /
285 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
289 struct rman sc_io_rman;
290 bus_addr_t sc_io_base;
291 bus_addr_t sc_io_size;
292 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE /
293 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
296 struct resource *sc_res;
297 bus_space_handle_t sc_bsh;
298 bus_space_tag_t sc_bst;
301 struct mtx sc_msi_mtx;
302 uint32_t sc_msi_bitmap;
304 int sc_busnr; /* Host bridge bus number */
305 int sc_devnr; /* Host bridge device number */
307 int sc_mode; /* Endpoint / Root Complex */
309 struct ofw_bus_iinfo sc_pci_iinfo;
312 /* Local forward prototypes */
313 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *);
314 static void mv_pcib_hw_cfginit(void);
315 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int,
317 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int,
318 u_int, u_int, uint32_t, int);
319 static int mv_pcib_init(struct mv_pcib_softc *, int, int);
320 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
321 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
322 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
323 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t);
324 static int mv_pcib_mem_init(struct mv_pcib_softc *);
326 /* Forward prototypes */
327 static int mv_pcib_probe(device_t);
328 static int mv_pcib_attach(device_t);
330 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
331 rman_res_t, rman_res_t, rman_res_t, u_int);
332 static int mv_pcib_release_resource(device_t, device_t, int, int,
334 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
335 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
337 static int mv_pcib_maxslots(device_t);
338 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
339 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
341 static int mv_pcib_route_interrupt(device_t, device_t, int);
342 #if defined(SOC_MV_ARMADAXP)
343 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *);
344 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
345 static int mv_pcib_release_msi(device_t, device_t, int, int *);
349 * Bus interface definitions.
351 static device_method_t mv_pcib_methods[] = {
352 /* Device interface */
353 DEVMETHOD(device_probe, mv_pcib_probe),
354 DEVMETHOD(device_attach, mv_pcib_attach),
357 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar),
358 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar),
359 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource),
360 DEVMETHOD(bus_release_resource, mv_pcib_release_resource),
361 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
362 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
363 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
364 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
367 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots),
368 DEVMETHOD(pcib_read_config, mv_pcib_read_config),
369 DEVMETHOD(pcib_write_config, mv_pcib_write_config),
370 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt),
371 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
372 #if defined(SOC_MV_ARMADAXP)
373 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi),
374 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi),
375 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi),
378 /* OFW bus interface */
379 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
380 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
381 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
382 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
383 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
388 static driver_t mv_pcib_driver = {
391 sizeof(struct mv_pcib_softc),
394 devclass_t pcib_devclass;
396 DRIVER_MODULE(pcib, ofwbus, mv_pcib_driver, pcib_devclass, 0, 0);
397 DRIVER_MODULE(pcib, pcib_ctrl, mv_pcib_driver, pcib_devclass, 0, 0);
399 static struct mtx pcicfg_mtx;
402 mv_pcib_probe(device_t self)
406 node = ofw_bus_get_node(self);
407 if (!fdt_is_type(node, "pci"))
410 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") ||
411 ofw_bus_is_compatible(self, "mrvl,pci")))
414 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
415 return (BUS_PROBE_DEFAULT);
419 mv_pcib_attach(device_t self)
421 struct mv_pcib_softc *sc;
422 phandle_t node, parnode;
424 int err, bus, devfn, port_id;
426 sc = device_get_softc(self);
429 node = ofw_bus_get_node(self);
430 parnode = OF_parent(node);
432 if (OF_getencprop(node, "marvell,pcie-port", &(port_id),
433 sizeof(port_id)) <= 0) {
434 /* If port ID does not exist in the FDT set value to 0 */
435 if (!OF_hasprop(node, "marvell,pcie-port"))
441 if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) {
442 sc->sc_type = MV_TYPE_PCIE;
443 sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id);
444 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id);
445 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id);
446 } else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) {
447 sc->sc_type = MV_TYPE_PCI;
448 sc->sc_win_target = MV_WIN_PCI_TARGET;
449 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
450 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
455 * Retrieve our mem-mapped registers range.
458 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
460 if (sc->sc_res == NULL) {
461 device_printf(self, "could not map memory\n");
464 sc->sc_bst = rman_get_bustag(sc->sc_res);
465 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
467 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL);
468 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT :
472 * Get PCI interrupt info.
474 if (sc->sc_mode == MV_MODE_ROOT)
475 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t));
478 * Configure decode windows for PCI(E) access.
480 if (mv_pcib_decode_win(node, sc) != 0)
483 mv_pcib_hw_cfginit();
486 * Enable PCIE device.
488 mv_pcib_enable(sc, port_id);
493 err = mv_pcib_mem_init(sc);
498 * Preliminary bus enumeration to find first linked devices and set
499 * appropriate bus number from which should start the actual enumeration
501 for (bus = 0; bus < PCI_BUSMAX; bus++) {
502 for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) {
503 reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4);
505 continue; /* no device */
507 sc->sc_busnr = bus; /* update bus number */
513 if (sc->sc_mode == MV_MODE_ROOT) {
514 err = mv_pcib_init(sc, sc->sc_busnr,
515 mv_pcib_maxslots(sc->sc_dev));
519 device_add_child(self, "pci", -1);
522 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
523 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS);
524 device_add_child(self, "pci_ep", -1);
527 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF);
528 return (bus_generic_attach(self));
531 /* XXX SYS_RES_ should be released here */
532 rman_fini(&sc->sc_mem_rman);
533 rman_fini(&sc->sc_io_rman);
539 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit)
542 #if !defined(SOC_MV_ARMADAXP)
546 * Check if PCIE device is enabled.
548 if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) {
549 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) &
550 ~(CPU_CONTROL_PCIE_DISABLE(unit)));
552 timeout = PCIE_LINK_TIMEOUT;
553 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
555 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) {
558 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
565 if (sc->sc_mode == MV_MODE_ROOT) {
569 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND);
570 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN |
571 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
572 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val);
577 mv_pcib_mem_init(struct mv_pcib_softc *sc)
584 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
585 err = rman_init(&sc->sc_mem_rman);
589 sc->sc_io_rman.rm_type = RMAN_ARRAY;
590 err = rman_init(&sc->sc_io_rman);
592 rman_fini(&sc->sc_mem_rman);
596 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
597 sc->sc_mem_base + sc->sc_mem_size - 1);
601 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
602 sc->sc_io_base + sc->sc_io_size - 1);
609 rman_fini(&sc->sc_mem_rman);
610 rman_fini(&sc->sc_io_rman);
615 static inline uint32_t
616 pcib_bit_get(uint32_t *map, uint32_t bit)
618 uint32_t n = bit / BITS_PER_UINT32;
620 bit = bit % BITS_PER_UINT32;
621 return (map[n] & (1 << bit));
625 pcib_bit_set(uint32_t *map, uint32_t bit)
627 uint32_t n = bit / BITS_PER_UINT32;
629 bit = bit % BITS_PER_UINT32;
630 map[n] |= (1 << bit);
633 static inline uint32_t
634 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
638 for (i = start; i < start + bits; i++)
639 if (pcib_bit_get(map, i))
646 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
650 for (i = start; i < start + bits; i++)
651 pcib_bit_set(map, i);
655 * The idea of this allocator is taken from ARM No-Cache memory
656 * management code (sys/arm/arm/vm_machdep.c).
659 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask)
661 uint32_t bits, bits_limit, i, *map, min_alloc, size;
666 base = sc->sc_io_base;
667 min_alloc = PCI_MIN_IO_ALLOC;
668 bits_limit = sc->sc_io_size / min_alloc;
672 base = sc->sc_mem_base;
673 min_alloc = PCI_MIN_MEM_ALLOC;
674 bits_limit = sc->sc_mem_size / min_alloc;
675 map = sc->sc_mem_map;
680 bits = size / min_alloc;
682 for (i = 0; i + bits <= bits_limit; i += bits)
683 if (pcib_map_check(map, i, bits)) {
684 pcib_map_set(map, i, bits);
685 addr = base + (i * min_alloc);
693 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
699 reg = PCIR_BAR(barno);
702 * Need to init the BAR register with 0xffffffff before correct
705 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
706 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
710 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
711 width = ((bar & 7) == 4) ? 2 : 1;
713 addr = pcib_alloc(sc, bar);
718 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
719 bus, slot, func, reg, bar, addr);
721 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
723 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
730 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func)
732 bus_addr_t io_base, mem_base;
733 uint32_t io_limit, mem_limit;
736 io_base = sc->sc_io_base;
737 io_limit = io_base + sc->sc_io_size - 1;
738 mem_base = sc->sc_mem_base;
739 mem_limit = mem_base + sc->sc_mem_size - 1;
741 /* Configure I/O decode registers */
742 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
744 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
746 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
748 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
751 /* Configure memory decode registers */
752 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
754 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
757 /* Disable memory prefetch decode */
758 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
760 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
762 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
764 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
767 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
770 /* Configure buses behind the bridge */
771 mv_pcib_init(sc, secbus, PCI_SLOTMAX);
775 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot)
777 int slot, func, maxfunc, error;
778 uint8_t hdrtype, command, class, subclass;
780 for (slot = 0; slot <= maxslot; slot++) {
782 for (func = 0; func <= maxfunc; func++) {
783 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
784 func, PCIR_HDRTYPE, 1);
786 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
789 if (func == 0 && (hdrtype & PCIM_MFDEV))
790 maxfunc = PCI_FUNCMAX;
792 command = mv_pcib_read_config(sc->sc_dev, bus, slot,
793 func, PCIR_COMMAND, 1);
794 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
795 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
796 PCIR_COMMAND, command, 1);
798 error = mv_pcib_init_all_bars(sc, bus, slot, func,
804 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
806 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
807 PCIR_COMMAND, command, 1);
809 /* Handle PCI-PCI bridges */
810 class = mv_pcib_read_config(sc->sc_dev, bus, slot,
811 func, PCIR_CLASS, 1);
812 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
813 func, PCIR_SUBCLASS, 1);
815 if (class != PCIC_BRIDGE ||
816 subclass != PCIS_BRIDGE_PCI)
819 mv_pcib_init_bridge(sc, bus, slot, func);
823 /* Enable all ABCD interrupts */
824 pcib_write_irq_mask(sc, (0xF << 24));
830 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
831 int func, int hdrtype)
835 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
838 /* Program the base address registers */
839 while (bar < maxbar) {
840 i = mv_pcib_init_bar(sc, bus, slot, func, bar);
843 device_printf(sc->sc_dev,
844 "PCI IO/Memory space exhausted\n");
852 static struct resource *
853 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
854 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
856 struct mv_pcib_softc *sc = device_get_softc(dev);
857 struct rman *rm = NULL;
858 struct resource *res;
862 rm = &sc->sc_io_rman;
865 rm = &sc->sc_mem_rman;
868 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
869 type, rid, start, end, count, flags));
872 if (RMAN_IS_DEFAULT_RANGE(start, end)) {
873 start = sc->sc_mem_base;
874 end = sc->sc_mem_base + sc->sc_mem_size - 1;
875 count = sc->sc_mem_size;
878 if ((start < sc->sc_mem_base) || (start + count - 1 != end) ||
879 (end > sc->sc_mem_base + sc->sc_mem_size - 1))
882 res = rman_reserve_resource(rm, start, end, count, flags, child);
886 rman_set_rid(res, *rid);
887 rman_set_bustag(res, fdtbus_bs_tag);
888 rman_set_bushandle(res, start);
890 if (flags & RF_ACTIVE)
891 if (bus_activate_resource(child, type, *rid, res)) {
892 rman_release_resource(res);
900 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid,
901 struct resource *res)
904 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY)
905 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
908 return (rman_release_resource(res));
912 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
914 struct mv_pcib_softc *sc = device_get_softc(dev);
918 *result = sc->sc_busnr;
920 case PCIB_IVAR_DOMAIN:
921 *result = device_get_unit(dev);
929 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
931 struct mv_pcib_softc *sc = device_get_softc(dev);
935 sc->sc_busnr = value;
943 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
946 if (sc->sc_type != MV_TYPE_PCIE)
949 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
953 mv_pcib_hw_cfginit(void)
955 static int opened = 0;
960 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
965 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot,
966 u_int func, u_int reg, int bytes)
968 uint32_t addr, data, ca, cd;
970 ca = (sc->sc_type != MV_TYPE_PCI) ?
971 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
972 cd = (sc->sc_type != MV_TYPE_PCI) ?
973 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
974 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
975 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
977 mtx_lock_spin(&pcicfg_mtx);
978 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
983 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
987 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
991 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
995 mtx_unlock_spin(&pcicfg_mtx);
1000 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot,
1001 u_int func, u_int reg, uint32_t data, int bytes)
1003 uint32_t addr, ca, cd;
1005 ca = (sc->sc_type != MV_TYPE_PCI) ?
1006 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
1007 cd = (sc->sc_type != MV_TYPE_PCI) ?
1008 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
1009 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
1010 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
1012 mtx_lock_spin(&pcicfg_mtx);
1013 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
1017 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
1018 cd + (reg & 3), data);
1021 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
1022 cd + (reg & 2), htole16(data));
1025 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
1029 mtx_unlock_spin(&pcicfg_mtx);
1033 mv_pcib_maxslots(device_t dev)
1035 struct mv_pcib_softc *sc = device_get_softc(dev);
1037 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
1041 mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func)
1043 #if defined(SOC_MV_ARMADA38X)
1044 struct mv_pcib_softc *sc = device_get_softc(dev);
1045 uint32_t vendor, device;
1047 vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR,
1048 PCIR_VENDOR_LENGTH);
1049 device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE,
1050 PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK;
1052 return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X);
1054 /* On platforms other than Armada38x, root link is always at slot 0 */
1060 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
1061 u_int reg, int bytes)
1063 struct mv_pcib_softc *sc = device_get_softc(dev);
1065 /* Return ~0 if link is inactive or trying to read from Root */
1066 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
1067 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
1070 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
1074 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
1075 u_int reg, uint32_t val, int bytes)
1077 struct mv_pcib_softc *sc = device_get_softc(dev);
1079 /* Return if link is inactive or trying to write to Root */
1080 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
1081 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
1084 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
1088 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin)
1090 struct mv_pcib_softc *sc;
1091 struct ofw_pci_register reg;
1092 uint32_t pintr, mintr[4];
1096 sc = device_get_softc(bus);
1099 /* Fabricate imap information in case this isn't an OFW device */
1100 bzero(®, sizeof(reg));
1101 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
1102 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
1103 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
1105 icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1106 ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr),
1109 return (ofw_bus_map_intr(dev, iparent, icells, mintr));
1111 /* Maybe it's a real interrupt, not an intpin */
1115 device_printf(bus, "could not route pin %d for device %d.%d\n",
1116 pin, pci_get_slot(dev), pci_get_function(dev));
1117 return (PCI_INVALID_IRQ);
1121 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
1123 struct mv_pci_range io_space, mem_space;
1129 if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) {
1130 device_printf(dev, "could not retrieve 'ranges' data\n");
1134 /* Configure CPU decoding windows */
1135 error = decode_win_cpu_set(sc->sc_win_target,
1136 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0);
1138 device_printf(dev, "could not set up CPU decode "
1139 "window for PCI IO\n");
1142 error = decode_win_cpu_set(sc->sc_win_target,
1143 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len,
1144 mem_space.base_parent);
1146 device_printf(dev, "could not set up CPU decode "
1147 "windows for PCI MEM\n");
1151 sc->sc_io_base = io_space.base_parent;
1152 sc->sc_io_size = io_space.len;
1154 sc->sc_mem_base = mem_space.base_parent;
1155 sc->sc_mem_size = mem_space.len;
1160 #if defined(SOC_MV_ARMADAXP)
1162 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
1165 struct mv_pcib_softc *sc;
1167 sc = device_get_softc(dev);
1168 irq = irq - MSI_IRQ;
1170 /* validate parameters */
1171 if (isclr(&sc->sc_msi_bitmap, irq)) {
1172 device_printf(dev, "invalid MSI 0x%x\n", irq);
1176 mv_msi_data(irq, addr, data);
1178 debugf("%s: irq: %d addr: %jx data: %x\n",
1179 __func__, irq, *addr, *data);
1185 mv_pcib_alloc_msi(device_t dev, device_t child, int count,
1186 int maxcount __unused, int *irqs)
1188 struct mv_pcib_softc *sc;
1191 if (powerof2(count) == 0 || count > MSI_IRQ_NUM)
1194 sc = device_get_softc(dev);
1195 mtx_lock(&sc->sc_msi_mtx);
1197 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) {
1198 for (i = start; i < start + count; i++) {
1199 if (isset(&sc->sc_msi_bitmap, i))
1202 if (i == start + count)
1206 if ((start + count) == MSI_IRQ_NUM) {
1207 mtx_unlock(&sc->sc_msi_mtx);
1211 for (i = start; i < start + count; i++) {
1212 setbit(&sc->sc_msi_bitmap, i);
1213 *irqs++ = MSI_IRQ + i;
1215 debugf("%s: start: %x count: %x\n", __func__, start, count);
1217 mtx_unlock(&sc->sc_msi_mtx);
1222 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs)
1224 struct mv_pcib_softc *sc;
1227 sc = device_get_softc(dev);
1228 mtx_lock(&sc->sc_msi_mtx);
1230 for (i = 0; i < count; i++)
1231 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ);
1233 mtx_unlock(&sc->sc_msi_mtx);