2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
5 * Copyright (c) 2010 The FreeBSD Foundation
6 * Copyright (c) 2010-2015 Semihalf
9 * Developed by Semihalf.
11 * Portions of this software were developed by Semihalf
12 * under sponsorship from the FreeBSD Foundation.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of MARVELL nor the names of contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Marvell integrated PCI/PCI-Express controller driver.
43 #include <sys/cdefs.h>
44 __FBSDID("$FreeBSD$");
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
53 #include <sys/queue.h>
56 #include <sys/endian.h>
57 #include <sys/devmap.h>
59 #include <machine/fdt.h>
60 #include <machine/intr.h>
65 #include <dev/fdt/fdt_common.h>
66 #include <dev/ofw/ofw_bus.h>
67 #include <dev/ofw/ofw_bus_subr.h>
68 #include <dev/ofw/ofw_pci.h>
69 #include <dev/pci/pcivar.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcib_private.h>
73 #include "ofw_bus_if.h"
76 #include <machine/resource.h>
77 #include <machine/bus.h>
79 #include <arm/mv/mvreg.h>
80 #include <arm/mv/mvvar.h>
81 #include <arm/mv/mvwin.h>
84 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
86 #define debugf(fmt, args...)
90 * Code and data related to fdt-based PCI configuration.
92 * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was
93 * always Marvell-specific so that was deleted and the code now lives here.
102 #define FDT_RANGES_CELLS ((3 + 3 + 2) * 2)
105 mv_pci_range_dump(struct mv_pci_range *range)
109 printf(" base_pci = 0x%08lx\n", range->base_pci);
110 printf(" base_par = 0x%08lx\n", range->base_parent);
111 printf(" len = 0x%08lx\n", range->len);
116 mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space,
117 struct mv_pci_range *mem_space)
119 pcell_t ranges[FDT_RANGES_CELLS];
120 struct mv_pci_range *pci_space;
121 pcell_t addr_cells, size_cells, par_addr_cells;
123 pcell_t cell0, cell1, cell2;
124 int tuple_size, tuples, i, rv, offset_cells, len;
127 * Retrieve 'ranges' property.
129 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
131 if (addr_cells != 3 || size_cells != 2)
134 par_addr_cells = fdt_parent_addr_cells(node);
135 if (par_addr_cells > 3)
138 len = OF_getproplen(node, "ranges");
139 if (len > sizeof(ranges))
142 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
145 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
147 tuples = len / tuple_size;
150 * Initialize the ranges so that we don't have to worry about
151 * having them all defined in the FDT. In particular, it is
152 * perfectly fine not to want I/O space on PCI buses.
154 bzero(io_space, sizeof(*io_space));
155 bzero(mem_space, sizeof(*mem_space));
157 rangesptr = &ranges[0];
159 for (i = 0; i < tuples; i++) {
160 cell0 = fdt_data_get((void *)rangesptr, 1);
162 cell1 = fdt_data_get((void *)rangesptr, 1);
164 cell2 = fdt_data_get((void *)rangesptr, 1);
167 if (cell0 & 0x02000000) {
168 pci_space = mem_space;
169 } else if (cell0 & 0x01000000) {
170 pci_space = io_space;
176 if (par_addr_cells == 3) {
178 * This is a PCI subnode 'ranges'. Skip cell0 and
179 * cell1 of this entry and only use cell2.
182 rangesptr += offset_cells;
185 if ((par_addr_cells - offset_cells) > 2) {
189 pci_space->base_parent = fdt_data_get((void *)rangesptr,
190 par_addr_cells - offset_cells);
191 rangesptr += par_addr_cells - offset_cells;
193 if (size_cells > 2) {
197 pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
198 rangesptr += size_cells;
200 pci_space->base_pci = cell2;
208 mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space,
209 struct mv_pci_range *mem_space)
213 debugf("Processing PCI node: %x\n", node);
214 if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) {
215 debugf("could not decode parent PCI node 'ranges'\n");
219 debugf("Post fixup dump:\n");
220 mv_pci_range_dump(io_space);
221 mv_pci_range_dump(mem_space);
226 mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va,
229 struct mv_pci_range io_space, mem_space;
232 if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0)
235 devmap->pd_va = (io_va ? io_va : io_space.base_parent);
236 devmap->pd_pa = io_space.base_parent;
237 devmap->pd_size = io_space.len;
240 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent);
241 devmap->pd_pa = mem_space.base_parent;
242 devmap->pd_size = mem_space.len;
247 * Code and data related to the Marvell pcib driver.
250 #define PCI_CFG_ENA (1U << 31)
251 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
252 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
253 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8)
254 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc)
256 #define PCI_REG_CFG_ADDR 0x0C78
257 #define PCI_REG_CFG_DATA 0x0C7C
259 #define PCIE_REG_CFG_ADDR 0x18F8
260 #define PCIE_REG_CFG_DATA 0x18FC
261 #define PCIE_REG_CONTROL 0x1A00
262 #define PCIE_CTRL_LINK1X 0x00000001
263 #define PCIE_REG_STATUS 0x1A04
264 #define PCIE_REG_IRQ_MASK 0x1910
266 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1)
267 #define PCIE_CONTROL_HOT_RESET (1 << 24)
269 #define PCIE_LINK_TIMEOUT 1000000
271 #define PCIE_STATUS_LINK_DOWN 1
272 #define PCIE_STATUS_DEV_OFFS 16
274 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */
275 #define PCI_MIN_IO_ALLOC 4
276 #define PCI_MIN_MEM_ALLOC 16
278 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t))
280 struct mv_pcib_softc {
283 struct rman sc_mem_rman;
284 bus_addr_t sc_mem_base;
285 bus_addr_t sc_mem_size;
286 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE /
287 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
291 struct rman sc_io_rman;
292 bus_addr_t sc_io_base;
293 bus_addr_t sc_io_size;
294 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE /
295 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
298 struct resource *sc_res;
299 bus_space_handle_t sc_bsh;
300 bus_space_tag_t sc_bst;
303 struct mtx sc_msi_mtx;
304 uint32_t sc_msi_bitmap;
306 int sc_busnr; /* Host bridge bus number */
307 int sc_devnr; /* Host bridge device number */
309 int sc_mode; /* Endpoint / Root Complex */
311 struct ofw_bus_iinfo sc_pci_iinfo;
314 /* Local forward prototypes */
315 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *);
316 static void mv_pcib_hw_cfginit(void);
317 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int,
319 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int,
320 u_int, u_int, uint32_t, int);
321 static int mv_pcib_init(struct mv_pcib_softc *, int, int);
322 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
323 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
324 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
325 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t);
326 static int mv_pcib_mem_init(struct mv_pcib_softc *);
328 /* Forward prototypes */
329 static int mv_pcib_probe(device_t);
330 static int mv_pcib_attach(device_t);
332 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
333 rman_res_t, rman_res_t, rman_res_t, u_int);
334 static int mv_pcib_release_resource(device_t, device_t, int, int,
336 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
337 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
339 static int mv_pcib_maxslots(device_t);
340 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
341 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
343 static int mv_pcib_route_interrupt(device_t, device_t, int);
344 #if defined(SOC_MV_ARMADAXP)
345 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *);
346 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
347 static int mv_pcib_release_msi(device_t, device_t, int, int *);
351 * Bus interface definitions.
353 static device_method_t mv_pcib_methods[] = {
354 /* Device interface */
355 DEVMETHOD(device_probe, mv_pcib_probe),
356 DEVMETHOD(device_attach, mv_pcib_attach),
359 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar),
360 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar),
361 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource),
362 DEVMETHOD(bus_release_resource, mv_pcib_release_resource),
363 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
364 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
365 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
366 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
369 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots),
370 DEVMETHOD(pcib_read_config, mv_pcib_read_config),
371 DEVMETHOD(pcib_write_config, mv_pcib_write_config),
372 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt),
373 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
374 #if defined(SOC_MV_ARMADAXP)
375 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi),
376 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi),
377 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi),
380 /* OFW bus interface */
381 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
382 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
383 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
384 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
385 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
390 static driver_t mv_pcib_driver = {
393 sizeof(struct mv_pcib_softc),
396 devclass_t pcib_devclass;
398 DRIVER_MODULE(pcib, ofwbus, mv_pcib_driver, pcib_devclass, 0, 0);
399 DRIVER_MODULE(pcib, pcib_ctrl, mv_pcib_driver, pcib_devclass, 0, 0);
401 static struct mtx pcicfg_mtx;
404 mv_pcib_probe(device_t self)
408 node = ofw_bus_get_node(self);
409 if (!fdt_is_type(node, "pci"))
412 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") ||
413 ofw_bus_is_compatible(self, "mrvl,pci")))
416 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
417 return (BUS_PROBE_DEFAULT);
421 mv_pcib_attach(device_t self)
423 struct mv_pcib_softc *sc;
424 phandle_t node, parnode;
426 int err, bus, devfn, port_id;
428 sc = device_get_softc(self);
431 node = ofw_bus_get_node(self);
432 parnode = OF_parent(node);
434 if (OF_getencprop(node, "marvell,pcie-port", &(port_id),
435 sizeof(port_id)) <= 0) {
436 /* If port ID does not exist in the FDT set value to 0 */
437 if (!OF_hasprop(node, "marvell,pcie-port"))
443 if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) {
444 sc->sc_type = MV_TYPE_PCIE;
445 sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id);
446 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id);
447 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id);
448 } else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) {
449 sc->sc_type = MV_TYPE_PCI;
450 sc->sc_win_target = MV_WIN_PCI_TARGET;
451 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
452 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
457 * Retrieve our mem-mapped registers range.
460 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
462 if (sc->sc_res == NULL) {
463 device_printf(self, "could not map memory\n");
466 sc->sc_bst = rman_get_bustag(sc->sc_res);
467 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
469 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL);
470 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT :
474 * Get PCI interrupt info.
476 if (sc->sc_mode == MV_MODE_ROOT)
477 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t));
480 * Configure decode windows for PCI(E) access.
482 if (mv_pcib_decode_win(node, sc) != 0)
485 mv_pcib_hw_cfginit();
488 * Enable PCIE device.
490 mv_pcib_enable(sc, port_id);
495 err = mv_pcib_mem_init(sc);
500 * Preliminary bus enumeration to find first linked devices and set
501 * appropriate bus number from which should start the actual enumeration
503 for (bus = 0; bus < PCI_BUSMAX; bus++) {
504 for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) {
505 reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4);
507 continue; /* no device */
509 sc->sc_busnr = bus; /* update bus number */
515 if (sc->sc_mode == MV_MODE_ROOT) {
516 err = mv_pcib_init(sc, sc->sc_busnr,
517 mv_pcib_maxslots(sc->sc_dev));
521 device_add_child(self, "pci", -1);
524 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
525 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS);
526 device_add_child(self, "pci_ep", -1);
529 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF);
530 return (bus_generic_attach(self));
533 /* XXX SYS_RES_ should be released here */
534 rman_fini(&sc->sc_mem_rman);
535 rman_fini(&sc->sc_io_rman);
541 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit)
544 #if !defined(SOC_MV_ARMADAXP)
548 * Check if PCIE device is enabled.
550 if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) {
551 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) &
552 ~(CPU_CONTROL_PCIE_DISABLE(unit)));
554 timeout = PCIE_LINK_TIMEOUT;
555 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
557 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) {
560 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
567 if (sc->sc_mode == MV_MODE_ROOT) {
571 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND);
572 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN |
573 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
574 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val);
579 mv_pcib_mem_init(struct mv_pcib_softc *sc)
586 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
587 err = rman_init(&sc->sc_mem_rman);
591 sc->sc_io_rman.rm_type = RMAN_ARRAY;
592 err = rman_init(&sc->sc_io_rman);
594 rman_fini(&sc->sc_mem_rman);
598 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
599 sc->sc_mem_base + sc->sc_mem_size - 1);
603 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
604 sc->sc_io_base + sc->sc_io_size - 1);
611 rman_fini(&sc->sc_mem_rman);
612 rman_fini(&sc->sc_io_rman);
617 static inline uint32_t
618 pcib_bit_get(uint32_t *map, uint32_t bit)
620 uint32_t n = bit / BITS_PER_UINT32;
622 bit = bit % BITS_PER_UINT32;
623 return (map[n] & (1 << bit));
627 pcib_bit_set(uint32_t *map, uint32_t bit)
629 uint32_t n = bit / BITS_PER_UINT32;
631 bit = bit % BITS_PER_UINT32;
632 map[n] |= (1 << bit);
635 static inline uint32_t
636 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
640 for (i = start; i < start + bits; i++)
641 if (pcib_bit_get(map, i))
648 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
652 for (i = start; i < start + bits; i++)
653 pcib_bit_set(map, i);
657 * The idea of this allocator is taken from ARM No-Cache memory
658 * management code (sys/arm/arm/vm_machdep.c).
661 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask)
663 uint32_t bits, bits_limit, i, *map, min_alloc, size;
668 base = sc->sc_io_base;
669 min_alloc = PCI_MIN_IO_ALLOC;
670 bits_limit = sc->sc_io_size / min_alloc;
674 base = sc->sc_mem_base;
675 min_alloc = PCI_MIN_MEM_ALLOC;
676 bits_limit = sc->sc_mem_size / min_alloc;
677 map = sc->sc_mem_map;
682 bits = size / min_alloc;
684 for (i = 0; i + bits <= bits_limit; i += bits)
685 if (pcib_map_check(map, i, bits)) {
686 pcib_map_set(map, i, bits);
687 addr = base + (i * min_alloc);
695 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
701 reg = PCIR_BAR(barno);
704 * Need to init the BAR register with 0xffffffff before correct
707 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
708 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
712 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
713 width = ((bar & 7) == 4) ? 2 : 1;
715 addr = pcib_alloc(sc, bar);
720 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
721 bus, slot, func, reg, bar, addr);
723 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
725 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
732 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func)
734 bus_addr_t io_base, mem_base;
735 uint32_t io_limit, mem_limit;
738 io_base = sc->sc_io_base;
739 io_limit = io_base + sc->sc_io_size - 1;
740 mem_base = sc->sc_mem_base;
741 mem_limit = mem_base + sc->sc_mem_size - 1;
743 /* Configure I/O decode registers */
744 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
746 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
748 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
750 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
753 /* Configure memory decode registers */
754 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
756 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
759 /* Disable memory prefetch decode */
760 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
762 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
764 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
766 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
769 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
772 /* Configure buses behind the bridge */
773 mv_pcib_init(sc, secbus, PCI_SLOTMAX);
777 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot)
779 int slot, func, maxfunc, error;
780 uint8_t hdrtype, command, class, subclass;
782 for (slot = 0; slot <= maxslot; slot++) {
784 for (func = 0; func <= maxfunc; func++) {
785 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
786 func, PCIR_HDRTYPE, 1);
788 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
791 if (func == 0 && (hdrtype & PCIM_MFDEV))
792 maxfunc = PCI_FUNCMAX;
794 command = mv_pcib_read_config(sc->sc_dev, bus, slot,
795 func, PCIR_COMMAND, 1);
796 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
797 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
798 PCIR_COMMAND, command, 1);
800 error = mv_pcib_init_all_bars(sc, bus, slot, func,
806 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
808 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
809 PCIR_COMMAND, command, 1);
811 /* Handle PCI-PCI bridges */
812 class = mv_pcib_read_config(sc->sc_dev, bus, slot,
813 func, PCIR_CLASS, 1);
814 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
815 func, PCIR_SUBCLASS, 1);
817 if (class != PCIC_BRIDGE ||
818 subclass != PCIS_BRIDGE_PCI)
821 mv_pcib_init_bridge(sc, bus, slot, func);
825 /* Enable all ABCD interrupts */
826 pcib_write_irq_mask(sc, (0xF << 24));
832 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
833 int func, int hdrtype)
837 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
840 /* Program the base address registers */
841 while (bar < maxbar) {
842 i = mv_pcib_init_bar(sc, bus, slot, func, bar);
845 device_printf(sc->sc_dev,
846 "PCI IO/Memory space exhausted\n");
854 static struct resource *
855 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
856 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
858 struct mv_pcib_softc *sc = device_get_softc(dev);
859 struct rman *rm = NULL;
860 struct resource *res;
864 rm = &sc->sc_io_rman;
867 rm = &sc->sc_mem_rman;
870 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
871 type, rid, start, end, count, flags));
874 if (RMAN_IS_DEFAULT_RANGE(start, end)) {
875 start = sc->sc_mem_base;
876 end = sc->sc_mem_base + sc->sc_mem_size - 1;
877 count = sc->sc_mem_size;
880 if ((start < sc->sc_mem_base) || (start + count - 1 != end) ||
881 (end > sc->sc_mem_base + sc->sc_mem_size - 1))
884 res = rman_reserve_resource(rm, start, end, count, flags, child);
888 rman_set_rid(res, *rid);
889 rman_set_bustag(res, fdtbus_bs_tag);
890 rman_set_bushandle(res, start);
892 if (flags & RF_ACTIVE)
893 if (bus_activate_resource(child, type, *rid, res)) {
894 rman_release_resource(res);
902 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid,
903 struct resource *res)
906 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY)
907 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
910 return (rman_release_resource(res));
914 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
916 struct mv_pcib_softc *sc = device_get_softc(dev);
920 *result = sc->sc_busnr;
922 case PCIB_IVAR_DOMAIN:
923 *result = device_get_unit(dev);
931 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
933 struct mv_pcib_softc *sc = device_get_softc(dev);
937 sc->sc_busnr = value;
945 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
948 if (sc->sc_type != MV_TYPE_PCIE)
951 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
955 mv_pcib_hw_cfginit(void)
957 static int opened = 0;
962 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
967 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot,
968 u_int func, u_int reg, int bytes)
970 uint32_t addr, data, ca, cd;
972 ca = (sc->sc_type != MV_TYPE_PCI) ?
973 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
974 cd = (sc->sc_type != MV_TYPE_PCI) ?
975 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
976 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
977 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
979 mtx_lock_spin(&pcicfg_mtx);
980 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
985 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
989 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
993 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
997 mtx_unlock_spin(&pcicfg_mtx);
1002 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot,
1003 u_int func, u_int reg, uint32_t data, int bytes)
1005 uint32_t addr, ca, cd;
1007 ca = (sc->sc_type != MV_TYPE_PCI) ?
1008 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
1009 cd = (sc->sc_type != MV_TYPE_PCI) ?
1010 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
1011 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
1012 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
1014 mtx_lock_spin(&pcicfg_mtx);
1015 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
1019 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
1020 cd + (reg & 3), data);
1023 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
1024 cd + (reg & 2), htole16(data));
1027 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
1031 mtx_unlock_spin(&pcicfg_mtx);
1035 mv_pcib_maxslots(device_t dev)
1037 struct mv_pcib_softc *sc = device_get_softc(dev);
1039 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
1043 mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func)
1045 #if defined(SOC_MV_ARMADA38X)
1046 struct mv_pcib_softc *sc = device_get_softc(dev);
1047 uint32_t vendor, device;
1049 vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR,
1050 PCIR_VENDOR_LENGTH);
1051 device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE,
1052 PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK;
1054 return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X);
1056 /* On platforms other than Armada38x, root link is always at slot 0 */
1062 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
1063 u_int reg, int bytes)
1065 struct mv_pcib_softc *sc = device_get_softc(dev);
1067 /* Return ~0 if link is inactive or trying to read from Root */
1068 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
1069 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
1072 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
1076 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
1077 u_int reg, uint32_t val, int bytes)
1079 struct mv_pcib_softc *sc = device_get_softc(dev);
1081 /* Return if link is inactive or trying to write to Root */
1082 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
1083 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
1086 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
1090 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin)
1092 struct mv_pcib_softc *sc;
1093 struct ofw_pci_register reg;
1094 uint32_t pintr, mintr[4];
1098 sc = device_get_softc(bus);
1101 /* Fabricate imap information in case this isn't an OFW device */
1102 bzero(®, sizeof(reg));
1103 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
1104 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
1105 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
1107 icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1108 ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr),
1111 return (ofw_bus_map_intr(dev, iparent, icells, mintr));
1113 /* Maybe it's a real interrupt, not an intpin */
1117 device_printf(bus, "could not route pin %d for device %d.%d\n",
1118 pin, pci_get_slot(dev), pci_get_function(dev));
1119 return (PCI_INVALID_IRQ);
1123 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
1125 struct mv_pci_range io_space, mem_space;
1131 if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) {
1132 device_printf(dev, "could not retrieve 'ranges' data\n");
1136 /* Configure CPU decoding windows */
1137 error = decode_win_cpu_set(sc->sc_win_target,
1138 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0);
1140 device_printf(dev, "could not set up CPU decode "
1141 "window for PCI IO\n");
1144 error = decode_win_cpu_set(sc->sc_win_target,
1145 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len,
1146 mem_space.base_parent);
1148 device_printf(dev, "could not set up CPU decode "
1149 "windows for PCI MEM\n");
1153 sc->sc_io_base = io_space.base_parent;
1154 sc->sc_io_size = io_space.len;
1156 sc->sc_mem_base = mem_space.base_parent;
1157 sc->sc_mem_size = mem_space.len;
1162 #if defined(SOC_MV_ARMADAXP)
1164 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
1167 struct mv_pcib_softc *sc;
1169 sc = device_get_softc(dev);
1170 irq = irq - MSI_IRQ;
1172 /* validate parameters */
1173 if (isclr(&sc->sc_msi_bitmap, irq)) {
1174 device_printf(dev, "invalid MSI 0x%x\n", irq);
1178 mv_msi_data(irq, addr, data);
1180 debugf("%s: irq: %d addr: %jx data: %x\n",
1181 __func__, irq, *addr, *data);
1187 mv_pcib_alloc_msi(device_t dev, device_t child, int count,
1188 int maxcount __unused, int *irqs)
1190 struct mv_pcib_softc *sc;
1193 if (powerof2(count) == 0 || count > MSI_IRQ_NUM)
1196 sc = device_get_softc(dev);
1197 mtx_lock(&sc->sc_msi_mtx);
1199 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) {
1200 for (i = start; i < start + count; i++) {
1201 if (isset(&sc->sc_msi_bitmap, i))
1204 if (i == start + count)
1208 if ((start + count) == MSI_IRQ_NUM) {
1209 mtx_unlock(&sc->sc_msi_mtx);
1213 for (i = start; i < start + count; i++) {
1214 setbit(&sc->sc_msi_bitmap, i);
1215 *irqs++ = MSI_IRQ + i;
1217 debugf("%s: start: %x count: %x\n", __func__, start, count);
1219 mtx_unlock(&sc->sc_msi_mtx);
1224 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs)
1226 struct mv_pcib_softc *sc;
1229 sc = device_get_softc(dev);
1230 mtx_lock(&sc->sc_msi_mtx);
1232 for (i = 0; i < count; i++)
1233 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ);
1235 mtx_unlock(&sc->sc_msi_mtx);