2 * Copyright (c) 2020 Michal Meloun <mmel@FreeBSD.org>
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
30 * ARMADA 8040 GPIO driver.
32 #include "opt_platform.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
44 #include <machine/bus.h>
45 #include <machine/intr.h>
46 #include <machine/resource.h>
48 #include <dev/extres/syscon/syscon.h>
50 #include <dev/gpio/gpiobusvar.h>
52 #include <dev/ofw/openfirm.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
57 #include "syscon_if.h"
59 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx)
60 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
61 #define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->mtx, \
62 device_get_nameunit(_sc->dev), "mvebu_gpio", MTX_DEF)
63 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx);
64 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED);
65 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED);
67 #define GPIO_DATA_OUT 0x00
68 #define GPIO_CONTROL 0x04
69 #define GPIO_BLINK_ENA 0x08
70 #define GPIO_DATA_IN_POL 0x0C
71 #define GPIO_DATA_IN 0x10
72 #define GPIO_INT_CAUSE 0x14
73 #define GPIO_INT_MASK 0x18
74 #define GPIO_INT_LEVEL_MASK 0x1C
75 #define GPIO_CONTROL_SET 0x28
76 #define GPIO_CONTROL_CLR 0x2C
77 #define GPIO_DATA_SET 0x30
78 #define GPIO_DATA_CLR 0x34
80 #define GPIO_BIT(_p) ((_p) % 32)
81 #define GPIO_REGNUM(_p) ((_p) / 32)
83 #define MV_GPIO_MAX_NIRQS 4
84 #define MV_GPIO_MAX_NPINS 32
86 struct mvebu_gpio_irqsrc {
87 struct intr_irqsrc isrc;
93 struct mvebu_gpio_softc;
94 struct mvebu_gpio_irq_cookie {
95 struct mvebu_gpio_softc *sc;
99 struct mvebu_gpio_softc {
103 struct syscon *syscon;
105 struct resource *irq_res[MV_GPIO_MAX_NIRQS];
106 void *irq_ih[MV_GPIO_MAX_NIRQS];
107 struct mvebu_gpio_irq_cookie irq_cookies[MV_GPIO_MAX_NIRQS];
109 struct gpio_pin gpio_pins[MV_GPIO_MAX_NPINS];
110 struct mvebu_gpio_irqsrc *isrcs;
113 static struct ofw_compat_data compat_data[] = {
114 {"marvell,armada-8k-gpio", 1},
118 /* --------------------------------------------------------------------------
124 gpio_write(struct mvebu_gpio_softc *sc, bus_size_t reg,
125 struct gpio_pin *pin, uint32_t val)
129 bit = GPIO_BIT(pin->gp_pin);
130 SYSCON_WRITE_4(sc->syscon, sc->offset + GPIO_REGNUM(pin->gp_pin) + reg,
134 static inline uint32_t
135 gpio_read(struct mvebu_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin)
140 bit = GPIO_BIT(pin->gp_pin);
141 val = SYSCON_READ_4(sc->syscon,
142 sc->offset + GPIO_REGNUM(pin->gp_pin) + reg);
144 return (val >> bit) & 1;
148 gpio_modify(struct mvebu_gpio_softc *sc, bus_size_t reg,
149 struct gpio_pin *pin, uint32_t val)
153 bit = GPIO_BIT(pin->gp_pin);
154 SYSCON_MODIFY_4(sc->syscon, sc->offset + GPIO_REGNUM(pin->gp_pin) + reg,
155 1 << bit, (val & 1) << bit);
159 mvebu_gpio_pin_configure(struct mvebu_gpio_softc *sc, struct gpio_pin *pin,
163 if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == 0)
166 /* Manage input/output */
167 pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
168 if (flags & GPIO_PIN_OUTPUT) {
169 pin->gp_flags |= GPIO_PIN_OUTPUT;
170 gpio_write(sc, GPIO_CONTROL_CLR, pin, 1);
172 pin->gp_flags |= GPIO_PIN_INPUT;
173 gpio_write(sc, GPIO_CONTROL_SET, pin, 1);
178 mvebu_gpio_get_bus(device_t dev)
180 struct mvebu_gpio_softc *sc;
182 sc = device_get_softc(dev);
187 mvebu_gpio_pin_max(device_t dev, int *maxpin)
189 struct mvebu_gpio_softc *sc;
191 sc = device_get_softc(dev);
192 *maxpin = sc->gpio_npins - 1;
197 mvebu_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
199 struct mvebu_gpio_softc *sc;
201 sc = device_get_softc(dev);
202 if (pin >= sc->gpio_npins)
205 *caps = sc->gpio_pins[pin].gp_caps;
211 mvebu_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
213 struct mvebu_gpio_softc *sc;
215 sc = device_get_softc(dev);
216 if (pin >= sc->gpio_npins)
219 *flags = sc->gpio_pins[pin].gp_flags;
225 mvebu_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
227 struct mvebu_gpio_softc *sc;
229 sc = device_get_softc(dev);
230 if (pin >= sc->gpio_npins)
233 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME);
239 mvebu_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
241 struct mvebu_gpio_softc *sc;
243 sc = device_get_softc(dev);
244 if (pin >= sc->gpio_npins)
247 mvebu_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags);
253 mvebu_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
255 struct mvebu_gpio_softc *sc;
257 sc = device_get_softc(dev);
258 if (pin >= sc->gpio_npins)
262 gpio_write(sc, GPIO_DATA_SET, &sc->gpio_pins[pin], 1);
264 gpio_write(sc, GPIO_DATA_CLR, &sc->gpio_pins[pin], 1);
270 mvebu_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
272 struct mvebu_gpio_softc *sc;
274 sc = device_get_softc(dev);
275 if (pin >= sc->gpio_npins)
279 *val = gpio_read(sc, GPIO_DATA_IN, &sc->gpio_pins[pin]);
280 *val ^= gpio_read(sc, GPIO_DATA_IN_POL, &sc->gpio_pins[pin]);
287 mvebu_gpio_pin_toggle(device_t dev, uint32_t pin)
289 struct mvebu_gpio_softc *sc;
292 sc = device_get_softc(dev);
293 if (pin >= sc->gpio_npins)
297 mvebu_gpio_pin_get(sc->dev, pin, &val);
299 gpio_write(sc, GPIO_DATA_CLR, &sc->gpio_pins[pin], 1);
301 gpio_write(sc, GPIO_DATA_SET, &sc->gpio_pins[pin], 1);
307 /* --------------------------------------------------------------------------
313 intr_modify(struct mvebu_gpio_softc *sc, bus_addr_t reg,
314 struct mvebu_gpio_irqsrc *mgi, uint32_t val)
318 bit = GPIO_BIT(mgi->irq);
319 SYSCON_MODIFY_4(sc->syscon,
320 sc->offset + GPIO_REGNUM(mgi->irq) + reg, 1 << bit,
325 mvebu_gpio_isrc_mask(struct mvebu_gpio_softc *sc,
326 struct mvebu_gpio_irqsrc *mgi, uint32_t val)
330 intr_modify(sc, GPIO_INT_LEVEL_MASK, mgi, val);
332 intr_modify(sc, GPIO_INT_MASK, mgi, val);
336 mvebu_gpio_isrc_eoi(struct mvebu_gpio_softc *sc,
337 struct mvebu_gpio_irqsrc *mgi)
341 if (!mgi->is_level) {
342 bit = GPIO_BIT(mgi->irq);
343 SYSCON_WRITE_4(sc->syscon,
344 sc->offset + GPIO_REGNUM(mgi->irq) + GPIO_INT_CAUSE,
350 mvebu_gpio_pic_attach(struct mvebu_gpio_softc *sc)
356 sc->isrcs = malloc(sizeof(*sc->isrcs) * sc->gpio_npins, M_DEVBUF,
359 name = device_get_nameunit(sc->dev);
360 for (irq = 0; irq < sc->gpio_npins; irq++) {
361 sc->isrcs[irq].irq = irq;
362 sc->isrcs[irq].is_level = false;
363 sc->isrcs[irq].is_inverted = false;
364 rv = intr_isrc_register(&sc->isrcs[irq].isrc,
365 sc->dev, 0, "%s,%u", name, irq);
367 return (rv); /* XXX deregister ISRCs */
369 if (intr_pic_register(sc->dev,
370 OF_xref_from_node(ofw_bus_get_node(sc->dev))) == NULL)
377 mvebu_gpio_pic_detach(struct mvebu_gpio_softc *sc)
381 * There has not been established any procedure yet
382 * how to detach PIC from living system correctly.
384 device_printf(sc->dev, "%s: not implemented yet\n", __func__);
389 mvebu_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
391 struct mvebu_gpio_softc *sc;
392 struct mvebu_gpio_irqsrc *mgi;
394 sc = device_get_softc(dev);
395 mgi = (struct mvebu_gpio_irqsrc *)isrc;
396 mvebu_gpio_isrc_mask(sc, mgi, 0);
400 mvebu_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
402 struct mvebu_gpio_softc *sc;
403 struct mvebu_gpio_irqsrc *mgi;
405 sc = device_get_softc(dev);
406 mgi = (struct mvebu_gpio_irqsrc *)isrc;
407 mvebu_gpio_isrc_mask(sc, mgi, 1);
411 mvebu_gpio_pic_map_fdt(struct mvebu_gpio_softc *sc, u_int ncells,
412 pcell_t *cells, u_int *irqp, bool *invertedp, bool *levelp)
414 bool inverted, level;
417 * The first cell is the interrupt number.
418 * The second cell is used to specify flags:
419 * bits[3:0] trigger type and level flags:
420 * 1 = low-to-high edge triggered.
421 * 2 = high-to-low edge triggered.
422 * 4 = active high level-sensitive.
423 * 8 = active low level-sensitive.
425 if (ncells != 2 || cells[0] >= sc->gpio_npins)
449 if (invertedp != NULL)
450 *invertedp = inverted;
457 mvebu_gpio_pic_map_gpio(struct mvebu_gpio_softc *sc, u_int gpio_pin_num,
458 u_int gpio_pin_flags, u_int intr_mode, u_int *irqp, bool *invertedp,
461 bool inverted, level;
463 if (gpio_pin_num >= sc->gpio_npins)
467 case GPIO_INTR_LEVEL_LOW:
471 case GPIO_INTR_LEVEL_HIGH:
475 case GPIO_INTR_CONFORM:
476 case GPIO_INTR_EDGE_RISING:
480 case GPIO_INTR_EDGE_FALLING:
487 *irqp = gpio_pin_num;
488 if (invertedp != NULL)
489 *invertedp = inverted;
496 mvebu_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
497 struct intr_irqsrc **isrcp)
501 struct mvebu_gpio_softc *sc;
503 sc = device_get_softc(dev);
505 if (data->type == INTR_MAP_DATA_FDT) {
506 struct intr_map_data_fdt *daf;
508 daf = (struct intr_map_data_fdt *)data;
509 rv = mvebu_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq,
511 } else if (data->type == INTR_MAP_DATA_GPIO) {
512 struct intr_map_data_gpio *dag;
514 dag = (struct intr_map_data_gpio *)data;
515 rv = mvebu_gpio_pic_map_gpio(sc, dag->gpio_pin_num,
516 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, NULL, NULL);
521 *isrcp = &sc->isrcs[irq].isrc;
526 mvebu_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
528 struct mvebu_gpio_softc *sc;
529 struct mvebu_gpio_irqsrc *mgi;
531 sc = device_get_softc(dev);
532 mgi = (struct mvebu_gpio_irqsrc *)isrc;
534 mvebu_gpio_isrc_eoi(sc, mgi);
538 mvebu_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
540 struct mvebu_gpio_softc *sc;
541 struct mvebu_gpio_irqsrc *mgi;
543 sc = device_get_softc(dev);
544 mgi = (struct mvebu_gpio_irqsrc *)isrc;
545 mvebu_gpio_isrc_mask(sc, mgi, 1);
549 mvebu_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
551 struct mvebu_gpio_softc *sc;
552 struct mvebu_gpio_irqsrc *mgi;
554 sc = device_get_softc(dev);
555 mgi = (struct mvebu_gpio_irqsrc *)isrc;
557 mvebu_gpio_isrc_mask(sc, mgi, 0);
559 mvebu_gpio_isrc_eoi(sc, mgi);
563 mvebu_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
564 struct resource *res, struct intr_map_data *data)
567 bool inverted, level;
569 struct mvebu_gpio_softc *sc;
570 struct mvebu_gpio_irqsrc *mgi;
572 sc = device_get_softc(dev);
573 mgi = (struct mvebu_gpio_irqsrc *)isrc;
578 /* Get and check config for an interrupt. */
579 if (data->type == INTR_MAP_DATA_FDT) {
580 struct intr_map_data_fdt *daf;
582 daf = (struct intr_map_data_fdt *)data;
583 rv = mvebu_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq,
585 } else if (data->type == INTR_MAP_DATA_GPIO) {
586 struct intr_map_data_gpio *dag;
588 dag = (struct intr_map_data_gpio *)data;
589 rv = mvebu_gpio_pic_map_gpio(sc, dag->gpio_pin_num,
590 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq,
599 * If this is a setup for another handler,
600 * only check that its configuration match.
602 if (isrc->isrc_handlers != 0)
604 mgi->is_level == level && mgi->is_inverted == inverted ?
607 mgi->is_level = level;
608 mgi->is_inverted = inverted;
611 intr_modify(sc, GPIO_DATA_IN_POL, mgi, inverted ? 1 : 0);
612 mvebu_gpio_pic_enable_intr(dev, isrc);
619 mvebu_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
620 struct resource *res, struct intr_map_data *data)
622 struct mvebu_gpio_softc *sc;
623 struct mvebu_gpio_irqsrc *mgi;
625 sc = device_get_softc(dev);
626 mgi = (struct mvebu_gpio_irqsrc *)isrc;
628 if (isrc->isrc_handlers == 0)
629 mvebu_gpio_isrc_mask(sc, mgi, 0);
633 /* --------------------------------------------------------------------------
640 mvebu_gpio_intr(void *arg)
643 struct mvebu_gpio_softc *sc;
644 struct trapframe *tf;
645 struct mvebu_gpio_irqsrc *mgi;
646 struct mvebu_gpio_irq_cookie *cookie;
648 cookie = (struct mvebu_gpio_irq_cookie *)arg;
650 tf = curthread->td_intr_frame;
652 for (i = 0; i < sc->gpio_npins; i++) {
653 lvl = gpio_read(sc, GPIO_DATA_IN, &sc->gpio_pins[i]);
654 lvl &= gpio_read(sc, GPIO_INT_LEVEL_MASK, &sc->gpio_pins[i]);
655 edge = gpio_read(sc, GPIO_DATA_IN, &sc->gpio_pins[i]);
656 edge &= gpio_read(sc, GPIO_INT_LEVEL_MASK, &sc->gpio_pins[i]);
657 if (edge == 0 && lvl == 0)
662 mvebu_gpio_isrc_eoi(sc, mgi);
664 if (intr_isrc_dispatch(&mgi->isrc, tf) != 0) {
665 mvebu_gpio_isrc_mask(sc, mgi, 0);
667 mvebu_gpio_isrc_eoi(sc, mgi);
668 device_printf(sc->dev,
669 "Stray irq %u disabled\n", mgi->irq);
672 return (FILTER_HANDLED);
676 mvebu_gpio_probe(device_t dev)
679 if (!ofw_bus_status_okay(dev))
681 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
684 device_set_desc(dev, "Marvell Integrated GPIO Controller");
689 mvebu_gpio_detach(device_t dev)
691 struct mvebu_gpio_softc *sc;
694 sc = device_get_softc(dev);
696 KASSERT(mtx_initialized(&sc->mtx), ("gpio mutex not initialized"));
698 for (i = 0; i < MV_GPIO_MAX_NIRQS; i++) {
699 if (sc->irq_ih[i] != NULL)
700 bus_teardown_intr(dev, sc->irq_res[i], sc->irq_ih[i]);
703 if (sc->isrcs != NULL)
704 mvebu_gpio_pic_detach(sc);
706 gpiobus_detach_bus(dev);
708 for (i = 0; i < MV_GPIO_MAX_NIRQS; i++) {
709 if (sc->irq_res[i] != NULL)
710 bus_release_resource(dev, SYS_RES_IRQ, 0,
713 GPIO_LOCK_DESTROY(sc);
719 mvebu_gpio_attach(device_t dev)
721 struct mvebu_gpio_softc *sc;
723 struct gpio_pin *pin;
727 sc = device_get_softc(dev);
729 node = ofw_bus_get_node(dev);
734 rv = OF_getencprop(node, "ngpios", &pincnt, sizeof(pcell_t));
737 "ERROR: no pin-count or ngpios entry found!\n");
741 sc->gpio_npins = MIN(pincnt, MV_GPIO_MAX_NPINS);
744 "%d pins available\n", sc->gpio_npins);
746 rv = OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset));
748 device_printf(dev, "ERROR: no 'offset' property found!\n");
752 if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 ||
753 sc->syscon == NULL) {
754 device_printf(dev, "ERROR: cannot get syscon handle!\n");
758 /* Allocate interrupts. */
759 for (i = 0; i < MV_GPIO_MAX_NIRQS; i++) {
760 sc->irq_cookies[i].sc = sc;
761 sc->irq_cookies[i].bank_num = i;
763 sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ,
765 if (sc->irq_res[i] == NULL)
767 if ((bus_setup_intr(dev, sc->irq_res[i],
768 INTR_TYPE_MISC | INTR_MPSAFE, mvebu_gpio_intr, NULL,
769 &sc->irq_cookies[i], &sc->irq_ih[i]))) {
771 "WARNING: unable to register interrupt handler\n");
772 mvebu_gpio_detach(dev);
778 for (i = 0; i < sc->gpio_npins; i++) {
779 pin = sc->gpio_pins + i;
781 if (sc->irq_res[0] != NULL)
782 pin->gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
783 GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH |
784 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING;
786 pin->gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
788 gpio_read(sc, GPIO_CONTROL, &sc->gpio_pins[i]) == 0 ?
789 GPIO_PIN_OUTPUT : GPIO_PIN_INPUT;
790 snprintf(pin->gp_name, GPIOMAXNAME, "gpio%d", i);
793 gpio_modify(sc, GPIO_INT_MASK, pin, 0);
794 gpio_modify(sc, GPIO_INT_LEVEL_MASK, pin, 0);
795 gpio_modify(sc, GPIO_INT_CAUSE, pin, 0);
796 gpio_modify(sc, GPIO_DATA_IN_POL, pin, 0);
797 gpio_modify(sc, GPIO_BLINK_ENA, pin, 0);
800 if (sc->irq_res[0] != NULL) {
801 rv = mvebu_gpio_pic_attach(sc);
803 device_printf(dev, "WARNING: unable to attach PIC\n");
804 mvebu_gpio_detach(dev);
809 sc->busdev = gpiobus_attach_bus(dev);
810 if (sc->busdev == NULL) {
811 mvebu_gpio_detach(dev);
815 return (bus_generic_attach(dev));
819 mvebu_gpio_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent,
820 int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags)
831 mvebu_gpio_get_node(device_t bus, device_t dev)
834 /* We only have one child, the GPIO bus, which needs our own node. */
835 return (ofw_bus_get_node(bus));
838 static device_method_t mvebu_gpio_methods[] = {
839 DEVMETHOD(device_probe, mvebu_gpio_probe),
840 DEVMETHOD(device_attach, mvebu_gpio_attach),
841 DEVMETHOD(device_detach, mvebu_gpio_detach),
843 /* Interrupt controller interface */
844 DEVMETHOD(pic_disable_intr, mvebu_gpio_pic_disable_intr),
845 DEVMETHOD(pic_enable_intr, mvebu_gpio_pic_enable_intr),
846 DEVMETHOD(pic_map_intr, mvebu_gpio_pic_map_intr),
847 DEVMETHOD(pic_setup_intr, mvebu_gpio_pic_setup_intr),
848 DEVMETHOD(pic_teardown_intr, mvebu_gpio_pic_teardown_intr),
849 DEVMETHOD(pic_post_filter, mvebu_gpio_pic_post_filter),
850 DEVMETHOD(pic_post_ithread, mvebu_gpio_pic_post_ithread),
851 DEVMETHOD(pic_pre_ithread, mvebu_gpio_pic_pre_ithread),
854 DEVMETHOD(gpio_get_bus, mvebu_gpio_get_bus),
855 DEVMETHOD(gpio_pin_max, mvebu_gpio_pin_max),
856 DEVMETHOD(gpio_pin_getname, mvebu_gpio_pin_getname),
857 DEVMETHOD(gpio_pin_getflags, mvebu_gpio_pin_getflags),
858 DEVMETHOD(gpio_pin_getcaps, mvebu_gpio_pin_getcaps),
859 DEVMETHOD(gpio_pin_setflags, mvebu_gpio_pin_setflags),
860 DEVMETHOD(gpio_pin_get, mvebu_gpio_pin_get),
861 DEVMETHOD(gpio_pin_set, mvebu_gpio_pin_set),
862 DEVMETHOD(gpio_pin_toggle, mvebu_gpio_pin_toggle),
863 DEVMETHOD(gpio_map_gpios, mvebu_gpio_map_gpios),
865 /* ofw_bus interface */
866 DEVMETHOD(ofw_bus_get_node, mvebu_gpio_get_node),
871 static DEFINE_CLASS_0(gpio, mvebu_gpio_driver, mvebu_gpio_methods,
872 sizeof(struct mvebu_gpio_softc));
873 EARLY_DRIVER_MODULE(mvebu_gpio, simplebus, mvebu_gpio_driver, NULL, NULL,
874 BUS_PASS_TIMER + BUS_PASS_ORDER_LAST);