2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
7 * Developed by Semihalf.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of MARVELL nor the names of contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Decode windows addresses.
42 * All decoding windows must be aligned to their size, which has to be
47 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA)
51 #define MV_PHYS_BASE 0xF1000000
52 #define MV_SIZE (1024 * 1024) /* 1 MB */
55 #define MV_CESA_SRAM_BASE 0xF1100000
58 * External devices: 0x80000000, 1 GB (VA == PA)
59 * Includes Device Bus, PCI and PCIE.
61 #if defined(SOC_MV_ORION)
62 #define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */
63 #elif defined(SOC_MV_KIRKWOOD)
64 #define MV_PCI_PORTS 1 /* 1x PCIE */
65 #elif defined(SOC_MV_DISCOVERY)
66 #define MV_PCI_PORTS 8 /* 8x PCIE */
67 #elif defined(SOC_MV_ARMADAXP)
68 #define MV_PCI_PORTS 3 /* 3x PCIE */
69 #elif defined(SOC_MV_ARMADA38X)
70 #define MV_PCI_PORTS 4 /* 4x PCIE */
72 #error "MV_PCI_PORTS not configured !"
76 #define MV_PCI_MEM_PHYS_BASE 0x80000000
77 #define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */
78 #define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE
79 #define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS)
80 #define MV_PCI_MEM_SLICE(n) (MV_PCI_MEM_BASE + ((n) * \
81 MV_PCI_MEM_SLICE_SIZE))
83 #define MV_PCI_IO_PHYS_BASE 0xBF000000
84 #define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */
85 #define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE
86 #define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS)
87 #define MV_PCI_IO_SLICE(n) (MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE))
89 #define MV_PCI_VA_MEM_BASE 0
90 #define MV_PCI_VA_IO_BASE 0
93 * Device Bus (VA == PA)
95 #define MV_DEV_BOOT_BASE 0xF9300000
96 #define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */
98 #define MV_DEV_CS0_BASE 0xF9400000
99 #define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */
101 #define MV_DEV_CS1_BASE 0xF9500000
102 #define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */
104 #define MV_DEV_CS2_BASE 0xFB500000
105 #define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */
109 * Integrated SoC peripherals addresses
111 #define MV_BASE MV_PHYS_BASE /* VA == PA mapping */
112 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
113 #define MV_DDR_CADR_BASE (MV_BASE + 0x20180)
115 #define MV_DDR_CADR_BASE (MV_BASE + 0x1500)
117 #define MV_MPP_BASE (MV_BASE + 0x10000)
119 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
120 #define MV_MISC_BASE (MV_BASE + 0x18200)
121 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
122 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
123 #define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700)
124 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x1800)
126 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
127 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
128 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100)
131 #define MV_PCI_BASE (MV_BASE + 0x30000)
132 #define MV_PCI_SIZE 0x2000
134 #if defined(SOC_MV_ARMADA38X)
135 #define MV_PCIE_BASE (MV_BASE + 0x80000)
137 #define MV_PCIE_BASE (MV_BASE + 0x40000)
139 #define MV_PCIE_SIZE 0x2000
141 #define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000)
142 #define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000)
143 #define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000)
144 #define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000)
145 #define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000)
146 #define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000)
147 #define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000)
148 #define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000)
150 #define MV_SDIO_BASE (MV_BASE + 0x90000)
151 #define MV_SDIO_SIZE 0x10000
154 * Decode windows definitions and macros
156 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
157 #define MV_WIN_CPU_CTRL(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8)))
158 #define MV_WIN_CPU_BASE(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4)
159 #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + 0x008)
160 #define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + 0x00C)
162 #define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880))
163 #define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884))
164 #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888))
165 #define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C))
168 #if defined(SOC_MV_DISCOVERY)
169 #define MV_WIN_CPU_MAX 14
170 #elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
171 #define MV_WIN_CPU_MAX 20
173 #define MV_WIN_CPU_MAX 8
176 #define MV_WIN_CPU_ATTR_SHIFT 8
177 #define MV_WIN_CPU_TARGET_SHIFT 4
178 #define MV_WIN_CPU_ENABLE_BIT 1
180 #define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0)
181 #define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4)
182 #define MV_WIN_DDR_MAX 4
185 * These values are valid only for peripherals decoding windows
186 * Bit in ATTR is zeroed according to CS bank number
188 #define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs)))
189 #define MV_WIN_DDR_TARGET 0x0
191 #if defined(SOC_MV_DISCOVERY)
192 #define MV_WIN_CESA_TARGET 9
193 #define MV_WIN_CESA_ATTR(eng_sel) 1
194 #elif defined(SOC_MV_ARMADAXP)
195 #define MV_WIN_CESA_TARGET 9
197 * Bits [2:3] of cesa attribute select engine:
202 #define MV_WIN_CESA_ATTR(eng_sel) (1 | ((eng_sel) << 2))
203 #elif defined(SOC_MV_ARMADA38X)
204 #define MV_WIN_CESA_TARGET 9
206 * Bits [1:0] = Data swapping
209 * 0x2 = Byte and word swap
211 * Bits [4:2] = CESA select:
215 #define MV_WIN_CESA_ATTR(eng_sel) (0x11 | (1 << (3 - (eng_sel))))
217 #define MV_WIN_CESA_TARGET 3
218 #define MV_WIN_CESA_ATTR(eng_sel) 0
221 /* CESA TDMA address decoding registers */
222 #define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xA04)
223 #define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xA00)
224 #define MV_WIN_CESA_MAX 4
226 #define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320)
227 #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324)
228 #define MV_WIN_USB_MAX 4
230 #define MV_WIN_USB3_CTRL(n) (0x8 * (n) + 0x4000)
231 #define MV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4004)
232 #define MV_WIN_USB3_MAX 8
234 #define MV_WIN_NETA_OFFSET 0x2000
235 #define MV_WIN_NETA_BASE(n) MV_WIN_ETH_BASE(n) + MV_WIN_NETA_OFFSET
237 #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200)
238 #define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204)
239 #define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280)
240 #define MV_WIN_ETH_MAX 6
242 #define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00)
243 #define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04)
244 #define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60)
245 #define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70)
246 #define MV_WIN_IDMA_MAX 8
247 #define MV_IDMA_CHAN_MAX 4
249 #define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100)
250 #define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100)
251 #define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100)
252 #define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100)
253 #define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100)
254 #define MV_WIN_XOR_MAX 8
255 #define MV_XOR_CHAN_MAX 2
256 #define MV_XOR_NON_REMAP 4
258 #if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD)
259 #define MV_WIN_PCIE_TARGET(n) 4
260 #define MV_WIN_PCIE_MEM_ATTR(n) 0xE8
261 #define MV_WIN_PCIE_IO_ATTR(n) 0xE0
262 #elif defined(SOC_MV_ARMADAXP)
263 #define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2)))
264 #define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2)))
265 #define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2)))
266 #elif defined(SOC_MV_ARMADA38X)
267 #define MV_WIN_PCIE_TARGET(n) ((n) == 0 ? 8 : 4)
268 #define MV_WIN_PCIE_MEM_ATTR(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20)))
269 #define MV_WIN_PCIE_IO_ATTR(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20)))
270 #elif defined(SOC_MV_ORION)
271 #define MV_WIN_PCIE_TARGET(n) 4
272 #define MV_WIN_PCIE_MEM_ATTR(n) 0x59
273 #define MV_WIN_PCIE_IO_ATTR(n) 0x51
276 #define MV_WIN_PCI_TARGET 3
277 #define MV_WIN_PCI_MEM_ATTR 0x59
278 #define MV_WIN_PCI_IO_ATTR 0x51
280 #define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \
282 #define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \
284 #define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \
286 #define MV_WIN_PCIE_MAX 6
288 #define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800)
289 #define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010)
290 #define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014)
291 #define MV_PCIE_BAR_MAX 4
292 #define MV_PCIE_BAR_64BIT (0x4)
293 #define MV_PCIE_BAR_PREFETCH_EN (0x8)
295 #define MV_PCIE_CONTROL (0x1a00)
296 #define MV_PCIE_ROOT_CMPLX (1 << 1)
298 #if defined(SOC_MV_ARMADA38X)
299 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x60)
300 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x64)
301 #define MV_WIN_SATA_SIZE(n) (0x10 * (n) + 0x68)
302 #define MV_WIN_SATA_MAX 4
304 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30)
305 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34)
306 #define MV_WIN_SATA_MAX 4
309 #define MV_WIN_SDHCI_CTRL(n) (0x8 * (n) + 0x4080)
310 #define MV_WIN_SDHCI_BASE(n) (0x8 * (n) + 0x4084)
311 #define MV_WIN_SDHCI_MAX 8
313 #if defined(SOC_MV_ARMADA38X)
314 #define MV_BOOTROM_MEM_ADDR 0xFFF00000
315 #define MV_BOOTROM_WIN_SIZE 0xF
316 #define MV_CPU_SUBSYS_REGS_LEN 0x100
318 #define IO_WIN_9_CTRL_OFFSET 0x98
319 #define IO_WIN_9_BASE_OFFSET 0x9C
321 /* Mbus decoding unit IDs and attributes */
322 #define MBUS_BOOTROM_TGT_ID 0x1
323 #define MBUS_BOOTROM_ATTR 0x1D
325 /* Internal Units Sync Barrier Control Register */
326 #define MV_SYNC_BARRIER_CTRL 0x84
327 #define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF
330 /* IO Window Control Register fields */
331 #define IO_WIN_SIZE_SHIFT 16
332 #define IO_WIN_SIZE_MASK 0xFFFF
333 #define IO_WIN_COH_ATTR_MASK (0xF << 12)
334 #define IO_WIN_ATTR_SHIFT 8
335 #define IO_WIN_ATTR_MASK 0xFF
336 #define IO_WIN_TGT_SHIFT 4
337 #define IO_WIN_TGT_MASK 0xF
338 #define IO_WIN_SYNC_SHIFT 1
339 #define IO_WIN_SYNC_MASK 0x1
340 #define IO_WIN_ENA_SHIFT 0
341 #define IO_WIN_ENA_MASK 0x1
343 #define WIN_REG_IDX_RD(pre,reg,off,base) \
344 static __inline uint32_t \
345 pre ## _ ## reg ## _read(int i) \
347 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \
350 #define WIN_REG_IDX_RD2(pre,reg,off,base) \
351 static __inline uint32_t \
352 pre ## _ ## reg ## _read(int i, int j) \
354 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \
357 #define WIN_REG_BASE_IDX_RD(pre,reg,off) \
358 static __inline uint32_t \
359 pre ## _ ## reg ## _read(uint32_t base, int i) \
361 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \
364 #define WIN_REG_BASE_IDX_RD2(pre,reg,off) \
365 static __inline uint32_t \
366 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \
368 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \
371 #define WIN_REG_IDX_WR(pre,reg,off,base) \
372 static __inline void \
373 pre ## _ ## reg ## _write(int i, uint32_t val) \
375 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \
378 #define WIN_REG_IDX_WR2(pre,reg,off,base) \
379 static __inline void \
380 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \
382 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \
385 #define WIN_REG_BASE_IDX_WR(pre,reg,off) \
386 static __inline void \
387 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \
389 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \
392 #define WIN_REG_BASE_IDX_WR2(pre,reg,off) \
393 static __inline void \
394 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \
396 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \
399 #define WIN_REG_RD(pre,reg,off,base) \
400 static __inline uint32_t \
401 pre ## _ ## reg ## _read(void) \
403 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \
406 #define WIN_REG_BASE_RD(pre,reg,off) \
407 static __inline uint32_t \
408 pre ## _ ## reg ## _read(uint32_t base) \
410 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \
413 #define WIN_REG_WR(pre,reg,off,base) \
414 static __inline void \
415 pre ## _ ## reg ## _write(uint32_t val) \
417 bus_space_write_4(fdtbus_bs_tag, base, off, val); \
420 #define WIN_REG_BASE_WR(pre,reg,off) \
421 static __inline void \
422 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \
424 bus_space_write_4(fdtbus_bs_tag, base, off, val); \
427 #endif /* _MVWIN_H_ */