2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
5 * Developed by Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * Decode windows addresses.
40 * All decoding windows must be aligned to their size, which has to be
45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA)
49 #define MV_PHYS_BASE 0xF1000000
50 #define MV_SIZE (1024 * 1024) /* 1 MB */
53 #define MV_CESA_SRAM_BASE 0xF1100000
56 * External devices: 0x80000000, 1 GB (VA == PA)
57 * Includes Device Bus, PCI and PCIE.
59 #if defined(SOC_MV_ORION)
60 #define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */
61 #elif defined(SOC_MV_KIRKWOOD)
62 #define MV_PCI_PORTS 1 /* 1x PCIE */
63 #elif defined(SOC_MV_DISCOVERY)
64 #define MV_PCI_PORTS 8 /* 8x PCIE */
65 #elif defined(SOC_MV_ARMADAXP)
66 #define MV_PCI_PORTS 3 /* 3x PCIE */
67 #elif defined(SOC_MV_ARMADA38X)
68 #define MV_PCI_PORTS 4 /* 4x PCIE */
70 #error "MV_PCI_PORTS not configured !"
74 #define MV_PCI_MEM_PHYS_BASE 0x80000000
75 #define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */
76 #define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE
77 #define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS)
78 #define MV_PCI_MEM_SLICE(n) (MV_PCI_MEM_BASE + ((n) * \
79 MV_PCI_MEM_SLICE_SIZE))
81 #define MV_PCI_IO_PHYS_BASE 0xBF000000
82 #define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */
83 #define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE
84 #define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS)
85 #define MV_PCI_IO_SLICE(n) (MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE))
87 #define MV_PCI_VA_MEM_BASE 0
88 #define MV_PCI_VA_IO_BASE 0
91 * Device Bus (VA == PA)
93 #define MV_DEV_BOOT_BASE 0xF9300000
94 #define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */
96 #define MV_DEV_CS0_BASE 0xF9400000
97 #define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */
99 #define MV_DEV_CS1_BASE 0xF9500000
100 #define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */
102 #define MV_DEV_CS2_BASE 0xFB500000
103 #define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */
107 * Integrated SoC peripherals addresses
109 #define MV_BASE MV_PHYS_BASE /* VA == PA mapping */
110 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
111 #define MV_DDR_CADR_BASE (MV_BASE + 0x20180)
113 #define MV_DDR_CADR_BASE (MV_BASE + 0x1500)
115 #define MV_MPP_BASE (MV_BASE + 0x10000)
117 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
118 #define MV_MISC_BASE (MV_BASE + 0x18200)
119 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
120 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
121 #define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700)
122 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x1800)
124 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
125 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
126 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100)
129 #define MV_PCI_BASE (MV_BASE + 0x30000)
130 #define MV_PCI_SIZE 0x2000
132 #if defined(SOC_MV_ARMADA38X)
133 #define MV_PCIE_BASE (MV_BASE + 0x80000)
135 #define MV_PCIE_BASE (MV_BASE + 0x40000)
137 #define MV_PCIE_SIZE 0x2000
139 #define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000)
140 #define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000)
141 #define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000)
142 #define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000)
143 #define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000)
144 #define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000)
145 #define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000)
146 #define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000)
148 #define MV_SDIO_BASE (MV_BASE + 0x90000)
149 #define MV_SDIO_SIZE 0x10000
152 * Decode windows definitions and macros
154 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
155 #define MV_WIN_CPU_CTRL(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8)))
156 #define MV_WIN_CPU_BASE(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4)
157 #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + 0x008)
158 #define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + 0x00C)
160 #define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880))
161 #define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884))
162 #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888))
163 #define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C))
166 #if defined(SOC_MV_DISCOVERY)
167 #define MV_WIN_CPU_MAX 14
168 #elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
169 #define MV_WIN_CPU_MAX 20
171 #define MV_WIN_CPU_MAX 8
174 #define MV_WIN_CPU_ATTR_SHIFT 8
175 #define MV_WIN_CPU_TARGET_SHIFT 4
176 #define MV_WIN_CPU_ENABLE_BIT 1
178 #define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0)
179 #define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4)
180 #define MV_WIN_DDR_MAX 4
183 * These values are valid only for peripherals decoding windows
184 * Bit in ATTR is zeroed according to CS bank number
186 #define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs)))
187 #define MV_WIN_DDR_TARGET 0x0
189 #if defined(SOC_MV_DISCOVERY)
190 #define MV_WIN_CESA_TARGET 9
191 #define MV_WIN_CESA_ATTR(eng_sel) 1
192 #elif defined(SOC_MV_ARMADAXP)
193 #define MV_WIN_CESA_TARGET 9
195 * Bits [2:3] of cesa attribute select engine:
200 #define MV_WIN_CESA_ATTR(eng_sel) (1 | ((eng_sel) << 2))
201 #elif defined(SOC_MV_ARMADA38X)
202 #define MV_WIN_CESA_TARGET 9
204 * Bits [1:0] = Data swapping
207 * 0x2 = Byte and word swap
209 * Bits [4:2] = CESA select:
213 #define MV_WIN_CESA_ATTR(eng_sel) (0x11 | (1 << (3 - (eng_sel))))
215 #define MV_WIN_CESA_TARGET 3
216 #define MV_WIN_CESA_ATTR(eng_sel) 0
219 /* CESA TDMA address decoding registers */
220 #define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xA04)
221 #define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xA00)
222 #define MV_WIN_CESA_MAX 4
224 #define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320)
225 #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324)
226 #define MV_WIN_USB_MAX 4
228 #define MV_WIN_USB3_CTRL(n) (0x8 * (n) + 0x4000)
229 #define MV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4004)
230 #define MV_WIN_USB3_MAX 8
232 #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200)
233 #define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204)
234 #define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280)
235 #define MV_WIN_ETH_MAX 6
237 #define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00)
238 #define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04)
239 #define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60)
240 #define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70)
241 #define MV_WIN_IDMA_MAX 8
242 #define MV_IDMA_CHAN_MAX 4
244 #define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100)
245 #define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100)
246 #define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100)
247 #define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100)
248 #define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100)
249 #define MV_WIN_XOR_MAX 8
250 #define MV_XOR_CHAN_MAX 2
251 #define MV_XOR_NON_REMAP 4
253 #if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD)
254 #define MV_WIN_PCIE_TARGET(n) 4
255 #define MV_WIN_PCIE_MEM_ATTR(n) 0xE8
256 #define MV_WIN_PCIE_IO_ATTR(n) 0xE0
257 #elif defined(SOC_MV_ARMADAXP)
258 #define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2)))
259 #define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2)))
260 #define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2)))
261 #elif defined(SOC_MV_ARMADA38X)
262 #define MV_WIN_PCIE_TARGET(n) ((n) == 0 ? 8 : 4)
263 #define MV_WIN_PCIE_MEM_ATTR(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20)))
264 #define MV_WIN_PCIE_IO_ATTR(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20)))
265 #elif defined(SOC_MV_ORION)
266 #define MV_WIN_PCIE_TARGET(n) 4
267 #define MV_WIN_PCIE_MEM_ATTR(n) 0x59
268 #define MV_WIN_PCIE_IO_ATTR(n) 0x51
271 #define MV_WIN_PCI_TARGET 3
272 #define MV_WIN_PCI_MEM_ATTR 0x59
273 #define MV_WIN_PCI_IO_ATTR 0x51
275 #define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \
277 #define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \
279 #define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \
281 #define MV_WIN_PCIE_MAX 6
283 #define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800)
284 #define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010)
285 #define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014)
286 #define MV_PCIE_BAR_MAX 4
287 #define MV_PCIE_BAR_64BIT (0x4)
288 #define MV_PCIE_BAR_PREFETCH_EN (0x8)
290 #define MV_PCIE_CONTROL (0x1a00)
291 #define MV_PCIE_ROOT_CMPLX (1 << 1)
293 #if defined(SOC_MV_ARMADA38X)
294 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x60)
295 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x64)
296 #define MV_WIN_SATA_SIZE(n) (0x10 * (n) + 0x68)
297 #define MV_WIN_SATA_MAX 4
299 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30)
300 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34)
301 #define MV_WIN_SATA_MAX 4
304 #define MV_WIN_SDHCI_CTRL(n) (0x8 * (n) + 0x4080)
305 #define MV_WIN_SDHCI_BASE(n) (0x8 * (n) + 0x4084)
306 #define MV_WIN_SDHCI_MAX 8
308 #if defined(SOC_MV_ARMADA38X)
309 #define MV_BOOTROM_MEM_ADDR 0xFFF00000
310 #define MV_BOOTROM_WIN_SIZE 0xF
311 #define MV_CPU_SUBSYS_REGS_LEN 0x100
313 #define IO_WIN_9_CTRL_OFFSET 0x98
314 #define IO_WIN_9_BASE_OFFSET 0x9C
316 /* Mbus decoding unit IDs and attributes */
317 #define MBUS_BOOTROM_TGT_ID 0x1
318 #define MBUS_BOOTROM_ATTR 0x1D
320 /* Internal Units Sync Barrier Control Register */
321 #define MV_SYNC_BARRIER_CTRL 0x84
322 #define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF
325 /* IO Window Control Register fields */
326 #define IO_WIN_SIZE_SHIFT 16
327 #define IO_WIN_SIZE_MASK 0xFFFF
328 #define IO_WIN_ATTR_SHIFT 8
329 #define IO_WIN_ATTR_MASK 0xFF
330 #define IO_WIN_TGT_SHIFT 4
331 #define IO_WIN_TGT_MASK 0xF
332 #define IO_WIN_SYNC_SHIFT 1
333 #define IO_WIN_SYNC_MASK 0x1
334 #define IO_WIN_ENA_SHIFT 0
335 #define IO_WIN_ENA_MASK 0x1
337 #define WIN_REG_IDX_RD(pre,reg,off,base) \
338 static __inline uint32_t \
339 pre ## _ ## reg ## _read(int i) \
341 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \
344 #define WIN_REG_IDX_RD2(pre,reg,off,base) \
345 static __inline uint32_t \
346 pre ## _ ## reg ## _read(int i, int j) \
348 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \
351 #define WIN_REG_BASE_IDX_RD(pre,reg,off) \
352 static __inline uint32_t \
353 pre ## _ ## reg ## _read(uint32_t base, int i) \
355 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \
358 #define WIN_REG_BASE_IDX_RD2(pre,reg,off) \
359 static __inline uint32_t \
360 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \
362 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \
365 #define WIN_REG_IDX_WR(pre,reg,off,base) \
366 static __inline void \
367 pre ## _ ## reg ## _write(int i, uint32_t val) \
369 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \
372 #define WIN_REG_IDX_WR2(pre,reg,off,base) \
373 static __inline void \
374 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \
376 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \
379 #define WIN_REG_BASE_IDX_WR(pre,reg,off) \
380 static __inline void \
381 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \
383 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \
386 #define WIN_REG_BASE_IDX_WR2(pre,reg,off) \
387 static __inline void \
388 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \
390 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \
393 #define WIN_REG_RD(pre,reg,off,base) \
394 static __inline uint32_t \
395 pre ## _ ## reg ## _read(void) \
397 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \
400 #define WIN_REG_BASE_RD(pre,reg,off) \
401 static __inline uint32_t \
402 pre ## _ ## reg ## _read(uint32_t base) \
404 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \
407 #define WIN_REG_WR(pre,reg,off,base) \
408 static __inline void \
409 pre ## _ ## reg ## _write(uint32_t val) \
411 bus_space_write_4(fdtbus_bs_tag, base, off, val); \
414 #define WIN_REG_BASE_WR(pre,reg,off) \
415 static __inline void \
416 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \
418 bus_space_write_4(fdtbus_bs_tag, base, off, val); \
421 #endif /* _MVWIN_H_ */