sys/arm/mv/timer.c

   1 /*-
   2  * Copyright (c) 2006 Benno Rice.
   3  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
   4  * All rights reserved.
   5  *
   6  * Adapted to Marvell SoC by Semihalf.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/kernel.h>
  38 #include <sys/module.h>
  39 #include <sys/malloc.h>
  40 #include <sys/rman.h>
  41 #include <sys/timeet.h>
  42 #include <sys/timetc.h>
  43 #include <sys/watchdog.h>
  44 #include <machine/bus.h>
  45 #include <machine/cpu.h>
  46 #include <machine/intr.h>
  47
  48 #include <arm/mv/mvreg.h>
  49 #include <arm/mv/mvvar.h>
  50
  51 #include <dev/ofw/ofw_bus.h>
  52 #include <dev/ofw/ofw_bus_subr.h>
  53
  54 #define INITIAL_TIMECOUNTER     (0xffffffff)
  55 #define MAX_WATCHDOG_TICKS      (0xffffffff)
  56
  57 #define MV_TMR  0x1
  58 #define MV_WDT  0x2
  59 #define MV_NONE 0x0
  60
  61 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
  62 #define MV_CLOCK_SRC            25000000        /* Timers' 25MHz mode */
  63 #else
  64 #define MV_CLOCK_SRC            get_tclk()
  65 #endif
  66
  67 #if defined(SOC_MV_ARMADA38X)
  68 #define WATCHDOG_TIMER  4
  69 #else
  70 #define WATCHDOG_TIMER  2
  71 #endif
  72
  73 struct mv_timer_softc {
  74         struct resource *       timer_res[2];
  75         bus_space_tag_t         timer_bst;
  76         bus_space_handle_t      timer_bsh;
  77         struct mtx              timer_mtx;
  78         struct eventtimer       et;
  79         boolean_t               has_wdt;
  80 };
  81
  82 static struct resource_spec mv_timer_spec[] = {
  83         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  84         { SYS_RES_IRQ,          0,      RF_ACTIVE | RF_OPTIONAL },
  85         { -1, 0 }
  86 };
  87
  88 /* Interrupt is not required by MV_WDT devices */
  89 static struct ofw_compat_data mv_timer_compat[] = {
  90         {"mrvl,timer",                  MV_TMR | MV_WDT },
  91         {"marvell,armada-380-wdt",      MV_WDT },
  92         {NULL,                          MV_NONE }
  93 };
  94
  95 static struct mv_timer_softc *timer_softc = NULL;
  96 static int timers_initialized = 0;
  97
  98 static int      mv_timer_probe(device_t);
  99 static int      mv_timer_attach(device_t);
 100
 101 static int      mv_hardclock(void *);
 102 static unsigned mv_timer_get_timecount(struct timecounter *);
 103
 104 static uint32_t mv_get_timer_control(void);
 105 static void     mv_set_timer_control(uint32_t);
 106 static uint32_t mv_get_timer(uint32_t);
 107 static void     mv_set_timer(uint32_t, uint32_t);
 108 static void     mv_set_timer_rel(uint32_t, uint32_t);
 109 static void     mv_watchdog_enable(void);
 110 static void     mv_watchdog_disable(void);
 111 static void     mv_watchdog_event(void *, unsigned int, int *);
 112 static int      mv_timer_start(struct eventtimer *et,
 113     sbintime_t first, sbintime_t period);
 114 static int      mv_timer_stop(struct eventtimer *et);
 115 static void     mv_setup_timers(void);
 116
 117 static struct timecounter mv_timer_timecounter = {
 118         .tc_get_timecount = mv_timer_get_timecount,
 119         .tc_name = "CPUTimer1",
 120         .tc_frequency = 0,      /* This is assigned on the fly in the init sequence */
 121         .tc_counter_mask = ~0u,
 122         .tc_quality = 1000,
 123 };
 124
 125 static int
 126 mv_timer_probe(device_t dev)
 127 {
 128
 129         if (!ofw_bus_status_okay(dev))
 130                 return (ENXIO);
 131
 132         if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE)
 133                 return (ENXIO);
 134
 135         device_set_desc(dev, "Marvell CPU Timer");
 136         return (0);
 137 }
 138
 139 static int
 140 mv_timer_attach(device_t dev)
 141 {
 142         int     error;
 143         void    *ihl;
 144         struct  mv_timer_softc *sc;
 145 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
 146         uint32_t irq_cause, irq_mask;
 147 #endif
 148
 149         if (timer_softc != NULL)
 150                 return (ENXIO);
 151
 152         sc = (struct mv_timer_softc *)device_get_softc(dev);
 153         timer_softc = sc;
 154
 155         error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
 156         if (error) {
 157                 device_printf(dev, "could not allocate resources\n");
 158                 return (ENXIO);
 159         }
 160
 161         sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
 162         sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
 163
 164         sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt") ||
 165             ofw_bus_is_compatible(dev, "marvell,armada-380-wdt");
 166
 167         mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
 168
 169         if (sc->has_wdt) {
 170                 mv_watchdog_disable();
 171                 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
 172         }
 173
 174         if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data
 175             == MV_WDT) {
 176                 /* Don't set timers for wdt-only entry. */
 177                 device_printf(dev, "only watchdog attached\n");
 178                 return (0);
 179         } else if (sc->timer_res[1] == NULL) {
 180                 device_printf(dev, "no interrupt resource\n");
 181                 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
 182                 return (ENXIO);
 183         }
 184
 185         if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
 186             mv_hardclock, NULL, sc, &ihl) != 0) {
 187                 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
 188                 device_printf(dev, "Could not setup interrupt.\n");
 189                 return (ENXIO);
 190         }
 191
 192         mv_setup_timers();
 193 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
 194         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 195         irq_cause &= IRQ_TIMER0_CLR;
 196
 197         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 198         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 199         irq_mask |= IRQ_TIMER0_MASK;
 200         irq_mask &= ~IRQ_TIMER1_MASK;
 201         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 202 #endif
 203         sc->et.et_name = "CPUTimer0";
 204         sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
 205         sc->et.et_quality = 1000;
 206
 207         sc->et.et_frequency = MV_CLOCK_SRC;
 208         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
 209         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
 210         sc->et.et_start = mv_timer_start;
 211         sc->et.et_stop = mv_timer_stop;
 212         sc->et.et_priv = sc;
 213         et_register(&sc->et);
 214         mv_timer_timecounter.tc_frequency = MV_CLOCK_SRC;
 215         tc_init(&mv_timer_timecounter);
 216
 217         return (0);
 218 }
 219
 220 static int
 221 mv_hardclock(void *arg)
 222 {
 223         struct  mv_timer_softc *sc;
 224         uint32_t irq_cause;
 225
 226         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 227         irq_cause &= IRQ_TIMER0_CLR;
 228         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 229
 230         sc = (struct mv_timer_softc *)arg;
 231         if (sc->et.et_active)
 232                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 233
 234         return (FILTER_HANDLED);
 235 }
 236
 237 static device_method_t mv_timer_methods[] = {
 238         DEVMETHOD(device_probe, mv_timer_probe),
 239         DEVMETHOD(device_attach, mv_timer_attach),
 240
 241         { 0, 0 }
 242 };
 243
 244 static driver_t mv_timer_driver = {
 245         "timer",
 246         mv_timer_methods,
 247         sizeof(struct mv_timer_softc),
 248 };
 249
 250 static devclass_t mv_timer_devclass;
 251
 252 DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0);
 253
 254 static unsigned
 255 mv_timer_get_timecount(struct timecounter *tc)
 256 {
 257
 258         return (INITIAL_TIMECOUNTER - mv_get_timer(1));
 259 }
 260
 261 void
 262 DELAY(int usec)
 263 {
 264         uint32_t        val, val_temp;
 265         int32_t         nticks;
 266
 267         if (!timers_initialized) {
 268                 for (; usec > 0; usec--)
 269                         for (val = 100; val > 0; val--)
 270                                 __asm __volatile("nop" ::: "memory");
 271                 return;
 272         }
 273
 274         val = mv_get_timer(1);
 275         nticks = ((MV_CLOCK_SRC / 1000000 + 1) * usec);
 276
 277         while (nticks > 0) {
 278                 val_temp = mv_get_timer(1);
 279                 if (val > val_temp)
 280                         nticks -= (val - val_temp);
 281                 else
 282                         nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
 283
 284                 val = val_temp;
 285         }
 286 }
 287
 288 static uint32_t
 289 mv_get_timer_control(void)
 290 {
 291
 292         return (bus_space_read_4(timer_softc->timer_bst,
 293             timer_softc->timer_bsh, CPU_TIMER_CONTROL));
 294 }
 295
 296 static void
 297 mv_set_timer_control(uint32_t val)
 298 {
 299
 300         bus_space_write_4(timer_softc->timer_bst,
 301             timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);
 302 }
 303
 304 static uint32_t
 305 mv_get_timer(uint32_t timer)
 306 {
 307
 308         return (bus_space_read_4(timer_softc->timer_bst,
 309             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));
 310 }
 311
 312 static void
 313 mv_set_timer(uint32_t timer, uint32_t val)
 314 {
 315
 316         bus_space_write_4(timer_softc->timer_bst,
 317             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);
 318 }
 319
 320 static void
 321 mv_set_timer_rel(uint32_t timer, uint32_t val)
 322 {
 323
 324         bus_space_write_4(timer_softc->timer_bst,
 325             timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
 326 }
 327
 328 static void
 329 mv_watchdog_enable(void)
 330 {
 331         uint32_t val, irq_cause;
 332 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
 333         uint32_t irq_mask;
 334 #endif
 335
 336         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 337         irq_cause &= IRQ_TIMER_WD_CLR;
 338         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 339
 340 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
 341         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
 342         val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
 343         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 344
 345         val = read_cpu_misc(RSTOUTn_MASK);
 346         val &= ~RSTOUTn_MASK_WD;
 347         write_cpu_misc(RSTOUTn_MASK, val);
 348 #else
 349         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 350         irq_mask |= IRQ_TIMER_WD_MASK;
 351         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 352
 353         val = read_cpu_ctrl(RSTOUTn_MASK);
 354         val |= WD_RST_OUT_EN;
 355         write_cpu_ctrl(RSTOUTn_MASK, val);
 356 #endif
 357
 358         val = mv_get_timer_control();
 359 #if defined(SOC_MV_ARMADA38X)
 360         val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN;
 361 #elif defined(SOC_MV_ARMADAXP)
 362         val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
 363 #else
 364         val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
 365 #endif
 366         mv_set_timer_control(val);
 367 }
 368
 369 static void
 370 mv_watchdog_disable(void)
 371 {
 372         uint32_t val, irq_cause;
 373 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
 374         uint32_t irq_mask;
 375 #endif
 376
 377         val = mv_get_timer_control();
 378 #if defined(SOC_MV_ARMADA38X)
 379         val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
 380 #else
 381         val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
 382 #endif
 383         mv_set_timer_control(val);
 384
 385 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
 386         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
 387         val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
 388         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 389
 390         val = read_cpu_misc(RSTOUTn_MASK);
 391         val |= RSTOUTn_MASK_WD;
 392         write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
 393 #else
 394         val = read_cpu_ctrl(RSTOUTn_MASK);
 395         val &= ~WD_RST_OUT_EN;
 396         write_cpu_ctrl(RSTOUTn_MASK, val);
 397
 398         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 399         irq_mask &= ~(IRQ_TIMER_WD_MASK);
 400         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 401 #endif
 402
 403         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 404         irq_cause &= IRQ_TIMER_WD_CLR;
 405         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 406 }
 407
 408
 409 /*
 410  * Watchdog event handler.
 411  */
 412 static void
 413 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
 414 {
 415         uint64_t ns;
 416         uint64_t ticks;
 417
 418         mtx_lock(&timer_softc->timer_mtx);
 419         if (cmd == 0)
 420                 mv_watchdog_disable();
 421         else {
 422                 /*
 423                  * Watchdog timeout is in nanosecs, calculation according to
 424                  * watchdog(9)
 425                  */
 426                 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
 427                 ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000;
 428                 if (ticks > MAX_WATCHDOG_TICKS)
 429                         mv_watchdog_disable();
 430                 else {
 431                         mv_set_timer(WATCHDOG_TIMER, ticks);
 432                         mv_watchdog_enable();
 433                         *error = 0;
 434                 }
 435         }
 436         mtx_unlock(&timer_softc->timer_mtx);
 437 }
 438
 439 static int
 440 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 441 {
 442         struct  mv_timer_softc *sc;
 443         uint32_t val, val1;
 444
 445         /* Calculate dividers. */
 446         sc = (struct mv_timer_softc *)et->et_priv;
 447         if (period != 0)
 448                 val = ((uint32_t)sc->et.et_frequency * period) >> 32;
 449         else
 450                 val = 0;
 451         if (first != 0)
 452                 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;
 453         else
 454                 val1 = val;
 455
 456         /* Apply configuration. */
 457         mv_set_timer_rel(0, val);
 458         mv_set_timer(0, val1);
 459         val = mv_get_timer_control();
 460         val |= CPU_TIMER0_EN;
 461         if (period != 0)
 462                 val |= CPU_TIMER0_AUTO;
 463         else
 464                 val &= ~CPU_TIMER0_AUTO;
 465         mv_set_timer_control(val);
 466         return (0);
 467 }
 468
 469 static int
 470 mv_timer_stop(struct eventtimer *et)
 471 {
 472         uint32_t val;
 473
 474         val = mv_get_timer_control();
 475         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
 476         mv_set_timer_control(val);
 477         return (0);
 478 }
 479
 480 static void
 481 mv_setup_timers(void)
 482 {
 483         uint32_t val;
 484
 485         mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
 486         mv_set_timer(1, INITIAL_TIMECOUNTER);
 487         val = mv_get_timer_control();
 488         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
 489         val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
 490 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
 491         /* Enable 25MHz mode */
 492         val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
 493 #endif
 494         mv_set_timer_control(val);
 495         timers_initialized = 1;
 496 }