sys/arm/mv/timer.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2006 Benno Rice.
   5  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
   6  * All rights reserved.
   7  *
   8  * Adapted to Marvell SoC by Semihalf.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include <sys/param.h>
  37 #include <sys/systm.h>
  38 #include <sys/bus.h>
  39 #include <sys/kernel.h>
  40 #include <sys/module.h>
  41 #include <sys/malloc.h>
  42 #include <sys/rman.h>
  43 #include <sys/timeet.h>
  44 #include <sys/timetc.h>
  45 #include <sys/watchdog.h>
  46 #include <machine/bus.h>
  47 #include <machine/cpu.h>
  48 #include <machine/intr.h>
  49
  50 #include <arm/mv/mvreg.h>
  51 #include <arm/mv/mvvar.h>
  52
  53 #include <dev/ofw/ofw_bus.h>
  54 #include <dev/ofw/ofw_bus_subr.h>
  55
  56 #define INITIAL_TIMECOUNTER     (0xffffffff)
  57 #define MAX_WATCHDOG_TICKS      (0xffffffff)
  58
  59 #define MV_TMR  0x1
  60 #define MV_WDT  0x2
  61 #define MV_NONE 0x0
  62
  63 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
  64 #define MV_CLOCK_SRC            25000000        /* Timers' 25MHz mode */
  65 #else
  66 #define MV_CLOCK_SRC            get_tclk()
  67 #endif
  68
  69 #if defined(SOC_MV_ARMADA38X)
  70 #define WATCHDOG_TIMER  4
  71 #else
  72 #define WATCHDOG_TIMER  2
  73 #endif
  74
  75 struct mv_timer_softc {
  76         struct resource *       timer_res[2];
  77         bus_space_tag_t         timer_bst;
  78         bus_space_handle_t      timer_bsh;
  79         struct mtx              timer_mtx;
  80         struct eventtimer       et;
  81         boolean_t               has_wdt;
  82 };
  83
  84 static struct resource_spec mv_timer_spec[] = {
  85         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  86         { SYS_RES_IRQ,          0,      RF_ACTIVE | RF_OPTIONAL },
  87         { -1, 0 }
  88 };
  89
  90 /* Interrupt is not required by MV_WDT devices */
  91 static struct ofw_compat_data mv_timer_compat[] = {
  92         {"mrvl,timer",                  MV_TMR | MV_WDT },
  93         {"marvell,armada-380-wdt",      MV_WDT },
  94         {NULL,                          MV_NONE }
  95 };
  96
  97 static struct mv_timer_softc *timer_softc = NULL;
  98 static int timers_initialized = 0;
  99
 100 static int      mv_timer_probe(device_t);
 101 static int      mv_timer_attach(device_t);
 102
 103 static int      mv_hardclock(void *);
 104 static unsigned mv_timer_get_timecount(struct timecounter *);
 105
 106 static uint32_t mv_get_timer_control(void);
 107 static void     mv_set_timer_control(uint32_t);
 108 static uint32_t mv_get_timer(uint32_t);
 109 static void     mv_set_timer(uint32_t, uint32_t);
 110 static void     mv_set_timer_rel(uint32_t, uint32_t);
 111 static void     mv_watchdog_enable(void);
 112 static void     mv_watchdog_disable(void);
 113 static void     mv_watchdog_event(void *, unsigned int, int *);
 114 static int      mv_timer_start(struct eventtimer *et,
 115     sbintime_t first, sbintime_t period);
 116 static int      mv_timer_stop(struct eventtimer *et);
 117 static void     mv_setup_timers(void);
 118
 119 static struct timecounter mv_timer_timecounter = {
 120         .tc_get_timecount = mv_timer_get_timecount,
 121         .tc_name = "CPUTimer1",
 122         .tc_frequency = 0,      /* This is assigned on the fly in the init sequence */
 123         .tc_counter_mask = ~0u,
 124         .tc_quality = 1000,
 125 };
 126
 127 static int
 128 mv_timer_probe(device_t dev)
 129 {
 130
 131         if (!ofw_bus_status_okay(dev))
 132                 return (ENXIO);
 133
 134         if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE)
 135                 return (ENXIO);
 136
 137         device_set_desc(dev, "Marvell CPU Timer");
 138         return (0);
 139 }
 140
 141 static int
 142 mv_timer_attach(device_t dev)
 143 {
 144         int     error;
 145         void    *ihl;
 146         struct  mv_timer_softc *sc;
 147 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
 148         uint32_t irq_cause, irq_mask;
 149 #endif
 150
 151         if (timer_softc != NULL)
 152                 return (ENXIO);
 153
 154         sc = (struct mv_timer_softc *)device_get_softc(dev);
 155         timer_softc = sc;
 156
 157         error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
 158         if (error) {
 159                 device_printf(dev, "could not allocate resources\n");
 160                 return (ENXIO);
 161         }
 162
 163         sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
 164         sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
 165
 166         sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt") ||
 167             ofw_bus_is_compatible(dev, "marvell,armada-380-wdt");
 168
 169         mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
 170
 171         if (sc->has_wdt) {
 172                 mv_watchdog_disable();
 173                 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
 174         }
 175
 176         if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data
 177             == MV_WDT) {
 178                 /* Don't set timers for wdt-only entry. */
 179                 device_printf(dev, "only watchdog attached\n");
 180                 return (0);
 181         } else if (sc->timer_res[1] == NULL) {
 182                 device_printf(dev, "no interrupt resource\n");
 183                 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
 184                 return (ENXIO);
 185         }
 186
 187         if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
 188             mv_hardclock, NULL, sc, &ihl) != 0) {
 189                 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
 190                 device_printf(dev, "Could not setup interrupt.\n");
 191                 return (ENXIO);
 192         }
 193
 194         mv_setup_timers();
 195 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
 196         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 197         irq_cause &= IRQ_TIMER0_CLR;
 198
 199         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 200         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 201         irq_mask |= IRQ_TIMER0_MASK;
 202         irq_mask &= ~IRQ_TIMER1_MASK;
 203         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 204 #endif
 205         sc->et.et_name = "CPUTimer0";
 206         sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
 207         sc->et.et_quality = 1000;
 208
 209         sc->et.et_frequency = MV_CLOCK_SRC;
 210         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
 211         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
 212         sc->et.et_start = mv_timer_start;
 213         sc->et.et_stop = mv_timer_stop;
 214         sc->et.et_priv = sc;
 215         et_register(&sc->et);
 216         mv_timer_timecounter.tc_frequency = MV_CLOCK_SRC;
 217         tc_init(&mv_timer_timecounter);
 218
 219         return (0);
 220 }
 221
 222 static int
 223 mv_hardclock(void *arg)
 224 {
 225         struct  mv_timer_softc *sc;
 226         uint32_t irq_cause;
 227
 228         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 229         irq_cause &= IRQ_TIMER0_CLR;
 230         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 231
 232         sc = (struct mv_timer_softc *)arg;
 233         if (sc->et.et_active)
 234                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 235
 236         return (FILTER_HANDLED);
 237 }
 238
 239 static device_method_t mv_timer_methods[] = {
 240         DEVMETHOD(device_probe, mv_timer_probe),
 241         DEVMETHOD(device_attach, mv_timer_attach),
 242
 243         { 0, 0 }
 244 };
 245
 246 static driver_t mv_timer_driver = {
 247         "timer",
 248         mv_timer_methods,
 249         sizeof(struct mv_timer_softc),
 250 };
 251
 252 static devclass_t mv_timer_devclass;
 253
 254 DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0);
 255
 256 static unsigned
 257 mv_timer_get_timecount(struct timecounter *tc)
 258 {
 259
 260         return (INITIAL_TIMECOUNTER - mv_get_timer(1));
 261 }
 262
 263 void
 264 DELAY(int usec)
 265 {
 266         uint32_t        val, val_temp;
 267         int32_t         nticks;
 268
 269         if (!timers_initialized) {
 270                 for (; usec > 0; usec--)
 271                         for (val = 100; val > 0; val--)
 272                                 __asm __volatile("nop" ::: "memory");
 273                 return;
 274         }
 275
 276         val = mv_get_timer(1);
 277         nticks = ((MV_CLOCK_SRC / 1000000 + 1) * usec);
 278
 279         while (nticks > 0) {
 280                 val_temp = mv_get_timer(1);
 281                 if (val > val_temp)
 282                         nticks -= (val - val_temp);
 283                 else
 284                         nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
 285
 286                 val = val_temp;
 287         }
 288 }
 289
 290 static uint32_t
 291 mv_get_timer_control(void)
 292 {
 293
 294         return (bus_space_read_4(timer_softc->timer_bst,
 295             timer_softc->timer_bsh, CPU_TIMER_CONTROL));
 296 }
 297
 298 static void
 299 mv_set_timer_control(uint32_t val)
 300 {
 301
 302         bus_space_write_4(timer_softc->timer_bst,
 303             timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);
 304 }
 305
 306 static uint32_t
 307 mv_get_timer(uint32_t timer)
 308 {
 309
 310         return (bus_space_read_4(timer_softc->timer_bst,
 311             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));
 312 }
 313
 314 static void
 315 mv_set_timer(uint32_t timer, uint32_t val)
 316 {
 317
 318         bus_space_write_4(timer_softc->timer_bst,
 319             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);
 320 }
 321
 322 static void
 323 mv_set_timer_rel(uint32_t timer, uint32_t val)
 324 {
 325
 326         bus_space_write_4(timer_softc->timer_bst,
 327             timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
 328 }
 329
 330 static void
 331 mv_watchdog_enable(void)
 332 {
 333         uint32_t val, irq_cause;
 334 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
 335         uint32_t irq_mask;
 336 #endif
 337
 338         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 339         irq_cause &= IRQ_TIMER_WD_CLR;
 340         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 341
 342 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
 343         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
 344         val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
 345         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 346
 347         val = read_cpu_misc(RSTOUTn_MASK);
 348         val &= ~RSTOUTn_MASK_WD;
 349         write_cpu_misc(RSTOUTn_MASK, val);
 350 #else
 351         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 352         irq_mask |= IRQ_TIMER_WD_MASK;
 353         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 354
 355         val = read_cpu_ctrl(RSTOUTn_MASK);
 356         val |= WD_RST_OUT_EN;
 357         write_cpu_ctrl(RSTOUTn_MASK, val);
 358 #endif
 359
 360         val = mv_get_timer_control();
 361 #if defined(SOC_MV_ARMADA38X)
 362         val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN;
 363 #elif defined(SOC_MV_ARMADAXP)
 364         val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
 365 #else
 366         val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
 367 #endif
 368         mv_set_timer_control(val);
 369 }
 370
 371 static void
 372 mv_watchdog_disable(void)
 373 {
 374         uint32_t val, irq_cause;
 375 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
 376         uint32_t irq_mask;
 377 #endif
 378
 379         val = mv_get_timer_control();
 380 #if defined(SOC_MV_ARMADA38X)
 381         val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
 382 #else
 383         val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
 384 #endif
 385         mv_set_timer_control(val);
 386
 387 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
 388         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
 389         val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
 390         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 391
 392         val = read_cpu_misc(RSTOUTn_MASK);
 393         val |= RSTOUTn_MASK_WD;
 394         write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
 395 #else
 396         val = read_cpu_ctrl(RSTOUTn_MASK);
 397         val &= ~WD_RST_OUT_EN;
 398         write_cpu_ctrl(RSTOUTn_MASK, val);
 399
 400         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 401         irq_mask &= ~(IRQ_TIMER_WD_MASK);
 402         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 403 #endif
 404
 405         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 406         irq_cause &= IRQ_TIMER_WD_CLR;
 407         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 408 }
 409
 410
 411 /*
 412  * Watchdog event handler.
 413  */
 414 static void
 415 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
 416 {
 417         uint64_t ns;
 418         uint64_t ticks;
 419
 420         mtx_lock(&timer_softc->timer_mtx);
 421         if (cmd == 0)
 422                 mv_watchdog_disable();
 423         else {
 424                 /*
 425                  * Watchdog timeout is in nanosecs, calculation according to
 426                  * watchdog(9)
 427                  */
 428                 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
 429                 ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000;
 430                 if (ticks > MAX_WATCHDOG_TICKS)
 431                         mv_watchdog_disable();
 432                 else {
 433                         mv_set_timer(WATCHDOG_TIMER, ticks);
 434                         mv_watchdog_enable();
 435                         *error = 0;
 436                 }
 437         }
 438         mtx_unlock(&timer_softc->timer_mtx);
 439 }
 440
 441 static int
 442 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 443 {
 444         struct  mv_timer_softc *sc;
 445         uint32_t val, val1;
 446
 447         /* Calculate dividers. */
 448         sc = (struct mv_timer_softc *)et->et_priv;
 449         if (period != 0)
 450                 val = ((uint32_t)sc->et.et_frequency * period) >> 32;
 451         else
 452                 val = 0;
 453         if (first != 0)
 454                 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;
 455         else
 456                 val1 = val;
 457
 458         /* Apply configuration. */
 459         mv_set_timer_rel(0, val);
 460         mv_set_timer(0, val1);
 461         val = mv_get_timer_control();
 462         val |= CPU_TIMER0_EN;
 463         if (period != 0)
 464                 val |= CPU_TIMER0_AUTO;
 465         else
 466                 val &= ~CPU_TIMER0_AUTO;
 467         mv_set_timer_control(val);
 468         return (0);
 469 }
 470
 471 static int
 472 mv_timer_stop(struct eventtimer *et)
 473 {
 474         uint32_t val;
 475
 476         val = mv_get_timer_control();
 477         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
 478         mv_set_timer_control(val);
 479         return (0);
 480 }
 481
 482 static void
 483 mv_setup_timers(void)
 484 {
 485         uint32_t val;
 486
 487         mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
 488         mv_set_timer(1, INITIAL_TIMECOUNTER);
 489         val = mv_get_timer_control();
 490         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
 491         val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
 492 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
 493         /* Enable 25MHz mode */
 494         val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
 495 #endif
 496         mv_set_timer_control(val);
 497         timers_initialized = 1;
 498 }