sys/arm/mv/timer.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2006 Benno Rice.
   5  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
   6  * All rights reserved.
   7  *
   8  * Adapted to Marvell SoC by Semihalf.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include <sys/param.h>
  37 #include <sys/systm.h>
  38 #include <sys/bus.h>
  39 #include <sys/kernel.h>
  40 #include <sys/module.h>
  41 #include <sys/malloc.h>
  42 #include <sys/rman.h>
  43 #include <sys/timeet.h>
  44 #include <sys/timetc.h>
  45 #include <sys/watchdog.h>
  46 #include <machine/bus.h>
  47 #include <machine/cpu.h>
  48 #include <machine/intr.h>
  49
  50 #include <arm/mv/mvreg.h>
  51 #include <arm/mv/mvvar.h>
  52
  53 #include <dev/ofw/ofw_bus.h>
  54 #include <dev/ofw/ofw_bus_subr.h>
  55
  56 #define INITIAL_TIMECOUNTER     (0xffffffff)
  57 #define MAX_WATCHDOG_TICKS      (0xffffffff)
  58
  59 #define MV_TMR  0x1
  60 #define MV_WDT  0x2
  61 #define MV_NONE 0x0
  62
  63 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
  64 #define MV_CLOCK_SRC            25000000        /* Timers' 25MHz mode */
  65 #else
  66 #define MV_CLOCK_SRC            get_tclk()
  67 #endif
  68
  69 #if defined(SOC_MV_ARMADA38X)
  70 #define WATCHDOG_TIMER  4
  71 #else
  72 #define WATCHDOG_TIMER  2
  73 #endif
  74
  75 struct mv_timer_softc {
  76         struct resource *       timer_res[2];
  77         bus_space_tag_t         timer_bst;
  78         bus_space_handle_t      timer_bsh;
  79         struct mtx              timer_mtx;
  80         struct eventtimer       et;
  81         boolean_t               has_wdt;
  82 };
  83
  84 static struct resource_spec mv_timer_spec[] = {
  85         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  86         { SYS_RES_IRQ,          0,      RF_ACTIVE | RF_OPTIONAL },
  87         { -1, 0 }
  88 };
  89
  90 /* Interrupt is not required by MV_WDT devices */
  91 static struct ofw_compat_data mv_timer_compat[] = {
  92         {"mrvl,timer",                  MV_TMR | MV_WDT },
  93         {"marvell,armada-380-wdt",      MV_WDT },
  94         {NULL,                          MV_NONE }
  95 };
  96
  97 static struct mv_timer_softc *timer_softc = NULL;
  98 static int timers_initialized = 0;
  99
 100 static int      mv_timer_probe(device_t);
 101 static int      mv_timer_attach(device_t);
 102
 103 static int      mv_hardclock(void *);
 104 static unsigned mv_timer_get_timecount(struct timecounter *);
 105
 106 static uint32_t mv_get_timer_control(void);
 107 static void     mv_set_timer_control(uint32_t);
 108 static uint32_t mv_get_timer(uint32_t);
 109 static void     mv_set_timer(uint32_t, uint32_t);
 110 static void     mv_set_timer_rel(uint32_t, uint32_t);
 111 static void     mv_watchdog_enable(void);
 112 static void     mv_watchdog_disable(void);
 113 static void     mv_watchdog_event(void *, unsigned int, int *);
 114 static int      mv_timer_start(struct eventtimer *et,
 115     sbintime_t first, sbintime_t period);
 116 static int      mv_timer_stop(struct eventtimer *et);
 117 static void     mv_setup_timers(void);
 118
 119 static struct timecounter mv_timer_timecounter = {
 120         .tc_get_timecount = mv_timer_get_timecount,
 121         .tc_name = "CPUTimer1",
 122         .tc_frequency = 0,      /* This is assigned on the fly in the init sequence */
 123         .tc_counter_mask = ~0u,
 124         .tc_quality = 1000,
 125 };
 126
 127 static int
 128 mv_timer_probe(device_t dev)
 129 {
 130
 131         if (!ofw_bus_status_okay(dev))
 132                 return (ENXIO);
 133
 134         if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE)
 135                 return (ENXIO);
 136
 137         device_set_desc(dev, "Marvell CPU Timer");
 138         return (0);
 139 }
 140
 141 static int
 142 mv_timer_attach(device_t dev)
 143 {
 144         int     error;
 145         void    *ihl;
 146         struct  mv_timer_softc *sc;
 147 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
 148         uint32_t irq_cause, irq_mask;
 149 #endif
 150
 151         if (timer_softc != NULL)
 152                 return (ENXIO);
 153
 154         sc = (struct mv_timer_softc *)device_get_softc(dev);
 155         timer_softc = sc;
 156
 157         error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
 158         if (error) {
 159                 device_printf(dev, "could not allocate resources\n");
 160                 return (ENXIO);
 161         }
 162
 163         sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
 164         sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
 165
 166         sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt") ||
 167             ofw_bus_is_compatible(dev, "marvell,armada-380-wdt");
 168
 169         mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
 170
 171         if (sc->has_wdt) {
 172                 mv_watchdog_disable();
 173                 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
 174         }
 175
 176         if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data
 177             == MV_WDT) {
 178                 /* Don't set timers for wdt-only entry. */
 179                 device_printf(dev, "only watchdog attached\n");
 180                 return (0);
 181         } else if (sc->timer_res[1] == NULL) {
 182                 device_printf(dev, "no interrupt resource\n");
 183                 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
 184                 return (ENXIO);
 185         }
 186
 187         if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
 188             mv_hardclock, NULL, sc, &ihl) != 0) {
 189                 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
 190                 device_printf(dev, "Could not setup interrupt.\n");
 191                 return (ENXIO);
 192         }
 193
 194         mv_setup_timers();
 195 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
 196         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 197         irq_cause &= IRQ_TIMER0_CLR;
 198
 199         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 200         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 201         irq_mask |= IRQ_TIMER0_MASK;
 202         irq_mask &= ~IRQ_TIMER1_MASK;
 203         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 204 #endif
 205         sc->et.et_name = "CPUTimer0";
 206         sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
 207         sc->et.et_quality = 1000;
 208
 209         sc->et.et_frequency = MV_CLOCK_SRC;
 210         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
 211         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
 212         sc->et.et_start = mv_timer_start;
 213         sc->et.et_stop = mv_timer_stop;
 214         sc->et.et_priv = sc;
 215         et_register(&sc->et);
 216         mv_timer_timecounter.tc_frequency = MV_CLOCK_SRC;
 217         tc_init(&mv_timer_timecounter);
 218
 219         return (0);
 220 }
 221
 222 static int
 223 mv_hardclock(void *arg)
 224 {
 225         struct  mv_timer_softc *sc;
 226         uint32_t irq_cause;
 227
 228         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 229         irq_cause &= IRQ_TIMER0_CLR;
 230         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 231
 232         sc = (struct mv_timer_softc *)arg;
 233         if (sc->et.et_active)
 234                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 235
 236         return (FILTER_HANDLED);
 237 }
 238
 239 static device_method_t mv_timer_methods[] = {
 240         DEVMETHOD(device_probe, mv_timer_probe),
 241         DEVMETHOD(device_attach, mv_timer_attach),
 242
 243         { 0, 0 }
 244 };
 245
 246 static driver_t mv_timer_driver = {
 247         "timer",
 248         mv_timer_methods,
 249         sizeof(struct mv_timer_softc),
 250 };
 251
 252 static devclass_t mv_timer_devclass;
 253
 254 DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0);
 255
 256 static unsigned
 257 mv_timer_get_timecount(struct timecounter *tc)
 258 {
 259
 260         return (INITIAL_TIMECOUNTER - mv_get_timer(1));
 261 }
 262
 263 void
 264 DELAY(int usec)
 265 {
 266         uint32_t        val, val_temp;
 267         int32_t         nticks;
 268
 269         if (!timers_initialized) {
 270                 for (; usec > 0; usec--)
 271                         for (val = 100; val > 0; val--)
 272                                 __asm __volatile("nop" ::: "memory");
 273                 return;
 274         }
 275         TSENTER();
 276
 277         val = mv_get_timer(1);
 278         nticks = ((MV_CLOCK_SRC / 1000000 + 1) * usec);
 279
 280         while (nticks > 0) {
 281                 val_temp = mv_get_timer(1);
 282                 if (val > val_temp)
 283                         nticks -= (val - val_temp);
 284                 else
 285                         nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
 286
 287                 val = val_temp;
 288         }
 289         TSEXIT();
 290 }
 291
 292 static uint32_t
 293 mv_get_timer_control(void)
 294 {
 295
 296         return (bus_space_read_4(timer_softc->timer_bst,
 297             timer_softc->timer_bsh, CPU_TIMER_CONTROL));
 298 }
 299
 300 static void
 301 mv_set_timer_control(uint32_t val)
 302 {
 303
 304         bus_space_write_4(timer_softc->timer_bst,
 305             timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);
 306 }
 307
 308 static uint32_t
 309 mv_get_timer(uint32_t timer)
 310 {
 311
 312         return (bus_space_read_4(timer_softc->timer_bst,
 313             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));
 314 }
 315
 316 static void
 317 mv_set_timer(uint32_t timer, uint32_t val)
 318 {
 319
 320         bus_space_write_4(timer_softc->timer_bst,
 321             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);
 322 }
 323
 324 static void
 325 mv_set_timer_rel(uint32_t timer, uint32_t val)
 326 {
 327
 328         bus_space_write_4(timer_softc->timer_bst,
 329             timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
 330 }
 331
 332 static void
 333 mv_watchdog_enable(void)
 334 {
 335         uint32_t val, irq_cause;
 336 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
 337         uint32_t irq_mask;
 338 #endif
 339
 340         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 341         irq_cause &= IRQ_TIMER_WD_CLR;
 342         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 343
 344 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
 345         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
 346         val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
 347         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 348
 349         val = read_cpu_misc(RSTOUTn_MASK);
 350         val &= ~RSTOUTn_MASK_WD;
 351         write_cpu_misc(RSTOUTn_MASK, val);
 352 #else
 353         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 354         irq_mask |= IRQ_TIMER_WD_MASK;
 355         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 356
 357         val = read_cpu_ctrl(RSTOUTn_MASK);
 358         val |= WD_RST_OUT_EN;
 359         write_cpu_ctrl(RSTOUTn_MASK, val);
 360 #endif
 361
 362         val = mv_get_timer_control();
 363 #if defined(SOC_MV_ARMADA38X)
 364         val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN;
 365 #elif defined(SOC_MV_ARMADAXP)
 366         val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
 367 #else
 368         val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
 369 #endif
 370         mv_set_timer_control(val);
 371 }
 372
 373 static void
 374 mv_watchdog_disable(void)
 375 {
 376         uint32_t val, irq_cause;
 377 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
 378         uint32_t irq_mask;
 379 #endif
 380
 381         val = mv_get_timer_control();
 382 #if defined(SOC_MV_ARMADA38X)
 383         val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
 384 #else
 385         val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
 386 #endif
 387         mv_set_timer_control(val);
 388
 389 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
 390         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
 391         val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
 392         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 393
 394         val = read_cpu_misc(RSTOUTn_MASK);
 395         val |= RSTOUTn_MASK_WD;
 396         write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
 397 #else
 398         val = read_cpu_ctrl(RSTOUTn_MASK);
 399         val &= ~WD_RST_OUT_EN;
 400         write_cpu_ctrl(RSTOUTn_MASK, val);
 401
 402         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 403         irq_mask &= ~(IRQ_TIMER_WD_MASK);
 404         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 405 #endif
 406
 407         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 408         irq_cause &= IRQ_TIMER_WD_CLR;
 409         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 410 }
 411
 412
 413 /*
 414  * Watchdog event handler.
 415  */
 416 static void
 417 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
 418 {
 419         uint64_t ns;
 420         uint64_t ticks;
 421
 422         mtx_lock(&timer_softc->timer_mtx);
 423         if (cmd == 0)
 424                 mv_watchdog_disable();
 425         else {
 426                 /*
 427                  * Watchdog timeout is in nanosecs, calculation according to
 428                  * watchdog(9)
 429                  */
 430                 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
 431                 ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000;
 432                 if (ticks > MAX_WATCHDOG_TICKS)
 433                         mv_watchdog_disable();
 434                 else {
 435                         mv_set_timer(WATCHDOG_TIMER, ticks);
 436                         mv_watchdog_enable();
 437                         *error = 0;
 438                 }
 439         }
 440         mtx_unlock(&timer_softc->timer_mtx);
 441 }
 442
 443 static int
 444 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 445 {
 446         struct  mv_timer_softc *sc;
 447         uint32_t val, val1;
 448
 449         /* Calculate dividers. */
 450         sc = (struct mv_timer_softc *)et->et_priv;
 451         if (period != 0)
 452                 val = ((uint32_t)sc->et.et_frequency * period) >> 32;
 453         else
 454                 val = 0;
 455         if (first != 0)
 456                 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;
 457         else
 458                 val1 = val;
 459
 460         /* Apply configuration. */
 461         mv_set_timer_rel(0, val);
 462         mv_set_timer(0, val1);
 463         val = mv_get_timer_control();
 464         val |= CPU_TIMER0_EN;
 465         if (period != 0)
 466                 val |= CPU_TIMER0_AUTO;
 467         else
 468                 val &= ~CPU_TIMER0_AUTO;
 469         mv_set_timer_control(val);
 470         return (0);
 471 }
 472
 473 static int
 474 mv_timer_stop(struct eventtimer *et)
 475 {
 476         uint32_t val;
 477
 478         val = mv_get_timer_control();
 479         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
 480         mv_set_timer_control(val);
 481         return (0);
 482 }
 483
 484 static void
 485 mv_setup_timers(void)
 486 {
 487         uint32_t val;
 488
 489         mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
 490         mv_set_timer(1, INITIAL_TIMECOUNTER);
 491         val = mv_get_timer_control();
 492         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
 493         val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
 494 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
 495         /* Enable 25MHz mode */
 496         val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
 497 #endif
 498         mv_set_timer_control(val);
 499         timers_initialized = 1;
 500 }