sys/arm/nvidia/tegra124/tegra124_clk_per.c

   1 /*-
   2  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/lock.h>
  34 #include <sys/mutex.h>
  35 #include <sys/rman.h>
  36
  37 #include <machine/bus.h>
  38
  39 #include <dev/extres/clk/clk.h>
  40
  41 #include <gnu/dts/include/dt-bindings/clock/tegra124-car.h>
  42 #include "tegra124_car.h"
  43
  44 /* The TEGRA124_CLK_XUSB_GATE is missing in current
  45  * DT bindings, define it localy
  46  */
  47 #ifdef TEGRA124_CLK_XUSB_GATE
  48 #error "TEGRA124_CLK_XUSB_GATE is now defined, revisit XUSB code!"
  49 #else
  50 #define TEGRA124_CLK_XUSB_GATE 143
  51 #endif
  52
  53 /* Bits in base register. */
  54 #define PERLCK_AMUX_MASK        0x0F
  55 #define PERLCK_AMUX_SHIFT       16
  56 #define PERLCK_AMUX_DIS         (1 << 20)
  57 #define PERLCK_UDIV_DIS         (1 << 24)
  58 #define PERLCK_ENA_MASK         (1 << 28)
  59 #define PERLCK_MUX_SHIFT        29
  60 #define PERLCK_MUX_MASK         0x07
  61
  62
  63 struct periph_def {
  64         struct clknode_init_def clkdef;
  65         uint32_t                base_reg;
  66         uint32_t                div_width;
  67         uint32_t                div_mask;
  68         uint32_t                div_f_width;
  69         uint32_t                div_f_mask;
  70         uint32_t                flags;
  71 };
  72
  73 struct pgate_def {
  74         struct clknode_init_def clkdef;
  75         uint32_t                idx;
  76         uint32_t                flags;
  77 };
  78 #define PLIST(x) static const char *x[]
  79
  80 #define GATE(_id, cname, plist, _idx)                                   \
  81 {                                                                       \
  82         .clkdef.id = TEGRA124_CLK_##_id,                                \
  83         .clkdef.name = cname,                                           \
  84         .clkdef.parent_names = (const char *[]){plist},                 \
  85         .clkdef.parent_cnt = 1,                                         \
  86         .clkdef.flags = CLK_NODE_STATIC_STRINGS,                        \
  87         .idx = _idx,                                                    \
  88         .flags = 0,                                                     \
  89 }
  90
  91 /* Sources for multiplexors. */
  92 PLIST(mux_a_N_audio_N_p_N_clkm) =
  93     {"pllA_out0", NULL, "audio",  NULL,
  94      "pllP_out0", NULL, "clk_m"};
  95 PLIST(mux_a_N_audio0_N_p_N_clkm) =
  96     {"pllA_out0", NULL, "audio0", NULL,
  97      "pllP_out0", NULL, "clk_m"};
  98 PLIST(mux_a_N_audio1_N_p_N_clkm) =
  99     {"pllA_out0", NULL, "audio1", NULL,
 100      "pllP_out0", NULL, "clk_m"};
 101 PLIST(mux_a_N_audio2_N_p_N_clkm) =
 102     {"pllA_out0", NULL, "audio2", NULL,
 103      "pllP_out0", NULL, "clk_m"};
 104 PLIST(mux_a_N_audio3_N_p_N_clkm) =
 105     {"pllA_out0", NULL, "audio3", NULL,
 106      "pllP_out0", NULL, "clk_m"};
 107 PLIST(mux_a_N_audio4_N_p_N_clkm) =
 108     {"pllA_out0", NULL, "audio4", NULL,
 109      "pllP_out0", NULL, "clk_m"};
 110 PLIST(mux_a_clks_p_clkm_e) =
 111     {"pllA_out0", "clk_s", "pllP_out0",
 112      "clk_m", "pllE_out0"};
 113 PLIST(mux_a_c2_c_c3_p_N_clkm) =
 114     {"pllA_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 115      "pllP_out0", NULL, "clk_m"};
 116
 117 PLIST(mux_m_c_p_a_c2_c3) =
 118     {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0",
 119      "pllC2_out0", "pllC3_out0"};
 120 PLIST(mux_m_c_p_a_c2_c3_clkm) =
 121     {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0",
 122      "pllC2_out0", "pllC3_out0", "clk_m"};
 123 PLIST(mux_m_c_p_a_c2_c3_clkm_c4) =
 124     {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0",
 125      "pllC2_out0", "pllC3_out0", "clk_m", "pllC4_out0"};
 126 PLIST(mux_m_c_p_clkm_mud_c2_c3) =
 127     {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m",
 128      "pllM_UD", "pllC2_out0", "pllC3_out0"};
 129 PLIST(mux_m_c_p_clkm_mud_c2_c3_cud) =
 130     {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m",
 131      "pllM_UD", "pllC2_out0", "pllC3_out0", "pllC_UD"};
 132
 133 PLIST(mux_m_c2_c_c3_p_N_a) =
 134     {"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 135      "pllP_out0", NULL, "pllA_out0"};
 136 PLIST(mux_m_c2_c_c3_p_N_a_c4) =
 137     {"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 138      NULL, "pllA_out0", "pllC4_out0"};
 139
 140 PLIST(mux_p_N_c_N_N_N_clkm) =
 141     {"pllP_out0", NULL, "pllC_out0", NULL,
 142      NULL, NULL, "clk_m"};
 143 PLIST(mux_p_N_c_N_m_N_clkm) =
 144     {"pllP_out0", NULL, "pllC_out0", NULL,
 145      "pllM_out0", NULL, "clk_m"};
 146 PLIST(mux_p_c_c2_clkm) =
 147     {"pllP_out0", "pllC_out0", "pllC2_out0", "clk_m"};
 148 PLIST(mux_p_c2_c_c3_m) =
 149     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 150      "pllM_out0"};
 151 PLIST(mux_p_c2_c_c3_m_N_clkm) =
 152     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 153      "pllM_out0", NULL, "clk_m"};
 154 PLIST(mux_p_c2_c_c3_m_e_clkm) =
 155     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 156      "pllM_out0", "pllE_out0", "clk_m"};
 157 PLIST(mux_p_c2_c_c3_m_a_clkm) =
 158     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 159      "pllM_out0", "pllA_out0", "clk_m"};
 160 PLIST(mux_p_c2_c_c3_m_clks_clkm) =
 161     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 162      "pllM_out0", "clk_s", "clk_m"};
 163 PLIST(mux_p_c2_c_c3_clks_N_clkm) =
 164     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 165      "clk_s", NULL, "clk_m"};
 166 PLIST(mux_p_c2_c_c3_clkm_N_clks) =
 167     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 168      "clk_m", NULL, "clk_s"};
 169 PLIST(mux_p_clkm_clks_E) =
 170     {"pllP_out0", "clk_m", "clk_s", "pllE_out0"};
 171 PLIST(mux_p_m_d_a_c_d2_clkm) =
 172     {"pllP_out0", "pllM_out0", "pllD_out0", "pllA_out0",
 173      "pllC_out0", "pllD2_out0", "clk_m"};
 174
 175 PLIST(mux_clkm_N_u48_N_p_N_u480) =
 176     {"clk_m", NULL, "pllU_48", NULL,
 177      "pllP_out0", NULL, "pllU_480"};
 178 PLIST(mux_clkm_p_c2_c_c3_refre) =
 179     {"clk_m", "pllP_out0", "pllC2_out0", "pllC_out0",
 180      "pllC3_out0", "pllREFE_out"};
 181 PLIST(mux_clkm_refe_clks_u480_c_c2_c3_oscdiv) =
 182     {"clk_m", "pllREFE_out", "clk_s", "pllU_480",
 183      "pllC_out0", "pllC2_out0", "pllC3_out0", "osc_div_clk"};
 184
 185 PLIST(mux_sep_audio) =
 186    {"pllA_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 187     "pllP_out0", NULL, "clk_m", NULL,
 188     "spdif_in", "i2s0", "i2s1", "i2s2",
 189     "i2s4", "pllA_out0", "ext_vimclk"};
 190
 191 static uint32_t clk_enable_reg[] = {
 192         CLK_OUT_ENB_L,
 193         CLK_OUT_ENB_H,
 194         CLK_OUT_ENB_U,
 195         CLK_OUT_ENB_V,
 196         CLK_OUT_ENB_W,
 197         CLK_OUT_ENB_X,
 198 };
 199
 200 static uint32_t clk_reset_reg[] = {
 201         RST_DEVICES_L,
 202         RST_DEVICES_H,
 203         RST_DEVICES_U,
 204         RST_DEVICES_V,
 205         RST_DEVICES_W,
 206         RST_DEVICES_X,
 207 };
 208
 209 #define L(n)  ((0 * 32) + (n))
 210 #define H(n)  ((1 * 32) + (n))
 211 #define U(n)  ((2 * 32) + (n))
 212 #define V(n)  ((3 * 32) + (n))
 213 #define W(n)  ((4 * 32) + (n))
 214 #define X(n)  ((5 * 32) + (n))
 215
 216 static struct pgate_def pgate_def[] = {
 217         /* bank L ->  0-31 */
 218         /* GATE(CPU, "cpu", "clk_m", L(0)), */
 219         GATE(ISPB, "ispb", "clk_m", L(3)),
 220         GATE(RTC, "rtc", "clk_s", L(4)),
 221         GATE(TIMER, "timer", "clk_m", L(5)),
 222         GATE(UARTA, "uarta", "pc_uarta" , L(6)),
 223         GATE(UARTB, "uartb", "pc_uartb", L(7)),
 224         GATE(VFIR, "vfir", "pc_vfir", L(7)),
 225         /* GATE(GPIO, "gpio", "clk_m", L(8)), */
 226         GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)),
 227         GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)),
 228         GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)),
 229         GATE(I2S1, "i2s1", "pc_i2s1", L(11)),
 230         GATE(I2C1, "i2c1", "pc_i2c1", L(12)),
 231         GATE(SDMMC1, "sdmmc1", "pc_sdmmc1", L(14)),
 232         GATE(SDMMC4, "sdmmc4", "pc_sdmmc4", L(15)),
 233         GATE(PWM, "pwm", "pc_pwm", L(17)),
 234         GATE(I2S2, "i2s2", "pc_i2s2", L(18)),
 235         GATE(VI, "vi", "pc_vi", L(20)),
 236         GATE(USBD, "usbd", "clk_m", L(22)),
 237         GATE(ISP, "isp", "pc_isp", L(23)),
 238         GATE(DISP2, "disp2", "pc_disp2", L(26)),
 239         GATE(DISP1, "disp1", "pc_disp1", L(27)),
 240         GATE(HOST1X, "host1x", "pc_host1x", L(28)),
 241         GATE(VCP, "vcp", "clk_m", L(29)),
 242         GATE(I2S0, "i2s0", "pc_i2s0", L(30)),
 243         /* GATE(CACHE2, "ccache2", "clk_m", L(31)), */
 244
 245         /* bank H -> 32-63 */
 246         GATE(MC, "mem", "clk_m", H(0)),
 247         /* GATE(AHBDMA, "ahbdma", "clk_m", H(1)), */
 248         GATE(APBDMA, "apbdma", "clk_m", H(2)),
 249         GATE(KBC, "kbc", "clk_s", H(4)),
 250         /* GATE(STAT_MON, "stat_mon", "clk_s", H(5)), */
 251         /* GATE(PMC, "pmc", "clk_s", H(6)), */
 252         GATE(FUSE, "fuse", "clk_m", H(7)),
 253         GATE(KFUSE, "kfuse", "clk_m", H(8)),
 254         GATE(SBC1, "spi1", "pc_spi1", H(9)),
 255         GATE(NOR, "snor", "pc_snor", H(10)),
 256         /* GATE(JTAG2TBC, "jtag2tbc", "clk_m", H(11)), */
 257         GATE(SBC2, "spi2", "pc_spi2", H(12)),
 258         GATE(SBC3, "spi3", "pc_spi3", H(14)),
 259         GATE(I2C5, "i2c5", "pc_i2c5", H(15)),
 260         GATE(DSIA, "dsia", "dsia_mux", H(16)),
 261         GATE(MIPI, "hsi", "pc_hsi", H(18)),
 262         GATE(HDMI, "hdmi", "pc_hdmi", H(19)),
 263         GATE(CSI, "csi", "pllP_out3", H(20)),
 264         GATE(I2C2, "i2c2", "pc_i2c2", H(22)),
 265         GATE(UARTC, "uartc", "pc_uartc", H(23)),
 266         GATE(MIPI_CAL, "mipi_cal", "clk_m", H(24)),
 267         GATE(EMC, "emc", "pc_emc_2x", H(25)),
 268         GATE(USB2, "usb2", "clk_m", H(26)),
 269         GATE(USB3, "usb3", "clk_m", H(27)),
 270         GATE(VDE, "vde", "pc_vde", H(29)),
 271         GATE(BSEA, "bsea", "clk_m", H(30)),
 272         GATE(BSEV, "bsev", "clk_m", H(31)),
 273
 274         /* bank U  -> 64-95 */
 275         GATE(UARTD, "uartd", "pc_uartd", U(1)),
 276         GATE(I2C3, "i2c3", "pc_i2c3", U(3)),
 277         GATE(SBC4, "spi4", "pc_spi4", U(4)),
 278         GATE(SDMMC3, "sdmmc3", "pc_sdmmc3", U(5)),
 279         GATE(PCIE, "pcie", "clk_m", U(6)),
 280         GATE(OWR, "owr", "pc_owr", U(7)),
 281         GATE(AFI, "afi", "clk_m", U(8)),
 282         GATE(CSITE, "csite", "pc_csite", U(9)),
 283         /* GATE(AVPUCQ, "avpucq", clk_m, U(11)), */
 284         GATE(TRACE, "traceclkin", "pc_traceclkin", U(13)),
 285         GATE(SOC_THERM, "soc_therm", "pc_soc_therm", U(14)),
 286         GATE(DTV, "dtv", "clk_m", U(15)),
 287         GATE(I2CSLOW, "i2c_slow", "pc_i2c_slow", U(17)),
 288         GATE(DSIB, "dsib", "dsib_mux", U(18)),
 289         GATE(TSEC, "tsec", "pc_tsec", U(19)),
 290         /* GATE(IRAMA, "irama", "clk_m", U(20)), */
 291         /* GATE(IRAMB, "iramb", "clk_m", U(21)), */
 292         /* GATE(IRAMC, "iramc", "clk_m", U(22)), */
 293         /* GATE(IRAMD, "iramd", "clk_m", U(23)), */
 294         /* GATE(CRAM2, "cram2", "clk_m", U(24)), */
 295         GATE(XUSB_HOST, "xusb_core_host", "pc_xusb_core_host", U(25)),
 296         /* GATE(M_DOUBLER, "m_doubler", "clk_m", U(26)), */
 297         GATE(MSENC, "msenc", "pc_msenc", U(27)),
 298         GATE(CSUS, "sus_out", "clk_m", U(28)),
 299         /* GATE(DEVD2_OUT, "devd2_out", "clk_m", U(29)), */
 300         /* GATE(DEVD1_OUT, "devd1_out", "clk_m", U(30)), */
 301         GATE(XUSB_DEV, "xusb_core_dev", "pc_xusb_core_dev", U(31)),
 302
 303         /* bank V  -> 96-127 */
 304         /* GATE(CPUG, "cpug", "clk_m", V(0)), */
 305         /* GATE(CPULP, "cpuLP", "clk_m", V(1)), */
 306         GATE(MSELECT, "mselect", "pc_mselect", V(3)),
 307         GATE(TSENSOR, "tsensor", "pc_tsensor", V(4)),
 308         GATE(I2S3, "i2s3", "pc_i2s3", V(5)),
 309         GATE(I2S4, "i2s4", "pc_i2s4", V(6)),
 310         GATE(I2C4, "i2c4", "pc_i2c4", V(7)),
 311         GATE(SBC5, "spi5", "pc_spi5", V(8)),
 312         GATE(SBC6, "spi6", "pc_spi6", V(9)),
 313         GATE(D_AUDIO, "audio", "pc_audio", V(10)),
 314         GATE(APBIF, "apbif", "clk_m", V(11)),
 315         GATE(DAM0, "dam0", "pc_dam0", V(12)),
 316         GATE(DAM1, "dam1", "pc_dam1", V(13)),
 317         GATE(DAM2, "dam2",  "pc_dam2", V(14)),
 318         GATE(HDA2CODEC_2X, "hda2codec_2x", "pc_hda2codec_2x", V(15)),
 319         /* GATE(ATOMICS, "atomics", "clk_m", V(16)), */
 320         /* GATE(SPDIF_DOUBLER, "spdif_doubler", "clk_m", V(22)), */
 321         GATE(ACTMON, "actmon", "pc_actmon", V(23)),
 322         GATE(EXTERN1, "extperiph1", "pc_extperiph1", V(24)),
 323         GATE(EXTERN2, "extperiph2", "pc_extperiph2", V(25)),
 324         GATE(EXTERN3, "extperiph3", "pc_extperiph3", V(26)),
 325         GATE(SATA_OOB, "sata_oob", "pc_sata_oob", V(27)),
 326         GATE(SATA, "sata", "pc_sata", V(28)),
 327         GATE(HDA, "hda", "pc_hda", V(29)),
 328
 329         /* bank W   -> 128-159*/
 330         GATE(HDA2HDMI, "hda2hdmi", "clk_m", W(0)),
 331         GATE(SATA_COLD, "sata_cold", "clk_m", W(1)), /* Reset only */
 332         /* GATE(PCIERX0, "pcierx0", "clk_m", W(2)), */
 333         /* GATE(PCIERX1, "pcierx1", "clk_m", W(3)), */
 334         /* GATE(PCIERX2, "pcierx2", "clk_m", W(4)), */
 335         /* GATE(PCIERX3, "pcierx3", "clk_m", W(5)), */
 336         /* GATE(PCIERX4, "pcierx4", "clk_m", W(6)), */
 337         /* GATE(PCIERX5, "pcierx5", "clk_m", W(7)), */
 338         /* GATE(CEC, "cec", "clk_m", W(8)), */
 339         /* GATE(PCIE2_IOBIST, "pcie2_iobist", "clk_m", W(9)), */
 340         /* GATE(EMC_IOBIST, "emc_iobist", "clk_m", W(10)), */
 341         /* GATE(HDMI_IOBIST, "hdmi_iobist", "clk_m", W(11)), */
 342         /* GATE(SATA_IOBIST, "sata_iobist", "clk_m", W(12)), */
 343         /* GATE(MIPI_IOBIST, "mipi_iobist", "clk_m", W(13)), */
 344         GATE(XUSB_GATE, "xusb_gate", "clk_m", W(15)),
 345         GATE(CILAB, "cilab", "pc_cilab", W(16)),
 346         GATE(CILCD, "cilcd", "pc_cilcd", W(17)),
 347         GATE(CILE, "cile", "pc_cile", W(18)),
 348         GATE(DSIALP, "dsia_lp", "pc_dsia_lp", W(19)),
 349         GATE(DSIBLP, "dsib_lp", "pc_dsib_lp", W(20)),
 350         GATE(ENTROPY, "entropy", "pc_entropy", W(21)),
 351         GATE(AMX, "amx", "pc_amx", W(25)),
 352         GATE(ADX, "adx", "pc_adx", W(26)),
 353         GATE(DFLL_REF, "dvfs_ref", "pc_dvfs_ref", W(27)),
 354         GATE(DFLL_SOC, "dvfs_soc", "pc_dvfs_soc",  W(27)),
 355         GATE(XUSB_SS, "xusb_ss", "xusb_ss_mux", W(28)),
 356         /* GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", W(29)), */
 357
 358         /* bank X -> 160-191*/
 359         /* GATE(SPARE, "spare", "clk_m", X(0)), */
 360         /* GATE(CAM_MCLK, "CAM_MCLK", "clk_m", X(4)), */
 361         /* GATE(CAM_MCLK2, "CAM_MCLK2", "clk_m", X(5)), */
 362         GATE(I2C6, "i2c6", "pc_i2c6", X(6)),
 363         GATE(VIM2_CLK, "vim2_clk", "clk_m", X(11)),
 364         /* GATE(EMC_DLL, "emc_dll", "pc_emc_dll", X(14)), */
 365         GATE(HDMI_AUDIO, "hdmi_audio", "pc_hdmi_audio", X(16)),
 366         GATE(CLK72MHZ, "clk72mhz", "pc_clk72mhz", X(17)),
 367         GATE(VIC03, "vic", "pc_vic", X(18)),
 368         GATE(ADX1, "adx1", "pc_adx1", X(20)),
 369         GATE(DPAUX, "dpaux", "clk_m", X(21)),
 370         GATE(SOR0_LVDS, "sor0", "pc_sor0", X(22)),
 371         GATE(GPU, "gpu", "osc_div_clk", X(24)),
 372         GATE(AMX1, "amx1", "pc_amx1", X(26)),
 373 };
 374
 375 /* Peripheral clock clock */
 376 #define DCF_HAVE_MUX            0x0100 /* Block with multipexor */
 377 #define DCF_HAVE_ENA            0x0200 /* Block with enable bit */
 378 #define DCF_HAVE_DIV            0x0400 /* Block with divider */
 379
 380 /* Mark block with additional bits / functionality. */
 381 #define DCF_IS_MASK             0x00FF
 382 #define DCF_IS_UART             0x0001
 383 #define DCF_IS_VI               0x0002
 384 #define DCF_IS_HOST1X           0x0003
 385 #define DCF_IS_XUSB_SS          0x0004
 386 #define DCF_IS_EMC_DLL          0x0005
 387 #define DCF_IS_SATA             0x0006
 388 #define DCF_IS_VIC              0x0007
 389 #define DCF_IS_AUDIO            0x0008
 390 #define DCF_IS_SOR0             0x0009
 391 #define DCF_IS_EMC              0x000A
 392
 393 /* Basic pheripheral clock */
 394 #define PER_CLK(_id, cn, pl, r, diw, fiw, f)                            \
 395 {                                                                       \
 396         .clkdef.id = _id,                                               \
 397         .clkdef.name = cn,                                              \
 398         .clkdef.parent_names = pl,                                      \
 399         .clkdef.parent_cnt = nitems(pl),                                \
 400         .clkdef.flags = CLK_NODE_STATIC_STRINGS,                        \
 401         .base_reg = r,                                                  \
 402         .div_width = diw,                                               \
 403         .div_f_width = fiw,                                             \
 404         .flags = f,                                                     \
 405 }
 406
 407 /* Mux with fractional 8.1 divider. */
 408 #define CLK_8_1(id, cn, pl, r,  f)                                      \
 409         PER_CLK(id, cn, pl, r,  8, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
 410
 411 /* Mux with fractional 16.1 divider. */
 412 #define CLK16_1(id, cn, pl, r,  f)                                      \
 413         PER_CLK(id, cn, pl, r,  16, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
 414 /* Mux with integer 16bits divider. */
 415 #define CLK16_0(id, cn, pl, r,  f)                                      \
 416         PER_CLK(id, cn, pl, r,  16, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
 417 /* Mux wihout divider. */
 418 #define CLK_0_0(id, cn, pl, r,  f)                                      \
 419         PER_CLK(id, cn, pl, r,  0, 0, (f) | DCF_HAVE_MUX)
 420
 421 static struct periph_def periph_def[] = {
 422         CLK_8_1(0, "pc_i2s1", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S1, DCF_HAVE_ENA),
 423         CLK_8_1(0, "pc_i2s2", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA),
 424         CLK_8_1(0, "pc_spdif_out", mux_a_N_audio_N_p_N_clkm, CLK_SOURCE_SPDIF_OUT, 0),
 425         CLK_8_1(0, "pc_spdif_in", mux_p_c2_c_c3_m, CLK_SOURCE_SPDIF_IN, 0),
 426         CLK_8_1(0, "pc_pwm", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_PWM, 0),
 427         CLK_8_1(0, "pc_spi2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI2, 0),
 428         CLK_8_1(0, "pc_spi3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI3, 0),
 429         CLK16_0(0, "pc_i2c5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C5, 0),
 430         CLK16_0(0, "pc_i2c1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C1, 0),
 431         CLK_8_1(0, "pc_spi1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI1, 0),
 432         CLK_0_0(0, "pc_disp1", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP1, 0),
 433         CLK_0_0(0, "pc_disp2", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP2, 0),
 434         CLK_8_1(0, "pc_isp", mux_m_c_p_a_c2_c3_clkm_c4, CLK_SOURCE_ISP, 0),
 435         CLK_8_1(0, "pc_vi", mux_m_c2_c_c3_p_N_a_c4, CLK_SOURCE_VI, DCF_IS_VI),
 436         CLK_8_1(0, "pc_sdmmc1", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC1, 0),
 437         CLK_8_1(0, "pc_sdmmc2", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC2, 0),
 438         CLK_8_1(0, "pc_sdmmc4", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC4, 0),
 439         CLK_8_1(0, "pc_vfir", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VFIR, 0),
 440         CLK_8_1(0, "pc_hsi", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HSI, 0),
 441         CLK16_1(0, "pc_uarta", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTA, DCF_IS_UART),
 442         CLK16_1(0, "pc_uartb", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTB, DCF_IS_UART),
 443         CLK_8_1(0, "pc_host1x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HOST1X, DCF_IS_HOST1X),
 444         CLK_8_1(0, "pc_hdmi", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_HDMI, 0),
 445         CLK16_0(0, "pc_i2c2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C2, 0),
 446         CLK_8_1(0, "pc_emc_2x", mux_m_c_p_clkm_mud_c2_c3_cud, CLK_SOURCE_EMC, DCF_IS_EMC),
 447         CLK16_1(0, "pc_uartc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTC, DCF_IS_UART),
 448         CLK_8_1(0, "pc_vi_sensor", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR, 0),
 449         CLK_8_1(0, "pc_spi4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI4, 0),
 450         CLK16_0(0, "pc_i2c3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C3, 0),
 451         CLK_8_1(0, "pc_sdmmc3", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC3, 0),
 452         CLK16_1(0, "pc_uartd", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTD, DCF_IS_UART),
 453         CLK_8_1(0, "pc_vde", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VDE, 0),
 454         CLK_8_1(0, "pc_owr", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_OWR, 0),
 455         CLK_8_1(0, "pc_snor", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_NOR, 0),
 456         CLK_8_1(0, "pc_csite", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_CSITE, 0),
 457         CLK_8_1(0, "pc_i2s0", mux_a_N_audio0_N_p_N_clkm, CLK_SOURCE_I2S0, 0),
 458 /* DTV xxx */
 459         CLK_8_1(0, "pc_msenc", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_MSENC, 0),
 460         CLK_8_1(0, "pc_tsec", mux_p_c2_c_c3_m_a_clkm, CLK_SOURCE_TSEC, 0),
 461 /* SPARE2 */
 462
 463
 464         CLK_8_1(0, "pc_mselect", mux_p_c2_c_c3_m_clks_clkm, CLK_SOURCE_MSELECT, 0),
 465         CLK_8_1(0, "pc_tsensor", mux_p_c2_c_c3_clkm_N_clks, CLK_SOURCE_TSENSOR, 0),
 466         CLK_8_1(0, "pc_i2s3", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA),
 467         CLK_8_1(0, "pc_i2s4", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA),
 468         CLK16_0(0, "pc_i2c4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C4, 0),
 469         CLK_8_1(0, "pc_spi5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI5, 0),
 470         CLK_8_1(0, "pc_spi6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI6, 0),
 471         CLK_8_1(0, "pc_audio", mux_sep_audio, CLK_SOURCE_AUDIO, DCF_IS_AUDIO),
 472         CLK_8_1(0, "pc_dam0", mux_sep_audio, CLK_SOURCE_DAM0, DCF_IS_AUDIO),
 473         CLK_8_1(0, "pc_dam1", mux_sep_audio, CLK_SOURCE_DAM1, DCF_IS_AUDIO),
 474         CLK_8_1(0, "pc_dam2",  mux_sep_audio, CLK_SOURCE_DAM2, DCF_IS_AUDIO),
 475         CLK_8_1(0, "pc_hda2codec_2x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA2CODEC_2X, 0),
 476         CLK_8_1(0, "pc_actmon", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_ACTMON, 0),
 477         CLK_8_1(0, "pc_extperiph1", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH1, 0),
 478         CLK_8_1(0, "pc_extperiph2", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH2,  0),
 479         CLK_8_1(0, "pc_extperiph3", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH3, 0),
 480         CLK_8_1(0, "pc_i2c_slow", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_I2C_SLOW, 0),
 481 /* SYS */
 482         CLK_8_1(0, "pc_sor0", mux_p_m_d_a_c_d2_clkm,  CLK_SOURCE_SOR0, DCF_IS_SOR0),
 483         CLK_8_1(0, "pc_sata_oob", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA_OOB, 0),
 484         CLK_8_1(0, "pc_sata", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA, DCF_IS_SATA),
 485         CLK_8_1(0, "pc_hda", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA, 0),
 486         CLK_8_1(TEGRA124_CLK_XUSB_HOST_SRC,
 487                    "pc_xusb_core_host", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_HOST, 0),
 488         CLK_8_1(TEGRA124_CLK_XUSB_FALCON_SRC,
 489                    "pc_xusb_falcon", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_FALCON, 0),
 490         CLK_8_1(TEGRA124_CLK_XUSB_FS_SRC,
 491                    "pc_xusb_fs", mux_clkm_N_u48_N_p_N_u480, CLK_SOURCE_XUSB_FS, 0),
 492         CLK_8_1(TEGRA124_CLK_XUSB_DEV_SRC,
 493                    "pc_xusb_core_dev", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_DEV, 0),
 494         CLK_8_1(TEGRA124_CLK_XUSB_SS_SRC,
 495                    "pc_xusb_ss", mux_clkm_refe_clks_u480_c_c2_c3_oscdiv, CLK_SOURCE_XUSB_SS, DCF_IS_XUSB_SS),
 496         CLK_8_1(0, "pc_cilab", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILAB, 0),
 497         CLK_8_1(0, "pc_cilcd", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILCD, 0),
 498         CLK_8_1(0, "pc_cile", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILE, 0),
 499         CLK_8_1(0, "pc_dsia_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIA_LP, 0),
 500         CLK_8_1(0, "pc_dsib_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIB_LP, 0),
 501         CLK_8_1(0, "pc_entropy", mux_p_clkm_clks_E, CLK_SOURCE_ENTROPY, 0),
 502         CLK_8_1(0, "pc_dvfs_ref", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA),
 503         CLK_8_1(0, "pc_dvfs_soc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA),
 504         CLK_8_1(0, "pc_traceclkin", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_TRACECLKIN, 0),
 505         CLK_8_1(0, "pc_adx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX, DCF_HAVE_ENA),
 506         CLK_8_1(0, "pc_amx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX, DCF_HAVE_ENA),
 507         CLK_8_1(0, "pc_emc_latency", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_LATENCY, 0),
 508         CLK_8_1(0, "pc_soc_therm", mux_m_c_p_a_c2_c3, CLK_SOURCE_SOC_THERM, 0),
 509         CLK_8_1(0, "pc_vi_sensor2", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR2, 0),
 510         CLK16_0(0, "pc_i2c6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C6, 0),
 511         CLK_8_1(0, "pc_emc_dll", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_DLL, DCF_IS_EMC_DLL),
 512         CLK_8_1(0, "pc_hdmi_audio", mux_p_c_c2_clkm, CLK_SOURCE_HDMI_AUDIO, 0),
 513         CLK_8_1(0, "pc_clk72mhz", mux_p_c_c2_clkm, CLK_SOURCE_CLK72MHZ, 0),
 514         CLK_8_1(0, "pc_adx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX1, DCF_HAVE_ENA),
 515         CLK_8_1(0, "pc_amx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX1, DCF_HAVE_ENA),
 516         CLK_8_1(0, "pc_vic", mux_m_c_p_a_c2_c3_clkm, CLK_SOURCE_VIC, DCF_IS_VIC),
 517 };
 518
 519 static int periph_init(struct clknode *clk, device_t dev);
 520 static int periph_recalc(struct clknode *clk, uint64_t *freq);
 521 static int periph_set_freq(struct clknode *clk, uint64_t fin,
 522     uint64_t *fout, int flags, int *stop);
 523 static int periph_set_mux(struct clknode *clk, int idx);
 524
 525 struct periph_sc {
 526         device_t                clkdev;
 527         uint32_t                base_reg;
 528         uint32_t                div_shift;
 529         uint32_t                div_width;
 530         uint32_t                div_mask;
 531         uint32_t                div_f_width;
 532         uint32_t                div_f_mask;
 533         uint32_t                flags;
 534
 535         uint32_t                divider;
 536         int                     mux;
 537 };
 538
 539 static clknode_method_t periph_methods[] = {
 540         /* Device interface */
 541         CLKNODEMETHOD(clknode_init,             periph_init),
 542         CLKNODEMETHOD(clknode_recalc_freq,      periph_recalc),
 543         CLKNODEMETHOD(clknode_set_freq,         periph_set_freq),
 544         CLKNODEMETHOD(clknode_set_mux,          periph_set_mux),
 545         CLKNODEMETHOD_END
 546 };
 547 DEFINE_CLASS_1(tegra124_periph, tegra124_periph_class, periph_methods,
 548    sizeof(struct periph_sc), clknode_class);
 549
 550 static int
 551 periph_init(struct clknode *clk, device_t dev)
 552 {
 553         struct periph_sc *sc;
 554         uint32_t reg;
 555         sc = clknode_get_softc(clk);
 556
 557         DEVICE_LOCK(sc);
 558         if (sc->flags & DCF_HAVE_ENA)
 559                 MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK);
 560
 561         RD4(sc, sc->base_reg, &reg);
 562         DEVICE_UNLOCK(sc);
 563
 564         /* Stnadard mux. */
 565         if (sc->flags & DCF_HAVE_MUX)
 566                 sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK;
 567         else
 568                 sc->mux = 0;
 569         if (sc->flags & DCF_HAVE_DIV)
 570                 sc->divider = (reg & sc->div_mask) + 2;
 571         else
 572                 sc->divider = 1;
 573         if ((sc->flags & DCF_IS_MASK) == DCF_IS_UART) {
 574                 if (!(reg & PERLCK_UDIV_DIS))
 575                         sc->divider = 2;
 576         }
 577
 578         /* AUDIO MUX */
 579         if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) {
 580                 if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) {
 581                         sc->mux = 8 +
 582                             ((reg >> PERLCK_AMUX_SHIFT) & PERLCK_MUX_MASK);
 583                 }
 584         }
 585         clknode_init_parent_idx(clk, sc->mux);
 586         return(0);
 587 }
 588
 589 static int
 590 periph_set_mux(struct clknode *clk, int idx)
 591 {
 592         struct periph_sc *sc;
 593         uint32_t reg;
 594
 595
 596         sc = clknode_get_softc(clk);
 597         if (!(sc->flags & DCF_HAVE_MUX))
 598                 return (ENXIO);
 599
 600         sc->mux = idx;
 601         DEVICE_LOCK(sc);
 602         RD4(sc, sc->base_reg, &reg);
 603         reg &= ~(PERLCK_MUX_MASK << PERLCK_MUX_SHIFT);
 604         if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) {
 605                 reg &= ~PERLCK_AMUX_DIS;
 606                 reg &= ~(PERLCK_MUX_MASK << PERLCK_AMUX_SHIFT);
 607
 608                 if (idx <= 7) {
 609                         reg |= idx << PERLCK_MUX_SHIFT;
 610                 } else {
 611                         reg |= 7 << PERLCK_MUX_SHIFT;
 612                         reg |= (idx - 8) << PERLCK_AMUX_SHIFT;
 613                 }
 614         } else {
 615                 reg |= idx << PERLCK_MUX_SHIFT;
 616         }
 617         WR4(sc, sc->base_reg, reg);
 618         DEVICE_UNLOCK(sc);
 619
 620         return(0);
 621 }
 622
 623 static int
 624 periph_recalc(struct clknode *clk, uint64_t *freq)
 625 {
 626         struct periph_sc *sc;
 627         uint32_t reg;
 628
 629         sc = clknode_get_softc(clk);
 630
 631         if (sc->flags & DCF_HAVE_DIV) {
 632                 DEVICE_LOCK(sc);
 633                 RD4(sc, sc->base_reg, &reg);
 634                 DEVICE_UNLOCK(sc);
 635                 *freq = (*freq << sc->div_f_width) / sc->divider;
 636         }
 637         return (0);
 638 }
 639
 640 static int
 641 periph_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
 642    int flags, int *stop)
 643 {
 644         struct periph_sc *sc;
 645         uint64_t tmp, divider;
 646
 647         sc = clknode_get_softc(clk);
 648         if (!(sc->flags & DCF_HAVE_DIV)) {
 649                 *stop = 0;
 650                 return (0);
 651         }
 652
 653         tmp = fin << sc->div_f_width;
 654         divider = tmp / *fout;
 655         if ((tmp % *fout) != 0)
 656                 divider++;
 657
 658         if (divider < (1 << sc->div_f_width))
 659                  divider = 1 << (sc->div_f_width - 1);
 660
 661         if (flags & CLK_SET_DRYRUN) {
 662                 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
 663                     (*fout != (tmp / divider)))
 664                         return (ERANGE);
 665         } else {
 666                 DEVICE_LOCK(sc);
 667                 MD4(sc, sc->base_reg, sc->div_mask,
 668                     (divider - (1 << sc->div_f_width)));
 669                 DEVICE_UNLOCK(sc);
 670                 sc->divider = divider;
 671         }
 672         *fout = tmp / divider;
 673         *stop = 1;
 674         return (0);
 675 }
 676
 677 static int
 678 periph_register(struct clkdom *clkdom, struct periph_def *clkdef)
 679 {
 680         struct clknode *clk;
 681         struct periph_sc *sc;
 682
 683         clk = clknode_create(clkdom, &tegra124_periph_class, &clkdef->clkdef);
 684         if (clk == NULL)
 685                 return (1);
 686
 687         sc = clknode_get_softc(clk);
 688         sc->clkdev = clknode_get_device(clk);
 689         sc->base_reg = clkdef->base_reg;
 690         sc->div_width = clkdef->div_width;
 691         sc->div_mask = (1 <<clkdef->div_width) - 1;
 692         sc->div_f_width = clkdef->div_f_width;
 693         sc->div_f_mask = (1 <<clkdef->div_f_width) - 1;
 694         sc->flags = clkdef->flags;
 695
 696         clknode_register(clkdom, clk);
 697         return (0);
 698 }
 699
 700 /* -------------------------------------------------------------------------- */
 701 static int pgate_init(struct clknode *clk, device_t dev);
 702 static int pgate_set_gate(struct clknode *clk, bool enable);
 703
 704 struct pgate_sc {
 705         device_t                clkdev;
 706         uint32_t                idx;
 707         uint32_t                flags;
 708         uint32_t                enabled;
 709
 710 };
 711
 712 static clknode_method_t pgate_methods[] = {
 713         /* Device interface */
 714         CLKNODEMETHOD(clknode_init,             pgate_init),
 715         CLKNODEMETHOD(clknode_set_gate,         pgate_set_gate),
 716         CLKNODEMETHOD_END
 717 };
 718 DEFINE_CLASS_1(tegra124_pgate, tegra124_pgate_class, pgate_methods,
 719    sizeof(struct pgate_sc), clknode_class);
 720
 721 static uint32_t
 722 get_enable_reg(int idx)
 723 {
 724         KASSERT(idx / 32 < nitems(clk_enable_reg),
 725             ("Invalid clock index for enable: %d", idx));
 726         return (clk_enable_reg[idx / 32]);
 727 }
 728
 729 static uint32_t
 730 get_reset_reg(int idx)
 731 {
 732         KASSERT(idx / 32 < nitems(clk_reset_reg),
 733             ("Invalid clock index for reset: %d", idx));
 734         return (clk_reset_reg[idx / 32]);
 735 }
 736
 737 static int
 738 pgate_init(struct clknode *clk, device_t dev)
 739 {
 740         struct pgate_sc *sc;
 741         uint32_t ena_reg, rst_reg, mask;
 742
 743         sc = clknode_get_softc(clk);
 744         mask = 1 << (sc->idx % 32);
 745
 746         DEVICE_LOCK(sc);
 747         RD4(sc, get_enable_reg(sc->idx), &ena_reg);
 748         RD4(sc, get_reset_reg(sc->idx), &rst_reg);
 749         DEVICE_UNLOCK(sc);
 750
 751         sc->enabled = ena_reg & mask ? 1 : 0;
 752         clknode_init_parent_idx(clk, 0);
 753
 754         return(0);
 755 }
 756
 757 static int
 758 pgate_set_gate(struct clknode *clk, bool enable)
 759 {
 760         struct pgate_sc *sc;
 761         uint32_t reg, mask, base_reg;
 762
 763         sc = clknode_get_softc(clk);
 764         mask = 1 << (sc->idx % 32);
 765         sc->enabled = enable;
 766         base_reg = get_enable_reg(sc->idx);
 767
 768         DEVICE_LOCK(sc);
 769         MD4(sc, base_reg, mask, enable ? mask : 0);
 770         RD4(sc, base_reg, &reg);
 771         DEVICE_UNLOCK(sc);
 772
 773         DELAY(2);
 774         return(0);
 775 }
 776
 777 int
 778 tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, bool reset)
 779 {
 780         uint32_t reg, mask, reset_reg;
 781
 782         mask = 1 << (idx % 32);
 783         reset_reg = get_reset_reg(idx);
 784
 785         CLKDEV_DEVICE_LOCK(sc->dev);
 786         CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0);
 787         CLKDEV_READ_4(sc->dev, reset_reg, &reg);
 788         CLKDEV_DEVICE_UNLOCK(sc->dev);
 789
 790         return(0);
 791 }
 792
 793 static int
 794 pgate_register(struct clkdom *clkdom, struct pgate_def *clkdef)
 795 {
 796         struct clknode *clk;
 797         struct pgate_sc *sc;
 798
 799         clk = clknode_create(clkdom, &tegra124_pgate_class, &clkdef->clkdef);
 800         if (clk == NULL)
 801                 return (1);
 802
 803         sc = clknode_get_softc(clk);
 804         sc->clkdev = clknode_get_device(clk);
 805         sc->idx = clkdef->idx;
 806         sc->flags = clkdef->flags;
 807
 808         clknode_register(clkdom, clk);
 809         return (0);
 810 }
 811
 812 void
 813 tegra124_periph_clock(struct tegra124_car_softc *sc)
 814 {
 815         int i, rv;
 816
 817         for (i = 0; i <  nitems(periph_def); i++) {
 818                 rv = periph_register(sc->clkdom, &periph_def[i]);
 819                 if (rv != 0)
 820                         panic("tegra124_periph_register failed");
 821         }
 822         for (i = 0; i <  nitems(pgate_def); i++) {
 823                 rv = pgate_register(sc->clkdom, &pgate_def[i]);
 824                 if (rv != 0)
 825                         panic("tegra124_pgate_register failed");
 826         }
 827
 828 }