sys/arm/nvidia/tegra124/tegra124_clk_per.c

   1 /*-
   2  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/lock.h>
  34 #include <sys/mutex.h>
  35 #include <sys/rman.h>
  36
  37 #include <machine/bus.h>
  38
  39 #include <dev/extres/clk/clk.h>
  40
  41 #include <gnu/dts/include/dt-bindings/clock/tegra124-car.h>
  42 #include "tegra124_car.h"
  43
  44 /* Bits in base register. */
  45 #define PERLCK_AMUX_MASK        0x0F
  46 #define PERLCK_AMUX_SHIFT       16
  47 #define PERLCK_AMUX_DIS         (1 << 20)
  48 #define PERLCK_UDIV_DIS         (1 << 24)
  49 #define PERLCK_ENA_MASK         (1 << 28)
  50 #define PERLCK_MUX_SHIFT        29
  51 #define PERLCK_MUX_MASK         0x07
  52
  53
  54 struct periph_def {
  55         struct clknode_init_def clkdef;
  56         uint32_t                base_reg;
  57         uint32_t                div_width;
  58         uint32_t                div_mask;
  59         uint32_t                div_f_width;
  60         uint32_t                div_f_mask;
  61         uint32_t                flags;
  62 };
  63
  64 struct pgate_def {
  65         struct clknode_init_def clkdef;
  66         uint32_t                idx;
  67         uint32_t                flags;
  68 };
  69 #define PLIST(x) static const char *x[]
  70
  71 #define GATE(_id, cname, plist, _idx)                                   \
  72 {                                                                       \
  73         .clkdef.id = TEGRA124_CLK_##_id,                                \
  74         .clkdef.name = cname,                                           \
  75         .clkdef.parent_names = (const char *[]){plist},                 \
  76         .clkdef.parent_cnt = 1,                                         \
  77         .clkdef.flags = CLK_NODE_STATIC_STRINGS,                        \
  78         .idx = _idx,                                                    \
  79         .flags = 0,                                                     \
  80 }
  81
  82 /* Sources for multiplexors. */
  83 PLIST(mux_a_N_audio_N_p_N_clkm) =
  84     {"pllA_out0", NULL, "audio",  NULL,
  85      "pllP_out0", NULL, "clk_m"};
  86 PLIST(mux_a_N_audio0_N_p_N_clkm) =
  87     {"pllA_out0", NULL, "audio0", NULL,
  88      "pllP_out0", NULL, "clk_m"};
  89 PLIST(mux_a_N_audio1_N_p_N_clkm) =
  90     {"pllA_out0", NULL, "audio1", NULL,
  91      "pllP_out0", NULL, "clk_m"};
  92 PLIST(mux_a_N_audio2_N_p_N_clkm) =
  93     {"pllA_out0", NULL, "audio2", NULL,
  94      "pllP_out0", NULL, "clk_m"};
  95 PLIST(mux_a_N_audio3_N_p_N_clkm) =
  96     {"pllA_out0", NULL, "audio3", NULL,
  97      "pllP_out0", NULL, "clk_m"};
  98 PLIST(mux_a_N_audio4_N_p_N_clkm) =
  99     {"pllA_out0", NULL, "audio4", NULL,
 100      "pllP_out0", NULL, "clk_m"};
 101 PLIST(mux_a_clks_p_clkm_e) =
 102     {"pllA_out0", "clk_s", "pllP_out0",
 103      "clk_m", "pllE_out0"};
 104 PLIST(mux_a_c2_c_c3_p_N_clkm) =
 105     {"pllA_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 106      "pllP_out0", NULL, "clk_m"};
 107
 108 PLIST(mux_m_c_p_a_c2_c3) =
 109     {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0",
 110      "pllC2_out0", "pllC3_out0"};
 111 PLIST(mux_m_c_p_a_c2_c3_clkm) =
 112     {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0",
 113      "pllC2_out0", "pllC3_out0", "clk_m"};
 114 PLIST(mux_m_c_p_a_c2_c3_clkm_c4) =
 115     {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0",
 116      "pllC2_out0", "pllC3_out0", "clk_m", "pllC4_out0"};
 117 PLIST(mux_m_c_p_clkm_mud_c2_c3) =
 118     {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m",
 119      "pllM_UD", "pllC2_out0", "pllC3_out0"};
 120 PLIST(mux_m_c2_c_c3_p_N_a) =
 121     {"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 122      "pllP_out0", NULL, "pllA_out0"};
 123 PLIST(mux_m_c2_c_c3_p_N_a_c4) =
 124     {"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 125      NULL, "pllA_out0", "pllC4_out0"};
 126
 127 PLIST(mux_p_N_c_N_N_N_clkm) =
 128     {"pllP_out0", NULL, "pllC_out0", NULL,
 129      NULL, NULL, "clk_m"};
 130 PLIST(mux_p_N_c_N_m_N_clkm) =
 131     {"pllP_out0", NULL, "pllC_out0", NULL,
 132      "pllM_out0", NULL, "clk_m"};
 133 PLIST(mux_p_c_c2_clkm) =
 134     {"pllP_out0", "pllC_out0", "pllC2_out0", "clk_m"};
 135 PLIST(mux_p_c2_c_c3_m) =
 136     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 137      "pllM_out0"};
 138 PLIST(mux_p_c2_c_c3_m_N_clkm) =
 139     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 140      "pllM_out0", NULL, "clk_m"};
 141 PLIST(mux_p_c2_c_c3_m_e_clkm) =
 142     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 143      "pllM_out0", "pllE_out0", "clk_m"};
 144 PLIST(mux_p_c2_c_c3_m_a_clkm) =
 145     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 146      "pllM_out0", "pllA_out0", "clk_m"};
 147 PLIST(mux_p_c2_c_c3_m_clks_clkm) =
 148     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 149      "pllM_out0", "clk_s", "clk_m"};
 150 PLIST(mux_p_c2_c_c3_clks_N_clkm) =
 151     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 152      "clk_s", NULL, "clk_m"};
 153 PLIST(mux_p_c2_c_c3_clkm_N_clks) =
 154     {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 155      "clk_m", NULL, "clk_s"};
 156 PLIST(mux_p_clkm_clks_E) =
 157     {"pllP_out0", "clk_m", "clk_s", "pllE_out0"};
 158 PLIST(mux_p_m_d_a_c_d2_clkm) =
 159     {"pllP_out0", "pllM_out0", "pllD_out0", "pllA_out0",
 160      "pllC_out0", "pllD2_out0", "clk_m"};
 161
 162 PLIST(mux_clkm_N_u48_N_p_N_u480) =
 163     {"clk_m", NULL, "pllU_48", NULL,
 164      "pllP_out0", NULL, "pllU_480"};
 165 PLIST(mux_clkm_p_c2_c_c3_refre) =
 166     {"clk_m", "pllP_out0", "pllC2_out0", "pllC_out0",
 167      "pllC3_out0", "pllREFE_out"};
 168 PLIST(mux_clkm_refe_clks_u480_c_c2_c3_oscdiv) =
 169     {"clk_m", "pllREFE_out", "clk_s", "pllU_480",
 170      "pllC_out0", "pllC2_out0", "pllC3_out0", "osc_div_clk"};
 171
 172 PLIST(mux_sep_audio) =
 173    {"pllA_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
 174     "pllP_out0", NULL, "clk_m", NULL,
 175     "spdif_in", "i2s0", "i2s1", "i2s2",
 176     "i2s4", "pllA_out0", "ext_vimclk"};
 177
 178 static uint32_t clk_enabale_reg[] = {
 179         CLK_OUT_ENB_L,
 180         CLK_OUT_ENB_H,
 181         CLK_OUT_ENB_U,
 182         CLK_OUT_ENB_V,
 183         CLK_OUT_ENB_W,
 184         CLK_OUT_ENB_X,
 185 };
 186
 187 static uint32_t clk_reset_reg[] = {
 188         RST_DEVICES_L,
 189         RST_DEVICES_H,
 190         RST_DEVICES_U,
 191         RST_DEVICES_V,
 192         RST_DEVICES_W,
 193         RST_DEVICES_X,
 194 };
 195
 196 #define L(n)  ((0 * 32) + (n))
 197 #define H(n)  ((1 * 32) + (n))
 198 #define U(n)  ((2 * 32) + (n))
 199 #define V(n)  ((3 * 32) + (n))
 200 #define W(n)  ((4 * 32) + (n))
 201 #define X(n)  ((5 * 32) + (n))
 202
 203 static struct pgate_def pgate_def[] = {
 204         /* bank L ->  0-31 */
 205         /* GATE(CPU, "cpu", "clk_m", L(0)), */
 206         GATE(ISPB, "ispb", "clk_m", L(3)),
 207         GATE(RTC, "rtc", "clk_s", L(4)),
 208         GATE(TIMER, "timer", "clk_m", L(5)),
 209         GATE(UARTA, "uarta", "pc_uarta" , L(6)),
 210         GATE(UARTB, "uartb", "pc_uartb", L(7)),
 211         GATE(VFIR, "vfir", "pc_vfir", L(7)),
 212         /* GATE(GPIO, "gpio", "clk_m", L(8)), */
 213         GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)),
 214         GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)),
 215         GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)),
 216         GATE(I2S1, "i2s1", "pc_i2s1", L(11)),
 217         GATE(I2C1, "i2c1", "pc_i2c1", L(12)),
 218         GATE(SDMMC1, "sdmmc1", "pc_sdmmc1", L(14)),
 219         GATE(SDMMC4, "sdmmc4", "pc_sdmmc4", L(15)),
 220         GATE(PWM, "pwm", "pc_pwm", L(17)),
 221         GATE(I2S2, "i2s2", "pc_i2s2", L(18)),
 222         GATE(VI, "vi", "pc_vi", L(20)),
 223         GATE(USBD, "usbd", "clk_m", L(22)),
 224         GATE(ISP, "isp", "pc_isp", L(23)),
 225         GATE(DISP2, "disp2", "pc_disp2", L(26)),
 226         GATE(DISP1, "disp1", "pc_disp1", L(27)),
 227         GATE(HOST1X, "host1x", "pc_host1x", L(28)),
 228         GATE(VCP, "vcp", "clk_m", L(29)),
 229         GATE(I2S0, "i2s0", "pc_i2s0", L(30)),
 230         /* GATE(CACHE2, "ccache2", "clk_m", L(31)), */
 231
 232         /* bank H -> 32-63 */
 233         GATE(MC, "mem", "clk_m", H(0)),
 234         /* GATE(AHBDMA, "ahbdma", "clk_m", H(1)), */
 235         GATE(APBDMA, "apbdma", "clk_m", H(2)),
 236         GATE(KBC, "kbc", "clk_s", H(4)),
 237         /* GATE(STAT_MON, "stat_mon", "clk_s", H(5)), */
 238         /* GATE(PMC, "pmc", "clk_s", H(6)), */
 239         GATE(FUSE, "fuse", "clk_m", H(7)),
 240         GATE(KFUSE, "kfuse", "clk_m", H(8)),
 241         GATE(SBC1, "spi1", "pc_spi1", H(9)),
 242         GATE(NOR, "snor", "pc_snor", H(10)),
 243         /* GATE(JTAG2TBC, "jtag2tbc", "clk_m", H(11)), */
 244         GATE(SBC2, "spi2", "pc_spi2", H(12)),
 245         GATE(SBC3, "spi3", "pc_spi3", H(14)),
 246         GATE(I2C5, "i2c5", "pc_i2c5", H(15)),
 247         GATE(DSIA, "dsia", "dsia_mux", H(16)),
 248         GATE(MIPI, "hsi", "pc_hsi", H(18)),
 249         GATE(HDMI, "hdmi", "pc_hdmi", H(19)),
 250         GATE(CSI, "csi", "pllP_out3", H(20)),
 251         GATE(I2C2, "i2c2", "pc_i2c2", H(22)),
 252         GATE(UARTC, "uartc", "pc_uartc", H(23)),
 253         GATE(MIPI_CAL, "mipi_cal", "clk_m", H(24)),
 254         GATE(EMC, "emc", "emc_mux", H(25)),
 255         GATE(USB2, "usb2", "clk_m", H(26)),
 256         GATE(USB3, "usb3", "clk_m", H(27)),
 257         GATE(VDE, "vde", "pc_vde", H(29)),
 258         GATE(BSEA, "bsea", "clk_m", H(30)),
 259         GATE(BSEV, "bsev", "clk_m", H(31)),
 260
 261         /* bank U  -> 64-95 */
 262         GATE(UARTD, "uartd", "pc_uartd", U(1)),
 263         GATE(I2C3, "i2c3", "pc_i2c3", U(3)),
 264         GATE(SBC4, "spi4", "pc_spi4", U(4)),
 265         GATE(SDMMC3, "sdmmc3", "pc_sdmmc3", U(5)),
 266         GATE(PCIE, "pcie", "clk_m", U(6)),
 267         GATE(OWR, "owr", "pc_owr", U(7)),
 268         GATE(AFI, "afi", "clk_m", U(8)),
 269         GATE(CSITE, "csite", "pc_csite", U(9)),
 270         /* GATE(AVPUCQ, "avpucq", clk_m, U(11)), */
 271         GATE(TRACE, "traceclkin", "pc_traceclkin", U(13)),
 272         GATE(SOC_THERM, "soc_therm", "pc_soc_therm", U(14)),
 273         GATE(DTV, "dtv", "clk_m", U(15)),
 274         GATE(I2CSLOW, "i2c_slow", "pc_i2c_slow", U(17)),
 275         GATE(DSIB, "dsib", "dsib_mux", U(18)),
 276         GATE(TSEC, "tsec", "pc_tsec", U(19)),
 277         /* GATE(IRAMA, "irama", "clk_m", U(20)), */
 278         /* GATE(IRAMB, "iramb", "clk_m", U(21)), */
 279         /* GATE(IRAMC, "iramc", "clk_m", U(22)), */
 280         /* GATE(IRAMD, "iramd", "clk_m", U(23)), */
 281         /* GATE(CRAM2, "cram2", "clk_m", U(24)), */
 282         GATE(XUSB_HOST, "xusb_core_host", "pc_xusb_core_host", U(25)),
 283         /* GATE(M_DOUBLER, "m_doubler", "clk_m", U(26)), */
 284         GATE(MSENC, "msenc", "pc_msenc", U(27)),
 285         GATE(CSUS, "sus_out", "clk_m", U(28)),
 286         /* GATE(DEVD2_OUT, "devd2_out", "clk_m", U(29)), */
 287         /* GATE(DEVD1_OUT, "devd1_out", "clk_m", U(30)), */
 288         GATE(XUSB_DEV_SRC, "xusb_core_dev", "pc_xusb_core_dev", U(31)),
 289
 290         /* bank V  -> 96-127 */
 291         /* GATE(CPUG, "cpug", "clk_m", V(0)), */
 292         /* GATE(CPULP, "cpuLP", "clk_m", V(1)), */
 293         GATE(MSELECT, "mselect", "pc_mselect", V(3)),
 294         GATE(TSENSOR, "tsensor", "pc_tsensor", V(4)),
 295         GATE(I2S3, "i2s3", "pc_i2s3", V(5)),
 296         GATE(I2S4, "i2s4", "pc_i2s4", V(6)),
 297         GATE(I2C4, "i2c4", "pc_i2c4", V(7)),
 298         GATE(SBC5, "spi5", "pc_spi5", V(8)),
 299         GATE(SBC6, "spi6", "pc_spi6", V(9)),
 300         GATE(D_AUDIO, "audio", "pc_audio", V(10)),
 301         GATE(APBIF, "apbif", "clk_m", V(11)),
 302         GATE(DAM0, "dam0", "pc_dam0", V(12)),
 303         GATE(DAM1, "dam1", "pc_dam1", V(13)),
 304         GATE(DAM2, "dam2",  "pc_dam2", V(14)),
 305         GATE(HDA2CODEC_2X, "hda2codec_2x", "pc_hda2codec_2x", V(15)),
 306         /* GATE(ATOMICS, "atomics", "clk_m", V(16)), */
 307         /* GATE(SPDIF_DOUBLER, "spdif_doubler", "clk_m", V(22)), */
 308         GATE(ACTMON, "actmon", "pc_actmon", V(23)),
 309         GATE(EXTERN1, "extperiph1", "pc_extperiph1", V(24)),
 310         GATE(EXTERN2, "extperiph2", "pc_extperiph2", V(25)),
 311         GATE(EXTERN3, "extperiph3", "pc_extperiph3", V(26)),
 312         GATE(SATA_OOB, "sata_oob", "pc_sata_oob", V(27)),
 313         GATE(SATA, "sata", "pc_sata", V(28)),
 314         GATE(HDA, "hda", "pc_hda", V(29)),
 315
 316         /* bank W   -> 128-159*/
 317         GATE(HDA2HDMI, "hda2hdmi", "clk_m", W(0)),
 318         GATE(SATA_COLD, "sata_cold", "clk_m", W(1)), /* Reset only */
 319         /* GATE(PCIERX0, "pcierx0", "clk_m", W(2)), */
 320         /* GATE(PCIERX1, "pcierx1", "clk_m", W(3)), */
 321         /* GATE(PCIERX2, "pcierx2", "clk_m", W(4)), */
 322         /* GATE(PCIERX3, "pcierx3", "clk_m", W(5)), */
 323         /* GATE(PCIERX4, "pcierx4", "clk_m", W(6)), */
 324         /* GATE(PCIERX5, "pcierx5", "clk_m", W(7)), */
 325         /* GATE(CEC, "cec", "clk_m", W(8)), */
 326         /* GATE(PCIE2_IOBIST, "pcie2_iobist", "clk_m", W(9)), */
 327         /* GATE(EMC_IOBIST, "emc_iobist", "clk_m", W(10)), */
 328         /* GATE(HDMI_IOBIST, "hdmi_iobist", "clk_m", W(11)), */
 329         /* GATE(SATA_IOBIST, "sata_iobist", "clk_m", W(12)), */
 330         /* GATE(MIPI_IOBIST, "mipi_iobist", "clk_m", W(13)), */
 331         /* GATE(XUSB_IOBIST, "xusb_iobist", "clk_m", W(15)), */
 332         GATE(CILAB, "cilab", "pc_cilab", W(16)),
 333         GATE(CILCD, "cilcd", "pc_cilcd", W(17)),
 334         GATE(CILE, "cile", "pc_cile", W(18)),
 335         GATE(DSIALP, "dsia_lp", "pc_dsia_lp", W(19)),
 336         GATE(DSIBLP, "dsib_lp", "pc_dsib_lp", W(20)),
 337         GATE(ENTROPY, "entropy", "pc_entropy", W(21)),
 338         GATE(AMX, "amx", "pc_amx", W(25)),
 339         GATE(ADX, "adx", "pc_adx", W(26)),
 340         GATE(DFLL_REF, "dvfs_ref", "pc_dvfs_ref", X(27)),
 341         GATE(DFLL_SOC, "dvfs_soc", "pc_dvfs_soc",  X(27)),
 342         GATE(XUSB_SS_SRC, "xusb_ss", "xusb_ss_mux", X(28)),
 343         /* GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", X(29)), */
 344
 345         /* bank X -> 160-191*/
 346         /* GATE(SPARE, "spare", "clk_m", X(0)), */
 347         /* GATE(CAM_MCLK, "CAM_MCLK", "clk_m", X(4)), */
 348         /* GATE(CAM_MCLK2, "CAM_MCLK2", "clk_m", X(5)), */
 349         GATE(I2C6, "i2c6", "pc_i2c6", X(6)),
 350         /* GATE(VIM2_CLK, "vim2_clk", clk_m, X(11)), */
 351         /* GATE(EMC_DLL, "emc_dll", "pc_emc_dll", X(14)), */
 352         GATE(HDMI_AUDIO, "hdmi_audio", "pc_hdmi_audio", X(16)),
 353         GATE(CLK72MHZ, "clk72mhz", "pc_clk72mhz", X(17)),
 354         GATE(VIC03, "vic", "pc_vic", X(18)),
 355         GATE(ADX1, "adx1", "pc_adx1", X(20)),
 356         GATE(DPAUX, "dpaux", "clk_m", X(21)),
 357         GATE(SOR0_LVDS, "sor0", "pc_sor0", X(22)),
 358         GATE(GPU, "gpu", "osc_div_clk", X(24)),
 359         GATE(AMX1, "amx1", "pc_amx1", X(26)),
 360 };
 361
 362 /* Peripheral clock clock */
 363 #define DCF_HAVE_MUX            0x0100 /* Block with multipexor */
 364 #define DCF_HAVE_ENA            0x0200 /* Block with enable bit */
 365 #define DCF_HAVE_DIV            0x0400 /* Block with divider */
 366
 367 /* Mark block with additional bis / functionality. */
 368 #define DCF_IS_MASK             0x00FF
 369 #define DCF_IS_UART             0x0001
 370 #define DCF_IS_VI               0x0002
 371 #define DCF_IS_HOST1X           0x0003
 372 #define DCF_IS_XUSB_SS          0x0004
 373 #define DCF_IS_EMC_DLL          0x0005
 374 #define FDS_IS_SATA             0x0006
 375 #define DCF_IS_VIC              0x0007
 376 #define DCF_IS_AUDIO            0x0008
 377 #define DCF_IS_SOR0             0x0009
 378
 379 /* Basic pheripheral clock */
 380 #define PER_CLK(_id, cn, pl, r, diw, fiw, f)                            \
 381 {                                                                       \
 382         .clkdef.id = _id,                                               \
 383         .clkdef.name = cn,                                              \
 384         .clkdef.parent_names = pl,                                      \
 385         .clkdef.parent_cnt = nitems(pl),                                \
 386         .clkdef.flags = CLK_NODE_STATIC_STRINGS,                        \
 387         .base_reg = r,                                                  \
 388         .div_width = diw,                                               \
 389         .div_f_width = fiw,                                             \
 390         .flags = f,                                                     \
 391 }
 392
 393 /* Mux with fractional 8.1 divider. */
 394 #define CLK_8_1(cn, pl, r,  f)                                          \
 395         PER_CLK(0, cn, pl, r,  8, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
 396 /* Mux with fractional 16.1 divider. */
 397 #define CLK16_1(cn, pl, r,  f)                                          \
 398         PER_CLK(0, cn, pl, r,  16, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
 399 /* Mux with integer 16bits divider. */
 400 #define CLK16_0(cn, pl, r,  f)                                          \
 401         PER_CLK(0, cn, pl, r,  16, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
 402 /* Mux wihout divider. */
 403 #define CLK_0_0(cn, pl, r,  f)                                          \
 404         PER_CLK(0, cn, pl, r,  0, 0, (f) | DCF_HAVE_MUX)
 405
 406 static struct periph_def periph_def[] = {
 407         CLK_8_1("pc_i2s1", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S1, DCF_HAVE_ENA),
 408         CLK_8_1("pc_i2s2", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA),
 409         CLK_8_1("pc_spdif_out", mux_a_N_audio_N_p_N_clkm, CLK_SOURCE_SPDIF_OUT, 0),
 410         CLK_8_1("pc_spdif_in", mux_p_c2_c_c3_m, CLK_SOURCE_SPDIF_IN, 0),
 411         CLK_8_1("pc_pwm", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_PWM, 0),
 412         CLK_8_1("pc_spi2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI2, 0),
 413         CLK_8_1("pc_spi3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI3, 0),
 414         CLK16_0("pc_i2c5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C5, 0),
 415         CLK16_0("pc_i2c1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C1, 0),
 416         CLK_8_1("pc_spi1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI1, 0),
 417         CLK_0_0("pc_disp1", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP1, 0),
 418         CLK_0_0("pc_disp2", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP2, 0),
 419         CLK_8_1("pc_isp", mux_m_c_p_a_c2_c3_clkm_c4, CLK_SOURCE_ISP, 0),
 420         CLK_8_1("pc_vi", mux_m_c2_c_c3_p_N_a_c4, CLK_SOURCE_VI, DCF_IS_VI),
 421         CLK_8_1("pc_sdmmc1", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC1, 0),
 422         CLK_8_1("pc_sdmmc2", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC2, 0),
 423         CLK_8_1("pc_sdmmc4", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC4, 0),
 424         CLK_8_1("pc_vfir", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VFIR, 0),
 425         CLK_8_1("pc_hsi", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HSI, 0),
 426         CLK16_1("pc_uarta", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTA, DCF_IS_UART),
 427         CLK16_1("pc_uartb", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTB, DCF_IS_UART),
 428         CLK_8_1("pc_host1x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HOST1X, DCF_IS_HOST1X),
 429         CLK_8_1("pc_hdmi", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_HDMI, 0),
 430         CLK16_0("pc_i2c2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C2, 0),
 431 /* EMC  8 */
 432         CLK16_1("pc_uartc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTC, DCF_IS_UART),
 433         CLK_8_1("pc_vi_sensor", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR, 0),
 434         CLK_8_1("pc_spi4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI4, 0),
 435         CLK16_0("pc_i2c3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C3, 0),
 436         CLK_8_1("pc_sdmmc3", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC3, 0),
 437         CLK16_1("pc_uartd", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTD, DCF_IS_UART),
 438         CLK_8_1("pc_vde", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VDE, 0),
 439         CLK_8_1("pc_owr", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_OWR, 0),
 440         CLK_8_1("pc_snor", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_NOR, 0),
 441         CLK_8_1("pc_csite", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_CSITE, 0),
 442         CLK_8_1("pc_i2s0", mux_a_N_audio0_N_p_N_clkm, CLK_SOURCE_I2S0, 0),
 443 /* DTV xxx */
 444         CLK_8_1("pc_msenc", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_MSENC, 0),
 445         CLK_8_1("pc_tsec", mux_p_c2_c_c3_m_a_clkm, CLK_SOURCE_TSEC, 0),
 446 /* SPARE2 */
 447
 448
 449         CLK_8_1("pc_mselect", mux_p_c2_c_c3_m_clks_clkm, CLK_SOURCE_MSELECT, 0),
 450         CLK_8_1("pc_tsensor", mux_p_c2_c_c3_clkm_N_clks, CLK_SOURCE_TSENSOR, 0),
 451         CLK_8_1("pc_i2s3", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA),
 452         CLK_8_1("pc_i2s4", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA),
 453         CLK16_0("pc_i2c4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C4, 0),
 454         CLK_8_1("pc_spi5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI5, 0),
 455         CLK_8_1("pc_spi6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI6, 0),
 456         CLK_8_1("pc_audio", mux_sep_audio, CLK_SOURCE_AUDIO, DCF_IS_AUDIO),
 457         CLK_8_1("pc_dam0", mux_sep_audio, CLK_SOURCE_DAM0, DCF_IS_AUDIO),
 458         CLK_8_1("pc_dam1", mux_sep_audio, CLK_SOURCE_DAM1, DCF_IS_AUDIO),
 459         CLK_8_1("pc_dam2",  mux_sep_audio, CLK_SOURCE_DAM2, DCF_IS_AUDIO),
 460         CLK_8_1("pc_hda2codec_2x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA2CODEC_2X, 0),
 461         CLK_8_1("pc_actmon", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_ACTMON, 0),
 462         CLK_8_1("pc_extperiph1", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH1, 0),
 463         CLK_8_1("pc_extperiph2", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH2,  0),
 464         CLK_8_1("pc_extperiph3", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH3, 0),
 465         CLK_8_1("pc_i2c_slow", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_I2C_SLOW, 0),
 466 /* SYS */
 467         CLK_8_1("pc_sor0", mux_p_m_d_a_c_d2_clkm,  CLK_SOURCE_SOR0, DCF_IS_SOR0),
 468         CLK_8_1("pc_sata_oob", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA_OOB, 0),
 469         CLK_8_1("pc_sata", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA, FDS_IS_SATA),
 470         CLK_8_1("pc_hda", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA, 0),
 471
 472
 473         CLK_8_1("pc_xusb_core_host", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_HOST, 0),
 474         CLK_8_1("pc_xusb_falcon", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_FALCON, 0),
 475         CLK_8_1("pc_xusb_fs", mux_clkm_N_u48_N_p_N_u480, CLK_SOURCE_XUSB_FS, 0),
 476         CLK_8_1("pc_xusb_core_dev", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_DEV, 0),
 477         CLK_8_1("pc_xusb_ss", mux_clkm_refe_clks_u480_c_c2_c3_oscdiv, CLK_SOURCE_XUSB_SS, DCF_IS_XUSB_SS),
 478         CLK_8_1("pc_cilab", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILAB, 0),
 479         CLK_8_1("pc_cilcd", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILCD, 0),
 480         CLK_8_1("pc_cile", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILE, 0),
 481         CLK_8_1("pc_dsia_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIA_LP, 0),
 482         CLK_8_1("pc_dsib_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIB_LP, 0),
 483         CLK_8_1("pc_entropy", mux_p_clkm_clks_E, CLK_SOURCE_ENTROPY, 0),
 484         CLK_8_1("pc_dvfs_ref", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA),
 485         CLK_8_1("pc_dvfs_soc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA),
 486         CLK_8_1("pc_traceclkin", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_TRACECLKIN, 0),
 487         CLK_8_1("pc_adx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX, DCF_HAVE_ENA),
 488         CLK_8_1("pc_amx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX, DCF_HAVE_ENA),
 489         CLK_8_1("pc_emc_latency", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_LATENCY, 0),
 490         CLK_8_1("pc_soc_therm", mux_m_c_p_a_c2_c3, CLK_SOURCE_SOC_THERM, 0),
 491         CLK_8_1("pc_vi_sensor2", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR2, 0),
 492         CLK16_0("pc_i2c6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C6, 0),
 493         CLK_8_1("pc_emc_dll", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_DLL, DCF_IS_EMC_DLL),
 494         CLK_8_1("pc_hdmi_audio", mux_p_c_c2_clkm, CLK_SOURCE_HDMI_AUDIO, 0),
 495         CLK_8_1("pc_clk72mhz", mux_p_c_c2_clkm, CLK_SOURCE_CLK72MHZ, 0),
 496         CLK_8_1("pc_adx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX1, DCF_HAVE_ENA),
 497         CLK_8_1("pc_amx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX1, DCF_HAVE_ENA),
 498         CLK_8_1("pc_vic", mux_m_c_p_a_c2_c3_clkm, CLK_SOURCE_VIC, DCF_IS_VIC),
 499 };
 500
 501 static int periph_init(struct clknode *clk, device_t dev);
 502 static int periph_recalc(struct clknode *clk, uint64_t *freq);
 503 static int periph_set_freq(struct clknode *clk, uint64_t fin,
 504     uint64_t *fout, int flags, int *stop);
 505 static int periph_set_mux(struct clknode *clk, int idx);
 506
 507 struct periph_sc {
 508         device_t                clkdev;
 509         uint32_t                base_reg;
 510         uint32_t                div_shift;
 511         uint32_t                div_width;
 512         uint32_t                div_mask;
 513         uint32_t                div_f_width;
 514         uint32_t                div_f_mask;
 515         uint32_t                flags;
 516
 517         uint32_t                divider;
 518         int                     mux;
 519 };
 520
 521 static clknode_method_t periph_methods[] = {
 522         /* Device interface */
 523         CLKNODEMETHOD(clknode_init,             periph_init),
 524         CLKNODEMETHOD(clknode_recalc_freq,      periph_recalc),
 525         CLKNODEMETHOD(clknode_set_freq,         periph_set_freq),
 526         CLKNODEMETHOD(clknode_set_mux,          periph_set_mux),
 527         CLKNODEMETHOD_END
 528 };
 529 DEFINE_CLASS_1(tegra124_periph, tegra124_periph_class, periph_methods,
 530    sizeof(struct periph_sc), clknode_class);
 531 static int
 532 periph_init(struct clknode *clk, device_t dev)
 533 {
 534         struct periph_sc *sc;
 535         uint32_t reg;
 536         sc = clknode_get_softc(clk);
 537
 538         DEVICE_LOCK(sc);
 539         if (sc->flags & DCF_HAVE_ENA)
 540                 MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK);
 541
 542         RD4(sc, sc->base_reg, &reg);
 543         DEVICE_UNLOCK(sc);
 544
 545         /* Stnadard mux. */
 546         if (sc->flags & DCF_HAVE_MUX)
 547                 sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK;
 548         else
 549                 sc->mux = 0;
 550         if (sc->flags & DCF_HAVE_DIV)
 551                 sc->divider = (reg & sc->div_mask) + 2;
 552         else
 553                 sc->divider = 1;
 554         if ((sc->flags & DCF_IS_MASK) == DCF_IS_UART) {
 555                 if (!(reg & PERLCK_UDIV_DIS))
 556                         sc->divider = 2;
 557         }
 558
 559         /* AUDIO MUX */
 560         if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) {
 561                 if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) {
 562                         sc->mux = 8 +
 563                             ((reg >> PERLCK_AMUX_SHIFT) & PERLCK_MUX_MASK);
 564                 }
 565         }
 566         clknode_init_parent_idx(clk, sc->mux);
 567         return(0);
 568 }
 569
 570 static int
 571 periph_set_mux(struct clknode *clk, int idx)
 572 {
 573         struct periph_sc *sc;
 574         uint32_t reg;
 575
 576
 577         sc = clknode_get_softc(clk);
 578         if (!(sc->flags & DCF_HAVE_MUX))
 579                 return (ENXIO);
 580
 581         sc->mux = idx;
 582         DEVICE_LOCK(sc);
 583         RD4(sc, sc->base_reg, &reg);
 584         reg &= ~(PERLCK_MUX_MASK << PERLCK_MUX_SHIFT);
 585         if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) {
 586                 reg &= ~PERLCK_AMUX_DIS;
 587                 reg &= ~(PERLCK_MUX_MASK << PERLCK_AMUX_SHIFT);
 588
 589                 if (idx <= 7) {
 590                         reg |= idx << PERLCK_MUX_SHIFT;
 591                 } else {
 592                         reg |= 7 << PERLCK_MUX_SHIFT;
 593                         reg |= (idx - 8) << PERLCK_AMUX_SHIFT;
 594                 }
 595         } else {
 596                 reg |= idx << PERLCK_MUX_SHIFT;
 597         }
 598         WR4(sc, sc->base_reg, reg);
 599         DEVICE_UNLOCK(sc);
 600
 601         return(0);
 602 }
 603
 604 static int
 605 periph_recalc(struct clknode *clk, uint64_t *freq)
 606 {
 607         struct periph_sc *sc;
 608         uint32_t reg;
 609
 610         sc = clknode_get_softc(clk);
 611
 612         if (sc->flags & DCF_HAVE_DIV) {
 613                 DEVICE_LOCK(sc);
 614                 RD4(sc, sc->base_reg, &reg);
 615                 DEVICE_UNLOCK(sc);
 616                 *freq = (*freq << sc->div_f_width) / sc->divider;
 617         }
 618         return (0);
 619 }
 620
 621 static int
 622 periph_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
 623    int flags, int *stop)
 624 {
 625         struct periph_sc *sc;
 626         uint64_t tmp, divider;
 627
 628         sc = clknode_get_softc(clk);
 629         if (!(sc->flags & DCF_HAVE_DIV)) {
 630                 *stop = 0;
 631                 return (0);
 632         }
 633
 634         tmp = fin << sc->div_f_width;
 635         divider = tmp / *fout;
 636         if ((tmp % *fout) != 0)
 637                 divider++;
 638
 639         if (divider < (1 << sc->div_f_width))
 640                  divider = 1 << sc->div_f_width;
 641
 642         if ((*stop != 0) &&
 643             ((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
 644             (*fout != (tmp / divider)))
 645                 return (ERANGE);
 646
 647         if ((flags & CLK_SET_DRYRUN) == 0) {
 648                 DEVICE_LOCK(sc);
 649                 MD4(sc, sc->base_reg, sc->div_mask,
 650                     (divider - (1 << sc->div_f_width)));
 651                 DEVICE_UNLOCK(sc);
 652                 sc->divider = divider;
 653         }
 654         *fout = tmp / divider;
 655         *stop = 1;
 656         return (0);
 657 }
 658
 659 static int
 660 periph_register(struct clkdom *clkdom, struct periph_def *clkdef)
 661 {
 662         struct clknode *clk;
 663         struct periph_sc *sc;
 664
 665         clk = clknode_create(clkdom, &tegra124_periph_class, &clkdef->clkdef);
 666         if (clk == NULL)
 667                 return (1);
 668
 669         sc = clknode_get_softc(clk);
 670         sc->clkdev = clknode_get_device(clk);
 671         sc->base_reg = clkdef->base_reg;
 672         sc->div_width = clkdef->div_width;
 673         sc->div_mask = (1 <<clkdef->div_width) - 1;
 674         sc->div_f_width = clkdef->div_f_width;
 675         sc->div_f_mask = (1 <<clkdef->div_f_width) - 1;
 676         sc->flags = clkdef->flags;
 677
 678         clknode_register(clkdom, clk);
 679         return (0);
 680 }
 681
 682 /* -------------------------------------------------------------------------- */
 683 static int pgate_init(struct clknode *clk, device_t dev);
 684 static int pgate_set_gate(struct clknode *clk, bool enable);
 685
 686 struct pgate_sc {
 687         device_t                clkdev;
 688         uint32_t                idx;
 689         uint32_t                flags;
 690         uint32_t                enabled;
 691
 692 };
 693
 694 static clknode_method_t pgate_methods[] = {
 695         /* Device interface */
 696         CLKNODEMETHOD(clknode_init,             pgate_init),
 697         CLKNODEMETHOD(clknode_set_gate,         pgate_set_gate),
 698         CLKNODEMETHOD_END
 699 };
 700 DEFINE_CLASS_1(tegra124_pgate, tegra124_pgate_class, pgate_methods,
 701    sizeof(struct pgate_sc), clknode_class);
 702
 703 static uint32_t
 704 get_enable_reg(int idx)
 705 {
 706         KASSERT(idx / 32 < nitems(clk_enabale_reg),
 707             ("Invalid clock index for enable: %d", idx));
 708         return (clk_enabale_reg[idx / 32]);
 709 }
 710
 711 static uint32_t
 712 get_reset_reg(int idx)
 713 {
 714         KASSERT(idx / 32 < nitems(clk_reset_reg),
 715             ("Invalid clock index for reset: %d", idx));
 716         return (clk_reset_reg[idx / 32]);
 717 }
 718
 719 static int
 720 pgate_init(struct clknode *clk, device_t dev)
 721 {
 722         struct pgate_sc *sc;
 723         uint32_t ena_reg, rst_reg, mask;
 724
 725         sc = clknode_get_softc(clk);
 726         mask = 1 << (sc->idx % 32);
 727
 728         DEVICE_LOCK(sc);
 729         RD4(sc, get_enable_reg(sc->idx), &ena_reg);
 730         RD4(sc, get_reset_reg(sc->idx), &rst_reg);
 731         DEVICE_UNLOCK(sc);
 732
 733         sc->enabled = ena_reg & mask ? 1 : 0;
 734         clknode_init_parent_idx(clk, 0);
 735
 736         return(0);
 737 }
 738
 739 static int
 740 pgate_set_gate(struct clknode *clk, bool enable)
 741 {
 742         struct pgate_sc *sc;
 743         uint32_t reg, mask, base_reg;
 744
 745         sc = clknode_get_softc(clk);
 746         mask = 1 << (sc->idx % 32);
 747         sc->enabled = enable;
 748         base_reg = get_enable_reg(sc->idx);
 749
 750         DEVICE_LOCK(sc);
 751         MD4(sc, base_reg, mask, enable ? mask : 0);
 752         RD4(sc, base_reg, &reg);
 753         DEVICE_UNLOCK(sc);
 754
 755         DELAY(2);
 756         return(0);
 757 }
 758
 759 int
 760 tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, bool reset)
 761 {
 762         uint32_t reg, mask, reset_reg;
 763
 764         mask = 1 << (idx % 32);
 765         reset_reg = get_reset_reg(idx);
 766
 767         CLKDEV_DEVICE_LOCK(sc->dev);
 768         CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0);
 769         CLKDEV_READ_4(sc->dev, reset_reg, &reg);
 770         CLKDEV_DEVICE_UNLOCK(sc->dev);
 771
 772         return(0);
 773 }
 774
 775 static int
 776 pgate_register(struct clkdom *clkdom, struct pgate_def *clkdef)
 777 {
 778         struct clknode *clk;
 779         struct pgate_sc *sc;
 780
 781         clk = clknode_create(clkdom, &tegra124_pgate_class, &clkdef->clkdef);
 782         if (clk == NULL)
 783                 return (1);
 784
 785         sc = clknode_get_softc(clk);
 786         sc->clkdev = clknode_get_device(clk);
 787         sc->idx = clkdef->idx;
 788         sc->flags = clkdef->flags;
 789
 790         clknode_register(clkdom, clk);
 791         return (0);
 792 }
 793
 794 void
 795 tegra124_periph_clock(struct tegra124_car_softc *sc)
 796 {
 797         int i, rv;
 798
 799         for (i = 0; i <  nitems(periph_def); i++) {
 800                 rv = periph_register(sc->clkdom, &periph_def[i]);
 801                 if (rv != 0)
 802                         panic("tegra124_periph_register failed");
 803         }
 804         for (i = 0; i <  nitems(pgate_def); i++) {
 805                 rv = pgate_register(sc->clkdom, &pgate_def[i]);
 806                 if (rv != 0)
 807                         panic("tegra124_pgate_register failed");
 808         }
 809
 810 }