2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
32 #include <sys/kernel.h>
34 #include <sys/mutex.h>
40 #include <machine/cpu.h>
41 #include <machine/intr.h>
42 #include <machine/fdt.h>
43 #include <machine/smp.h>
44 #include <machine/platformvar.h>
45 #include <machine/pmap.h>
47 #include <arm/nvidia/tegra124/tegra124_mp.h>
49 #define PMC_PHYSBASE 0x7000e400
50 #define PMC_SIZE 0x400
51 #define PMC_CONTROL_REG 0x0
52 #define PMC_PWRGATE_TOGGLE 0x30
53 #define PCM_PWRGATE_TOGGLE_START (1 << 8)
54 #define PMC_PWRGATE_STATUS 0x38
56 #define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 /* exception vectors */
57 #define TEGRA_EXCEPTION_VECTORS_SIZE 1024
58 #define TEGRA_EXCEPTION_VECTOR_ENTRY 0x100
61 tegra124_mp_setmaxid(platform_t plat)
65 /* If we've already set the global vars don't bother to do it again. */
69 /* Read current CP15 Cache Size ID Register */
70 ncpu = cp15_l2ctlr_get();
71 ncpu = CPUV7_L2CTLR_NPROC(ncpu);
78 tegra124_mp_start_ap(platform_t plat)
80 bus_space_handle_t pmc;
81 bus_space_handle_t exvec;
86 if (bus_space_map(fdtbus_bs_tag, PMC_PHYSBASE, PMC_SIZE, 0, &pmc) != 0)
87 panic("Couldn't map the PMC\n");
88 if (bus_space_map(fdtbus_bs_tag, TEGRA_EXCEPTION_VECTORS_BASE,
89 TEGRA_EXCEPTION_VECTORS_SIZE, 0, &exvec) != 0)
90 panic("Couldn't map the exception vectors\n");
92 bus_space_write_4(fdtbus_bs_tag, exvec , TEGRA_EXCEPTION_VECTOR_ENTRY,
93 pmap_kextract((vm_offset_t)mpentry));
94 bus_space_read_4(fdtbus_bs_tag, exvec , TEGRA_EXCEPTION_VECTOR_ENTRY);
96 /* Wait until POWERGATE is ready (max 20 APB cycles). */
98 val = bus_space_read_4(fdtbus_bs_tag, pmc,
100 } while ((val & PCM_PWRGATE_TOGGLE_START) != 0);
102 for (i = 1; i < mp_ncpus; i++) {
103 val = bus_space_read_4(fdtbus_bs_tag, pmc, PMC_PWRGATE_STATUS);
104 mask = 1 << (i + 8); /* cpu mask */
105 if ((val & mask) == 0) {
106 /* Wait until POWERGATE is ready (max 20 APB cycles). */
108 val = bus_space_read_4(fdtbus_bs_tag, pmc,
110 } while ((val & PCM_PWRGATE_TOGGLE_START) != 0);
111 bus_space_write_4(fdtbus_bs_tag, pmc,
113 PCM_PWRGATE_TOGGLE_START | (8 + i));
115 /* Wait until CPU is powered */
117 val = bus_space_read_4(fdtbus_bs_tag, pmc,
119 } while ((val & mask) == 0);
124 bus_space_unmap(fdtbus_bs_tag, pmc, PMC_SIZE);
125 bus_space_unmap(fdtbus_bs_tag, exvec, TEGRA_EXCEPTION_VECTORS_SIZE);