2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/malloc.h>
38 #include <machine/bus.h>
39 #include <machine/fdt.h>
41 #include <dev/extres/hwreset/hwreset.h>
42 #include <dev/extres/phy/phy.h>
43 #include <dev/extres/regulator/regulator.h>
44 #include <dev/fdt/fdt_common.h>
45 #include <dev/fdt/fdt_pinctrl.h>
46 #include <dev/ofw/openfirm.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
50 #include <arm/nvidia/tegra_efuse.h>
52 #include <gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
54 #include "phydev_if.h"
56 /* FUSE calibration data. */
57 #define FUSE_XUSB_CALIB 0x0F0
58 #define FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(x) (((x) >> 15) & 0x3F);
59 #define FUSE_XUSB_CALIB_HS_IREF_CAP(x) (((x) >> 13) & 0x03);
60 #define FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(x) (((x) >> 11) & 0x03);
61 #define FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(x) (((x) >> 7) & 0x0F);
62 #define FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(x) (((x) >> 0) & 0x3F);
66 #define XUSB_PADCTL_USB2_PAD_MUX 0x004
68 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
69 #define USB2_PORT_CAP_ULPI_PORT_INTERNAL (1 << 25)
70 #define USB2_PORT_CAP_ULPI_PORT_CAP (1 << 24)
71 #define USB2_PORT_CAP_PORT_REVERSE_ID(p) (1 << (3 + (p) * 4))
72 #define USB2_PORT_CAP_PORT_INTERNAL(p) (1 << (2 + (p) * 4))
73 #define USB2_PORT_CAP_PORT_CAP(p, x) (((x) & 3) << ((p) * 4))
74 #define USB2_PORT_CAP_PORT_CAP_OTG 0x3
75 #define USB2_PORT_CAP_PORT_CAP_DEVICE 0x2
76 #define USB2_PORT_CAP_PORT_CAP_HOST 0x1
77 #define USB2_PORT_CAP_PORT_CAP_DISABLED 0x0
79 #define XUSB_PADCTL_SS_PORT_MAP 0x014
80 #define SS_PORT_MAP_PORT_INTERNAL(p) (1 << (3 + (p) * 4))
81 #define SS_PORT_MAP_PORT_MAP(p, x) (((x) & 7) << ((p) * 4))
83 #define XUSB_PADCTL_ELPG_PROGRAM 0x01C
84 #define ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
85 #define ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
86 #define ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
87 #define ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
88 #define ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(x) (1 << (17 + (x) * 4))
89 #define ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
91 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
92 #define IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
93 #define IOPHY_PLL_P0_CTL1_REFCLK_SEL(x) (((x) & 0xF) << 12)
94 #define IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
96 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
97 #define IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
98 #define IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
99 #define IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
101 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(x) (0x058 + (x) * 4)
102 #define IOPHY_USB3_PAD_CTL2_CDR_CNTL(x) (((x) & 0x00FF) << 4)
103 #define IOPHY_USB3_PAD_CTL2_RX_EQ(x) (((x) & 0xFFFF) << 8)
104 #define IOPHY_USB3_PAD_CTL2_RX_WANDER(x) (((x) & 0x000F) << 4)
105 #define IOPHY_USB3_PAD_CTL2_RX_TERM_CNTL(x) (((x) & 0x0003) << 2)
106 #define IOPHY_USB3_PAD_CTL2_TX_TERM_CNTL(x) (((x) & 0x0003) << 0)
109 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(x) (0x068 + (x) * 4)
111 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0(x) (0x0A0 + (x) * 4)
112 #define USB2_OTG_PAD_CTL0_LSBIAS_SEL (1 << 23)
113 #define USB2_OTG_PAD_CTL0_DISCON_DETECT_METHOD (1 << 22)
114 #define USB2_OTG_PAD_CTL0_PD_ZI (1 << 21)
115 #define USB2_OTG_PAD_CTL0_PD2 (1 << 20)
116 #define USB2_OTG_PAD_CTL0_PD (1 << 19)
117 #define USB2_OTG_PAD_CTL0_TERM_EN (1 << 18)
118 #define USB2_OTG_PAD_CTL0_LS_LS_FSLEW(x) (((x) & 0x03) << 16)
119 #define USB2_OTG_PAD_CTL0_LS_RSLEW(x) (((x) & 0x03) << 14)
120 #define USB2_OTG_PAD_CTL0_FS_SLEW(x) (((x) & 0x03) << 12)
121 #define USB2_OTG_PAD_CTL0_HS_SLEW(x) (((x) & 0x3F) << 6)
122 #define USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(x) (((x) & 0x3F) << 0)
124 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1(x) (0x0AC + (x) * 4)
125 #define USB2_OTG_PAD_CTL1_RPU_RANGE_ADJ(x) (((x) & 0x3) << 11)
126 #define USB2_OTG_PAD_CTL1_HS_IREF_CAP(x) (((x) & 0x3) << 9)
127 #define USB2_OTG_PAD_CTL1_SPARE(x) (((x) & 0x3) << 7)
128 #define USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(x) (((x) & 0xF) << 3)
129 #define USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
130 #define USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP (1 << 1)
131 #define USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP (1 << 0)
133 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x0B8
134 #define USB2_BIAS_PAD_CTL0_ADJRPU(x) (((x) & 0x7) << 14)
135 #define USB2_BIAS_PAD_CTL0_PD_TRK (1 << 13)
136 #define USB2_BIAS_PAD_CTL0_PD (1 << 12)
137 #define USB2_BIAS_PAD_CTL0_TERM_OFFSETL(x) (((x) & 0x3) << 9)
138 #define USB2_BIAS_PAD_CTL0_VBUS_LEVEL(x) (((x) & 0x3) << 7)
139 #define USB2_BIAS_PAD_CTL0_HS_CHIRP_LEVEL(x) (((x) & 0x3) << 5)
140 #define USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(x) (((x) & 0x7) << 2)
141 #define USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(x) (((x) & 0x3) << 0)
143 #define XUSB_PADCTL_HSIC_PAD0_CTL0 0x0C8
144 #define HSIC_PAD0_CTL0_HSIC_OPT(x) (((x) & 0xF) << 16)
145 #define HSIC_PAD0_CTL0_TX_SLEWN(x) (((x) & 0xF) << 12)
146 #define HSIC_PAD0_CTL0_TX_SLEWP(x) (((x) & 0xF) << 8)
147 #define HSIC_PAD0_CTL0_TX_RTUNEN(x) (((x) & 0xF) << 4)
148 #define HSIC_PAD0_CTL0_TX_RTUNEP(x) (((x) & 0xF) << 0)
150 #define XUSB_PADCTL_USB3_PAD_MUX 0x134
151 #define USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
152 #define USB3_PAD_MUX_SATA_IDDQ_DISABLE (1 << 6)
155 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
156 #define IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
157 #define IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
158 #define IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
159 #define IOPHY_PLL_S0_CTL1_PLL_RST_L (1 << 1)
160 #define IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
162 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2 0x13C
163 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL3 0x140
164 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL4 0x144
166 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
167 #define IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
168 #define IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
170 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2 0x14C
171 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL3 0x150
172 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL4 0x154
173 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5 0x158
174 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6 0x15C
177 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
178 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
181 struct padctl_softc {
183 struct resource *mem_res;
187 /* Fuses calibration data */
188 uint32_t hs_curr_level_0;
189 uint32_t hs_curr_level_123;
190 uint32_t hs_iref_cap;
191 uint32_t hs_term_range_adj;
192 uint32_t hs_squelch_level;
194 uint32_t hs_curr_level_offset;
197 static struct ofw_compat_data compat_data[] = {
198 {"nvidia,tegra124-xusb-padctl", 1},
203 enum padctl_port_type {
212 enum padctl_port_type type;
214 const char *base_name;
216 int (*init)(struct padctl_softc *sc,
217 struct padctl_port *port);
221 regulator_t supply_vbus; /* USB2, USB3 */
222 bool internal; /* ULPI, USB2, USB3 */
223 uint32_t companion; /* USB3 */
224 struct padctl_lane *lane;
227 static int usb3_port_init(struct padctl_softc *sc, struct padctl_port *port);
229 #define PORT(t, n, p, i) { \
236 static struct padctl_port ports_tbl[] = {
237 PORT(PADCTL_PORT_USB2, "usb2", 0, NULL),
238 PORT(PADCTL_PORT_USB2, "usb2", 1, NULL),
239 PORT(PADCTL_PORT_USB2, "usb2", 2, NULL),
240 PORT(PADCTL_PORT_ULPI, "ulpi", 0, NULL),
241 PORT(PADCTL_PORT_HSIC, "hsic", 0, NULL),
242 PORT(PADCTL_PORT_HSIC, "hsic", 1, NULL),
243 PORT(PADCTL_PORT_USB3, "usb3", 0, usb3_port_init),
244 PORT(PADCTL_PORT_USB3, "usb3", 1, usb3_port_init),
247 /* Pads - a group of lannes. */
248 enum padctl_pad_type {
259 enum padctl_pad_type type;
260 int (*powerup)(struct padctl_softc *sc,
261 struct padctl_lane *lane);
262 int (*powerdown)(struct padctl_softc *sc,
263 struct padctl_lane *lane);
266 struct padctl_lane *lanes[8]; /* Safe maximum value. */
270 static int usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
271 static int usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
272 static int pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
273 static int pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
274 static int sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
275 static int sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
277 #define PAD(n, t, u, d) { \
283 static struct padctl_pad pads_tbl[] = {
284 PAD("usb2", PADCTL_PAD_USB2, usb2_powerup, usb2_powerdown),
285 PAD("ulpi", PADCTL_PAD_ULPI, NULL, NULL),
286 PAD("hsic", PADCTL_PAD_HSIC, NULL, NULL),
287 PAD("pcie", PADCTL_PAD_PCIE, pcie_powerup, pcie_powerdown),
288 PAD("sata", PADCTL_PAD_SATA, sata_powerup, sata_powerdown),
292 static char *otg_mux[] = {"snps", "xusb", "uart", "rsvd"};
293 static char *usb_mux[] = {"snps", "xusb"};
294 static char *pci_mux[] = {"pcie", "usb3-ss", "sata", "rsvd"};
306 struct padctl_pad *pad;
307 struct padctl_port *port;
312 #define LANE(n, p, r, s, m, mx) { \
319 .nmux = nitems(mx), \
321 static struct padctl_lane lanes_tbl[] = {
322 LANE("usb2", 0, XUSB_PADCTL_USB2_PAD_MUX, 0, 0x3, otg_mux),
323 LANE("usb2", 1, XUSB_PADCTL_USB2_PAD_MUX, 2, 0x3, otg_mux),
324 LANE("usb2", 2, XUSB_PADCTL_USB2_PAD_MUX, 4, 0x3, otg_mux),
325 LANE("ulpi", 0, XUSB_PADCTL_USB2_PAD_MUX, 12, 0x1, usb_mux),
326 LANE("hsic", 0, XUSB_PADCTL_USB2_PAD_MUX, 14, 0x1, usb_mux),
327 LANE("hsic", 1, XUSB_PADCTL_USB2_PAD_MUX, 15, 0x1, usb_mux),
328 LANE("pcie", 0, XUSB_PADCTL_USB3_PAD_MUX, 16, 0x3, pci_mux),
329 LANE("pcie", 1, XUSB_PADCTL_USB3_PAD_MUX, 18, 0x3, pci_mux),
330 LANE("pcie", 2, XUSB_PADCTL_USB3_PAD_MUX, 20, 0x3, pci_mux),
331 LANE("pcie", 3, XUSB_PADCTL_USB3_PAD_MUX, 22, 0x3, pci_mux),
332 LANE("pcie", 4, XUSB_PADCTL_USB3_PAD_MUX, 24, 0x3, pci_mux),
333 LANE("sata", 0, XUSB_PADCTL_USB3_PAD_MUX, 26, 0x3, pci_mux),
336 /* Define all possible mappings for USB3 port lanes */
337 struct padctl_lane_map {
339 enum padctl_pad_type pad_type;
343 #define LANE_MAP(pi, pt, li) { \
348 static struct padctl_lane_map lane_map_tbl[] = {
349 LANE_MAP(0, PADCTL_PAD_PCIE, 0), /* port USB3-0 -> lane PCIE-0 */
350 LANE_MAP(1, PADCTL_PAD_PCIE, 1), /* port USB3-1 -> lane PCIE-1 */
352 LANE_MAP(1, PADCTL_PAD_SATA, 0), /* port USB3-1 -> lane SATA-0 */
355 /* Phy class and methods. */
356 static int xusbpadctl_phy_enable(struct phynode *phy, bool enable);
357 static phynode_method_t xusbpadctl_phynode_methods[] = {
358 PHYNODEMETHOD(phynode_enable, xusbpadctl_phy_enable),
362 DEFINE_CLASS_1(xusbpadctl_phynode, xusbpadctl_phynode_class,
363 xusbpadctl_phynode_methods, 0, phynode_class);
365 static struct padctl_port *search_lane_port(struct padctl_softc *sc,
366 struct padctl_lane *lane);
367 /* -------------------------------------------------------------------------
372 usb3_port_init(struct padctl_softc *sc, struct padctl_port *port)
376 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);
378 reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx);
380 reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx);
381 reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0);
382 reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion);
383 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);
385 reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx));
386 reg &= ~IOPHY_USB3_PAD_CTL2_CDR_CNTL(~0);
387 reg &= ~IOPHY_USB3_PAD_CTL2_RX_EQ(~0);
388 reg &= ~IOPHY_USB3_PAD_CTL2_RX_WANDER(~0);
389 reg |= IOPHY_USB3_PAD_CTL2_CDR_CNTL(0x24);
390 reg |= IOPHY_USB3_PAD_CTL2_RX_EQ(0xF070);
391 reg |= IOPHY_USB3_PAD_CTL2_RX_WANDER(0xF);
392 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg);
394 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx),
397 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
398 reg &= ~ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(port->idx);
399 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
402 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
403 reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(port->idx);
404 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
407 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
408 reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(port->idx);
409 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
416 pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane)
421 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
422 reg &= ~IOPHY_PLL_P0_CTL1_REFCLK_SEL(~0);
423 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
426 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
427 reg |= IOPHY_PLL_P0_CTL2_REFCLKBUF_EN;
428 reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_EN;
429 reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
430 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg);
433 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
434 reg |= IOPHY_PLL_P0_CTL1_PLL_RST;
435 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
438 for (i = 100; i > 0; i--) {
439 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
440 if (reg & IOPHY_PLL_P0_CTL1_PLL0_LOCKDET)
445 device_printf(sc->dev, "Failed to power up PCIe phy\n");
448 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
449 reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);
450 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
456 pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane)
460 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
461 reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);
462 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
464 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
465 reg &= ~IOPHY_PLL_P0_CTL1_PLL_RST;
466 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
474 sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane)
479 reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
480 reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
481 reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ;
482 WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);
484 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
485 reg &= ~IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
486 reg &= ~IOPHY_PLL_S0_CTL1_PLL_IDDQ;
487 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
489 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
490 reg |= IOPHY_PLL_S0_CTL1_PLL1_MODE;
491 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
493 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
494 reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L;
495 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
497 for (i = 100; i >= 0; i--) {
498 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
499 if (reg & IOPHY_PLL_S0_CTL1_PLL1_LOCKDET)
504 device_printf(sc->dev, "Failed to power up SATA phy\n");
507 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
508 reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L;
509 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
511 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
512 reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE;
513 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
519 sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane)
523 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
524 reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE;
525 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
527 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
528 reg &= ~IOPHY_PLL_S0_CTL1_PLL_RST_L;
529 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
532 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
533 reg &= ~IOPHY_PLL_S0_CTL1_PLL1_MODE;
534 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
537 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
538 reg |= IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
539 reg |= IOPHY_PLL_S0_CTL1_PLL_IDDQ;
540 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
543 reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
544 reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
545 reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ;
546 WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);
553 usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane)
556 struct padctl_port *port;
559 port = search_lane_port(sc, lane);
561 device_printf(sc->dev, "Cannot find port for lane: %s\n",
564 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
565 reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0);
566 reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0);
567 reg |= USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(sc->hs_squelch_level);
568 reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(5);
569 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
571 reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP);
572 reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0);
573 reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST);
574 WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg);
576 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx));
577 reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0);
578 reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0);
579 reg &= ~USB2_OTG_PAD_CTL0_LS_RSLEW(~0);
580 reg &= ~USB2_OTG_PAD_CTL0_PD;
581 reg &= ~USB2_OTG_PAD_CTL0_PD2;
582 reg &= ~USB2_OTG_PAD_CTL0_PD_ZI;
584 reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14);
585 if (lane->idx == 0) {
586 reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_0);
587 reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(3);
589 reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_123);
590 reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(0);
592 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg);
594 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx));
595 reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0);
596 reg &= ~USB2_OTG_PAD_CTL1_HS_IREF_CAP(~0);
597 reg &= ~USB2_OTG_PAD_CTL1_PD_DR;
598 reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP;
599 reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP;
601 reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj);
602 reg |= USB2_OTG_PAD_CTL1_HS_IREF_CAP(sc->hs_iref_cap);
603 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg);
605 if (port != NULL && port->supply_vbus != NULL) {
606 rv = regulator_enable(port->supply_vbus);
608 device_printf(sc->dev,
609 "Cannot enable vbus regulator\n");
613 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
614 reg &= ~USB2_BIAS_PAD_CTL0_PD;
615 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
621 usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane)
624 struct padctl_port *port;
627 port = search_lane_port(sc, lane);
629 device_printf(sc->dev, "Cannot find port for lane: %s\n",
632 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
633 reg |= USB2_BIAS_PAD_CTL0_PD;
634 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
636 if (port != NULL && port->supply_vbus != NULL) {
637 rv = regulator_enable(port->supply_vbus);
639 device_printf(sc->dev,
640 "Cannot disable vbus regulator\n");
649 phy_powerup(struct padctl_softc *sc)
653 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
654 reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
655 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
658 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
659 reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
660 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
663 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
664 reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
665 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
672 phy_powerdown(struct padctl_softc *sc)
676 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
677 reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
678 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
681 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
682 reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
683 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
686 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
687 reg |= ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
688 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
695 xusbpadctl_phy_enable(struct phynode *phy, bool enable)
699 struct padctl_softc *sc;
700 struct padctl_lane *lane;
701 struct padctl_pad *pad;
704 dev = phynode_get_device(phy);
705 id = phynode_get_id(phy);
706 sc = device_get_softc(dev);
708 if (id < 0 || id >= nitems(lanes_tbl)) {
709 device_printf(dev, "Unknown phy: %d\n", id);
712 lane = lanes_tbl + id;
713 if (!lane->enabled) {
714 device_printf(dev, "Lane is not enabled/configured: %s\n",
720 if (sc->phy_ena_cnt == 0) {
721 rv = phy_powerup(sc);
729 rv = pad->powerup(sc, lane);
731 rv = pad->powerdown(sc, lane);
736 if (sc->phy_ena_cnt == 1) {
737 rv = phy_powerdown(sc);
747 /* -------------------------------------------------------------------------
751 static struct padctl_port *
752 search_port(struct padctl_softc *sc, char *port_name)
756 for (i = 0; i < nitems(ports_tbl); i++) {
757 if (strcmp(port_name, ports_tbl[i].name) == 0)
758 return (&ports_tbl[i]);
763 static struct padctl_port *
764 search_lane_port(struct padctl_softc *sc, struct padctl_lane *lane)
768 for (i = 0; i < nitems(ports_tbl); i++) {
769 if (!ports_tbl[i].enabled)
771 if (ports_tbl[i].lane == lane)
772 return (ports_tbl + i);
777 static struct padctl_lane *
778 search_lane(struct padctl_softc *sc, char *lane_name)
782 for (i = 0; i < nitems(lanes_tbl); i++) {
783 if (strcmp(lane_name, lanes_tbl[i].name) == 0)
784 return (lanes_tbl + i);
789 static struct padctl_lane *
790 search_pad_lane(struct padctl_softc *sc, enum padctl_pad_type type, int idx)
794 for (i = 0; i < nitems(lanes_tbl); i++) {
795 if (!lanes_tbl[i].enabled)
797 if (type == lanes_tbl[i].pad->type && idx == lanes_tbl[i].idx)
798 return (lanes_tbl + i);
803 static struct padctl_lane *
804 search_usb3_pad_lane(struct padctl_softc *sc, int idx)
807 struct padctl_lane *lane, *tmp;
810 for (i = 0; i < nitems(lane_map_tbl); i++) {
811 if (idx != lane_map_tbl[i].port_idx)
813 tmp = search_pad_lane(sc, lane_map_tbl[i].pad_type,
814 lane_map_tbl[i].lane_idx);
817 if (strcmp(tmp->mux[tmp->mux_idx], "usb3-ss") != 0)
820 device_printf(sc->dev, "Duplicated mappings found for"
821 " lanes: %s and %s\n", lane->name, tmp->name);
829 static struct padctl_pad *
830 search_pad(struct padctl_softc *sc, char *pad_name)
834 for (i = 0; i < nitems(pads_tbl); i++) {
835 if (strcmp(pad_name, pads_tbl[i].name) == 0)
836 return (pads_tbl + i);
842 search_mux(struct padctl_softc *sc, struct padctl_lane *lane, char *fnc_name)
846 for (i = 0; i < lane->nmux; i++) {
847 if (strcmp(fnc_name, lane->mux[i]) == 0)
854 config_lane(struct padctl_softc *sc, struct padctl_lane *lane)
858 reg = RD4(sc, lane->reg);
859 reg &= ~(lane->mask << lane->shift);
860 reg |= (lane->mux_idx & lane->mask) << lane->shift;
861 WR4(sc, lane->reg, reg);
866 process_lane(struct padctl_softc *sc, phandle_t node, struct padctl_pad *pad)
868 struct padctl_lane *lane;
869 struct phynode *phynode;
870 struct phynode_init_def phy_init;
877 rv = OF_getprop_alloc(node, "name", (void **)&name);
879 device_printf(sc->dev, "Cannot read lane name.\n");
883 lane = search_lane(sc, name);
885 device_printf(sc->dev, "Unknown lane: %s\n", name);
890 /* Read function (mux) settings. */
891 rv = OF_getprop_alloc(node, "nvidia,function", (void **)&function);
893 device_printf(sc->dev, "Cannot read lane function.\n");
898 lane->mux_idx = search_mux(sc, lane, function);
899 if (lane->mux_idx == ~0) {
900 device_printf(sc->dev, "Unknown function %s for lane %s\n",
906 rv = config_lane(sc, lane);
908 device_printf(sc->dev, "Cannot configure lane: %s: %d\n",
914 lane->enabled = true;
915 pad->lanes[pad->nlanes++] = lane;
917 /* Create and register phy. */
918 bzero(&phy_init, sizeof(phy_init));
919 phy_init.id = lane - lanes_tbl;
920 phy_init.ofw_node = node;
921 phynode = phynode_create(sc->dev, &xusbpadctl_phynode_class, &phy_init);
922 if (phynode == NULL) {
923 device_printf(sc->dev, "Cannot create phy\n");
927 if (phynode_register(phynode) == NULL) {
928 device_printf(sc->dev, "Cannot create phy\n");
937 if (function != NULL)
938 OF_prop_free(function);
943 process_pad(struct padctl_softc *sc, phandle_t node)
945 struct padctl_pad *pad;
950 rv = OF_getprop_alloc(node, "name", (void **)&name);
952 device_printf(sc->dev, "Cannot read pad name.\n");
955 pad = search_pad(sc, name);
957 device_printf(sc->dev, "Unknown pad: %s\n", name);
962 /* Read and process associated lanes. */
963 node = ofw_bus_find_child(node, "lanes");
965 device_printf(sc->dev, "Cannot find regulators subnode\n");
970 for (node = OF_child(node); node != 0; node = OF_peer(node)) {
971 if (!ofw_bus_node_status_okay(node))
974 rv = process_lane(sc, node, pad);
987 process_port(struct padctl_softc *sc, phandle_t node)
990 struct padctl_port *port;
995 rv = OF_getprop_alloc(node, "name", (void **)&name);
997 device_printf(sc->dev, "Cannot read port name.\n");
1001 port = search_port(sc, name);
1003 device_printf(sc->dev, "Unknown port: %s\n", name);
1008 if (port->type == PADCTL_PORT_USB3) {
1009 rv = OF_getencprop(node, "nvidia,usb2-companion",
1010 &(port->companion), sizeof(port->companion));
1012 device_printf(sc->dev,
1013 "Missing 'nvidia,usb2-companion' property "
1014 "for port: %s\n", name);
1020 if (OF_hasprop(node, "vbus-supply")) {
1021 rv = regulator_get_by_ofw_property(sc->dev, 0,
1022 "vbus-supply", &port->supply_vbus);
1024 device_printf(sc->dev,
1025 "Cannot get 'vbus-supply' regulator "
1026 "for port: %s\n", name);
1032 if (OF_hasprop(node, "nvidia,internal"))
1033 port->internal = true;
1034 /* Find assigned lane */
1035 if (port->lane == NULL) {
1036 switch(port->type) {
1037 /* Routing is fixed for USB2, ULPI AND HSIC. */
1038 case PADCTL_PORT_USB2:
1039 port->lane = search_pad_lane(sc, PADCTL_PAD_USB2,
1042 case PADCTL_PORT_ULPI:
1043 port->lane = search_pad_lane(sc, PADCTL_PAD_ULPI,
1046 case PADCTL_PORT_HSIC:
1047 port->lane = search_pad_lane(sc, PADCTL_PAD_HSIC,
1050 case PADCTL_PORT_USB3:
1051 port->lane = search_usb3_pad_lane(sc, port->idx);
1055 if (port->lane == NULL) {
1056 device_printf(sc->dev, "Cannot find lane for port: %s\n", name);
1060 port->enabled = true;
1069 parse_fdt(struct padctl_softc *sc, phandle_t base_node)
1075 node = ofw_bus_find_child(base_node, "pads");
1078 device_printf(sc->dev, "Cannot find pads subnode.\n");
1081 for (node = OF_child(node); node != 0; node = OF_peer(node)) {
1082 if (!ofw_bus_node_status_okay(node))
1084 rv = process_pad(sc, node);
1089 node = ofw_bus_find_child(base_node, "ports");
1091 device_printf(sc->dev, "Cannot find ports subnode.\n");
1094 for (node = OF_child(node); node != 0; node = OF_peer(node)) {
1095 if (!ofw_bus_node_status_okay(node))
1097 rv = process_port(sc, node);
1106 load_calibration(struct padctl_softc *sc)
1110 /* All XUSB pad calibrations are packed into single dword.*/
1111 reg = tegra_fuse_read_4(FUSE_XUSB_CALIB);
1112 sc->hs_curr_level_0 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(reg);
1113 sc->hs_curr_level_123 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(reg);
1114 sc->hs_iref_cap = FUSE_XUSB_CALIB_HS_IREF_CAP(reg);
1115 sc->hs_squelch_level = FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(reg);
1116 sc->hs_term_range_adj = FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(reg);
1119 /* -------------------------------------------------------------------------
1124 xusbpadctl_probe(device_t dev)
1127 if (!ofw_bus_status_okay(dev))
1130 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
1133 device_set_desc(dev, "Tegra XUSB phy");
1134 return (BUS_PROBE_DEFAULT);
1138 xusbpadctl_detach(device_t dev)
1141 /* This device is always present. */
1146 xusbpadctl_attach(device_t dev)
1148 struct padctl_softc * sc;
1150 struct padctl_port *port;
1153 sc = device_get_softc(dev);
1155 node = ofw_bus_get_node(dev);
1158 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1160 if (sc->mem_res == NULL) {
1161 device_printf(dev, "Cannot allocate memory resources\n");
1165 rv = hwreset_get_by_ofw_name(dev, 0, "padctl", &sc->rst);
1167 device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv);
1170 rv = hwreset_deassert(sc->rst);
1172 device_printf(dev, "Cannot unreset 'padctl' reset: %d\n", rv);
1176 load_calibration(sc);
1178 rv = parse_fdt(sc, node);
1180 device_printf(dev, "Cannot parse fdt configuration: %d\n", rv);
1183 for (i = 0; i < nitems(ports_tbl); i++) {
1184 port = ports_tbl + i;
1187 if (port->init == NULL)
1189 rv = port->init(sc, port);
1191 device_printf(dev, "Cannot init port '%s'\n",
1199 static device_method_t tegra_xusbpadctl_methods[] = {
1200 /* Device interface */
1201 DEVMETHOD(device_probe, xusbpadctl_probe),
1202 DEVMETHOD(device_attach, xusbpadctl_attach),
1203 DEVMETHOD(device_detach, xusbpadctl_detach),
1208 static devclass_t tegra_xusbpadctl_devclass;
1209 static DEFINE_CLASS_0(xusbpadctl, tegra_xusbpadctl_driver,
1210 tegra_xusbpadctl_methods, sizeof(struct padctl_softc));
1211 EARLY_DRIVER_MODULE(tegra_xusbpadctl, simplebus, tegra_xusbpadctl_driver,
1212 tegra_xusbpadctl_devclass, NULL, NULL, 73);