sys/arm/nvidia/tegra_ahci.c

   1 /*-
   2  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 /*
  31  * AHCI driver for Tegra SoCs.
  32  */
  33 #include <sys/param.h>
  34 #include <sys/module.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/conf.h>
  38 #include <sys/endian.h>
  39 #include <sys/kernel.h>
  40 #include <sys/lock.h>
  41 #include <sys/malloc.h>
  42 #include <sys/mutex.h>
  43 #include <sys/rman.h>
  44
  45 #include <machine/bus.h>
  46 #include <machine/resource.h>
  47
  48 #include <dev/ahci/ahci.h>
  49 #include <dev/extres/clk/clk.h>
  50 #include <dev/extres/hwreset/hwreset.h>
  51 #include <dev/extres/phy/phy.h>
  52 #include <dev/extres/regulator/regulator.h>
  53 #include <dev/fdt/fdt_common.h>
  54 #include <dev/fdt/fdt_pinctrl.h>
  55 #include <dev/ofw/ofw_bus.h>
  56 #include <dev/ofw/ofw_bus_subr.h>
  57
  58 #include <arm/nvidia/tegra_efuse.h>
  59 #include <arm/nvidia/tegra_pmc.h>
  60
  61 #define AHCI_WR4(_sc, _r, _v)   bus_write_4((_sc)->ctlr.r_mem, (_r), (_v))
  62 #define AHCI_RD4(_sc, _r)       bus_read_4((_sc)->ctlr.r_mem, (_r))
  63 #define SATA_WR4(_sc, _r, _v)   bus_write_4((_sc)->sata_mem, (_r), (_v))
  64 #define SATA_RD4(_sc, _r)       bus_read_4((_sc)->sata_mem, (_r))
  65
  66 static struct ofw_compat_data compat_data[] = {
  67         {"nvidia,tegra124-ahci",        1},
  68         {NULL,                  0}
  69 };
  70
  71 struct tegra_ahci_sc {
  72         struct ahci_controller  ctlr;   /* Must be first */
  73         device_t                dev;
  74         struct resource         *sata_mem;
  75         clk_t                   clk_sata;
  76         clk_t                   clk_sata_oob;
  77         clk_t                   clk_pll_e;
  78         clk_t                   clk_cml;
  79         hwreset_t               hwreset_sata;
  80         hwreset_t               hwreset_sata_oob;
  81         hwreset_t               hwreset_sata_cold;
  82         regulator_t             supply_hvdd;
  83         regulator_t             supply_vddio;
  84         regulator_t             supply_avdd;
  85         regulator_t             supply_target_5v;
  86         regulator_t             supply_target_12v;
  87         phy_t                   phy;
  88 };
  89
  90 struct sata_pad_calibration {
  91         uint32_t gen1_tx_amp;
  92         uint32_t gen1_tx_peak;
  93         uint32_t gen2_tx_amp;
  94         uint32_t gen2_tx_peak;
  95 };
  96
  97 static const struct sata_pad_calibration tegra124_pad_calibration[] = {
  98         {0x18, 0x04, 0x18, 0x0a},
  99         {0x0e, 0x04, 0x14, 0x0a},
 100         {0x0e, 0x07, 0x1a, 0x0e},
 101         {0x14, 0x0e, 0x1a, 0x0e},
 102 };
 103
 104 #define SATA_CONFIGURATION                      0x180
 105 #define  SATA_CONFIGURATION_EN_FPCI                     (1 << 0)
 106
 107 #define SATA_FPCI_BAR5                          0x94
 108 #define  SATA_FPCI_BAR5_START_SHIFT                     4
 109
 110 #define SATA_INTR_MASK                          0x188
 111 #define SATA_INTR_MASK_IP_INT_MASK                      (1 << 16)
 112
 113 #define SCFG_OFFSET                             0x1000
 114
 115 #define T_SATA0_CFG_1                           0x04
 116 #define  T_SATA0_CFG_1_IO_SPACE                         (1 << 0)
 117 #define  T_SATA0_CFG_1_MEMORY_SPACE                     (1 << 1)
 118 #define  T_SATA0_CFG_1_BUS_MASTER                       (1 << 2)
 119 #define  T_SATA0_CFG_1_SERR                             (1 << 8)
 120
 121 #define T_SATA0_CFG_9                           0x24
 122 #define  T_SATA0_CFG_9_BASE_ADDRESS_SHIFT               13
 123
 124 #define T_SATA0_AHCI_HBA_CAP_BKDR               0x300
 125 #define T_SATA0_BKDOOR_CC                       0x4a4
 126 #define T_SATA0_CFG_SATA                        0x54c
 127 #define  T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN           (1 << 12)
 128
 129 #define T_SATA0_CFG_MISC                        0x550
 130 #define T_SATA0_INDEX                           0x680
 131
 132 #define T_SATA0_CHX_PHY_CTRL1_GEN1              0x690
 133 #define  T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK        0xff
 134 #define  T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT       8
 135 #define  T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK         0xff
 136 #define  T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT        0
 137
 138
 139 #define T_SATA0_CHX_PHY_CTRL1_GEN2              0x694
 140 #define  T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK        0xff
 141 #define  T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT       12
 142 #define  T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK         0xff
 143 #define  T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT        0
 144
 145 #define T_SATA0_CHX_PHY_CTRL2                   0x69c
 146 #define  T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1            0x23
 147
 148 #define T_SATA0_CHX_PHY_CTRL11                  0x6d0
 149 #define  T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ              (0x2800 << 16)
 150
 151 #define FUSE_SATA_CALIB                         0x124
 152 #define FUSE_SATA_CALIB_MASK                    0x3
 153
 154
 155 #define SATA_AUX_MISC_CNTL                      0x1108
 156 #define SATA_AUX_PAD_PLL_CTRL_0                 0x1120
 157 #define SATA_AUX_PAD_PLL_CTRL_1                 0x1124
 158 #define SATA_AUX_PAD_PLL_CTRL_2                 0x1128
 159 #define SATA_AUX_PAD_PLL_CTRL_3                 0x112c
 160
 161 #define T_AHCI_HBA_CCC_PORTS                    0x0018
 162 #define T_AHCI_HBA_CAP_BKDR                     0x00A0
 163 #define  T_AHCI_HBA_CAP_BKDR_S64A                       (1 << 31)
 164 #define  T_AHCI_HBA_CAP_BKDR_SNCQ                       (1 << 30)
 165 #define  T_AHCI_HBA_CAP_BKDR_SSNTF                      (1 << 29)
 166 #define  T_AHCI_HBA_CAP_BKDR_SMPS                       (1 << 28)
 167 #define  T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP              (1 << 27)
 168 #define  T_AHCI_HBA_CAP_BKDR_SALP                       (1 << 26)
 169 #define  T_AHCI_HBA_CAP_BKDR_SAL                        (1 << 25)
 170 #define  T_AHCI_HBA_CAP_BKDR_SUPP_CLO                   (1 << 24)
 171 #define  T_AHCI_HBA_CAP_BKDR_INTF_SPD_SUPP(x)           (((x) & 0xF) << 20)
 172 #define  T_AHCI_HBA_CAP_BKDR_SUPP_NONZERO_OFFSET        (1 << 19)
 173 #define  T_AHCI_HBA_CAP_BKDR_SUPP_AHCI_ONLY             (1 << 18)
 174 #define  T_AHCI_HBA_CAP_BKDR_SUPP_PM                    (1 << 17)
 175 #define  T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING              (1 << 16)
 176 #define  T_AHCI_HBA_CAP_BKDR_PIO_MULT_DRQ_BLK           (1 << 15)
 177 #define  T_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP             (1 << 14)
 178 #define  T_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP             (1 << 13)
 179 #define  T_AHCI_HBA_CAP_BKDR_NUM_CMD_SLOTS(x)           (((x) & 0x1F) <<  8)
 180 #define  T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING         (1 <<  7)
 181 #define  T_AHCI_HBA_CAP_BKDR_ENCL_MGMT_SUPP             (1 <<  6)
 182 #define  T_AHCI_HBA_CAP_BKDR_EXT_SATA                   (1 <<  5)
 183 #define  T_AHCI_HBA_CAP_BKDR_NUM_PORTS(x)               (((x) & 0xF) <<  0)
 184
 185 #define T_AHCI_PORT_BKDR                        0x0170
 186
 187 #define  T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE_VAL(x) (((x) & 0xFF) << 24)
 188 #define  T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE_VAL(x) (((x) & 0x1F) << 16)
 189 #define  T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE        (1 << 15)
 190 #define  T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE        (1 << 14)
 191 #define  T_AHCI_PORT_BKDR_PXDEVSLP_DM(x)                (((x) & 0xF) << 10)
 192 #define  T_AHCI_PORT_BKDR_PORT_UNCONNECTED              (1 <<  9)
 193 #define  T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_CLAMP_THIS_CH  (1 <<  8)
 194 #define  T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP (1 <<  7)
 195 #define  T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_TXRXCLK_CLAMP  (1 <<  6)
 196 #define  T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP (1 <<  5)
 197 #define  T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_DEVCLK_CLAMP   (1 <<  4)
 198 #define  T_AHCI_PORT_BKDR_HOTPLUG_CAP                   (1 <<  3)
 199 #define  T_AHCI_PORT_BKDR_MECH_SWITCH                   (1 <<  2)
 200 #define  T_AHCI_PORT_BKDR_COLD_PRSN_DET                 (1 <<  1)
 201 #define  T_AHCI_PORT_BKDR_EXT_SATA_SUPP                 (1 <<  0)
 202
 203 static int
 204 get_fdt_resources(struct tegra_ahci_sc *sc, phandle_t node)
 205 {
 206         int rv;
 207
 208
 209         rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-supply",
 210             &sc->supply_hvdd );
 211         if (rv != 0) {
 212                 device_printf(sc->dev, "Cannot get 'hvdd' regulator\n");
 213                 return (ENXIO);
 214         }
 215         rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-supply",
 216             &sc->supply_vddio);
 217         if (rv != 0) {
 218                 device_printf(sc->dev, "Cannot get 'vddio' regulator\n");
 219                 return (ENXIO);
 220         }
 221         rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-supply",
 222             &sc->supply_avdd);
 223         if (rv != 0) {
 224                 device_printf(sc->dev, "Cannot get 'avdd' regulator\n");
 225                 return (ENXIO);
 226         }
 227         rv = regulator_get_by_ofw_property(sc->dev, 0, "target-5v-supply",
 228             &sc->supply_target_5v);
 229         if (rv != 0) {
 230                 device_printf(sc->dev, "Cannot get 'target-5v' regulator\n");
 231                 return (ENXIO);
 232         }
 233         rv = regulator_get_by_ofw_property(sc->dev, 0, "target-12v-supply",
 234             &sc->supply_target_12v);
 235         if (rv != 0) {
 236                 device_printf(sc->dev, "Cannot get 'target-12v' regulator\n");
 237                 return (ENXIO);
 238         }
 239
 240         rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata", &sc->hwreset_sata );
 241         if (rv != 0) {
 242                 device_printf(sc->dev, "Cannot get 'sata' reset\n");
 243                 return (ENXIO);
 244         }
 245         rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-oob",
 246             &sc->hwreset_sata_oob);
 247         if (rv != 0) {
 248                 device_printf(sc->dev, "Cannot get 'sata oob' reset\n");
 249                 return (ENXIO);
 250         }
 251         rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-cold",
 252             &sc->hwreset_sata_cold);
 253         if (rv != 0) {
 254                 device_printf(sc->dev, "Cannot get 'sata cold' reset\n");
 255                 return (ENXIO);
 256         }
 257
 258         rv = phy_get_by_ofw_name(sc->dev, 0, "sata-0", &sc->phy);
 259         if (rv != 0) {
 260                 device_printf(sc->dev, "Cannot get 'sata' phy\n");
 261                 return (ENXIO);
 262         }
 263
 264         rv = clk_get_by_ofw_name(sc->dev, 0, "sata", &sc->clk_sata);
 265         if (rv != 0) {
 266                 device_printf(sc->dev, "Cannot get 'sata' clock\n");
 267                 return (ENXIO);
 268         }
 269         rv = clk_get_by_ofw_name(sc->dev, 0, "sata-oob", &sc->clk_sata_oob);
 270         if (rv != 0) {
 271                 device_printf(sc->dev, "Cannot get 'sata oob' clock\n");
 272                 return (ENXIO);
 273         }
 274         rv = clk_get_by_ofw_name(sc->dev, 0, "cml1", &sc->clk_cml);
 275         if (rv != 0) {
 276                 device_printf(sc->dev, "Cannot get 'cml1' clock\n");
 277                 return (ENXIO);
 278         }
 279         rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e);
 280         if (rv != 0) {
 281                 device_printf(sc->dev, "Cannot get 'pll_e' clock\n");
 282                 return (ENXIO);
 283         }
 284         return (0);
 285 }
 286
 287 static int
 288 enable_fdt_resources(struct tegra_ahci_sc *sc)
 289 {
 290         int rv;
 291
 292         rv = regulator_enable(sc->supply_hvdd);
 293         if (rv != 0) {
 294                 device_printf(sc->dev, "Cannot enable  'hvdd' regulator\n");
 295                 return (rv);
 296         }
 297         rv = regulator_enable(sc->supply_vddio);
 298         if (rv != 0) {
 299                 device_printf(sc->dev, "Cannot enable  'vddio' regulator\n");
 300                 return (rv);
 301         }
 302         rv = regulator_enable(sc->supply_avdd);
 303         if (rv != 0) {
 304                 device_printf(sc->dev, "Cannot enable  'avdd' regulator\n");
 305                 return (rv);
 306         }
 307         rv = regulator_enable(sc->supply_target_5v);
 308         if (rv != 0) {
 309                 device_printf(sc->dev,
 310                     "Cannot enable  'target-5v' regulator\n");
 311                 return (rv);
 312         }
 313         rv = regulator_enable(sc->supply_target_12v);
 314         if (rv != 0) {
 315                 device_printf(sc->dev,
 316                     "Cannot enable  'sc->target-12v' regulator\n");
 317                 return (rv);
 318         }
 319
 320         /* Stop clocks */
 321         clk_stop(sc->clk_sata);
 322         clk_stop(sc->clk_sata_oob);
 323         tegra_powergate_power_off(TEGRA_POWERGATE_SAX);
 324
 325         rv = hwreset_assert(sc->hwreset_sata);
 326         if (rv != 0) {
 327                 device_printf(sc->dev, "Cannot assert 'sata' reset\n");
 328                 return (rv);
 329         }
 330         rv = hwreset_assert(sc->hwreset_sata_oob);
 331         if (rv != 0) {
 332                 device_printf(sc->dev, "Cannot assert 'sata oob' reset\n");
 333                 return (rv);
 334         }
 335
 336         rv = hwreset_assert(sc->hwreset_sata_cold);
 337         if (rv != 0) {
 338                 device_printf(sc->dev, "Cannot assert 'sata cold' reset\n");
 339                 return (rv);
 340         }
 341         rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SAX,
 342             sc->clk_sata, sc->hwreset_sata);
 343         if (rv != 0) {
 344                 device_printf(sc->dev, "Cannot enable 'SAX' powergate\n");
 345                 return (rv);
 346         }
 347
 348         rv = clk_enable(sc->clk_sata_oob);
 349         if (rv != 0) {
 350                 device_printf(sc->dev, "Cannot enable 'sata oob' clock\n");
 351                 return (rv);
 352         }
 353         rv = clk_enable(sc->clk_cml);
 354         if (rv != 0) {
 355                 device_printf(sc->dev, "Cannot enable 'cml' clock\n");
 356                 return (rv);
 357         }
 358         rv = clk_enable(sc->clk_pll_e);
 359         if (rv != 0) {
 360                 device_printf(sc->dev, "Cannot enable 'pll e' clock\n");
 361                 return (rv);
 362         }
 363
 364         rv = hwreset_deassert(sc->hwreset_sata_cold);
 365         if (rv != 0) {
 366                 device_printf(sc->dev, "Cannot unreset 'sata cold' reset\n");
 367                 return (rv);
 368         }
 369         rv = hwreset_deassert(sc->hwreset_sata_oob);
 370         if (rv != 0) {
 371                 device_printf(sc->dev, "Cannot unreset 'sata oob' reset\n");
 372                 return (rv);
 373         }
 374
 375         rv = phy_enable(sc->dev, sc->phy);
 376         if (rv != 0) {
 377                 device_printf(sc->dev, "Cannot enable SATA phy\n");
 378                 return (rv);
 379         }
 380
 381         return (0);
 382 }
 383
 384 static int
 385 tegra_ahci_ctrl_init(struct tegra_ahci_sc *sc)
 386 {
 387         uint32_t val;
 388         const struct sata_pad_calibration *calib;
 389
 390         val = SATA_RD4(sc, SATA_CONFIGURATION);
 391         val |= SATA_CONFIGURATION_EN_FPCI;
 392         SATA_WR4(sc, SATA_CONFIGURATION, val);
 393
 394
 395         /* Pad calibration. */
 396         val = tegra_fuse_read_4(FUSE_SATA_CALIB);
 397         calib = tegra124_pad_calibration + (val & FUSE_SATA_CALIB_MASK);
 398         SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 1);
 399
 400         val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
 401         val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK <<
 402             T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT);
 403         val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK <<
 404             T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT);
 405         val |= calib->gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
 406         val |= calib->gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
 407         SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1, val);
 408
 409         val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
 410         val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK <<
 411             T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT);
 412         val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK <<
 413             T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT);
 414         val |= calib->gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT;
 415         val |= calib->gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT;
 416         SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2, val);
 417
 418         SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11,
 419             T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ);
 420
 421         SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2,
 422             T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1);
 423
 424         SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 0);
 425
 426         /* Set device ID. */
 427         val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA);
 428         val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
 429         SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA, val);
 430
 431         SATA_WR4(sc, SCFG_OFFSET + T_SATA0_BKDOOR_CC, 0x01060100);
 432
 433         val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA);
 434         val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
 435         SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA, val);
 436
 437         /* Enable IO & memory access, bus master mode */
 438         val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_1);
 439         val |= T_SATA0_CFG_1_IO_SPACE;
 440         val |= T_SATA0_CFG_1_MEMORY_SPACE;
 441         val |= T_SATA0_CFG_1_BUS_MASTER;
 442         val |= T_SATA0_CFG_1_SERR;
 443         SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_1, val);
 444
 445         /* SATA MMIO. */
 446         SATA_WR4(sc, SATA_FPCI_BAR5, 0x10000 << SATA_FPCI_BAR5_START_SHIFT);
 447         /* AHCI bar */
 448         SATA_WR4(sc,  SCFG_OFFSET + T_SATA0_CFG_9,
 449             0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT);
 450
 451         /* Unmask  interrupts. */
 452         val = SATA_RD4(sc, SATA_INTR_MASK);
 453         val |= SATA_INTR_MASK_IP_INT_MASK;
 454         SATA_WR4(sc, SATA_INTR_MASK, val);
 455
 456         return (0);
 457 }
 458
 459 static int
 460 tegra_ahci_ctlr_reset(device_t dev)
 461 {
 462         struct tegra_ahci_sc *sc;
 463         int rv;
 464         uint32_t reg;
 465
 466         sc = device_get_softc(dev);
 467         rv = ahci_ctlr_reset(dev);
 468         if (rv != 0)
 469                 return (0);
 470         AHCI_WR4(sc, T_AHCI_HBA_CCC_PORTS, 1);
 471
 472         /* Overwrite AHCI capabilites. */
 473         reg  = AHCI_RD4(sc, T_AHCI_HBA_CAP_BKDR);
 474         reg &= ~T_AHCI_HBA_CAP_BKDR_NUM_PORTS(~0);
 475         reg |= T_AHCI_HBA_CAP_BKDR_NUM_PORTS(0);
 476         reg |= T_AHCI_HBA_CAP_BKDR_EXT_SATA;
 477         reg |= T_AHCI_HBA_CAP_BKDR_ENCL_MGMT_SUPP;
 478         reg |= T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING;
 479         reg |= T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING;
 480         reg |= T_AHCI_HBA_CAP_BKDR_SUPP_PM;
 481         reg |= T_AHCI_HBA_CAP_BKDR_SUPP_CLO;
 482         reg |= T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP;
 483         AHCI_WR4(sc, T_AHCI_HBA_CAP_BKDR, reg);
 484
 485         /* Overwrite AHCI portcapabilites. */
 486         reg  = AHCI_RD4(sc, T_AHCI_PORT_BKDR);
 487         reg |= T_AHCI_PORT_BKDR_COLD_PRSN_DET;
 488         reg |= T_AHCI_PORT_BKDR_HOTPLUG_CAP;
 489         reg |= T_AHCI_PORT_BKDR_EXT_SATA_SUPP;
 490         AHCI_WR4(sc, T_AHCI_PORT_BKDR, reg);
 491
 492         return (0);
 493 }
 494
 495 static int
 496 tegra_ahci_probe(device_t dev)
 497 {
 498
 499         if (!ofw_bus_status_okay(dev))
 500                 return (ENXIO);
 501
 502         if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
 503                 return (ENXIO);
 504
 505         device_set_desc_copy(dev, "AHCI SATA controller");
 506         return (BUS_PROBE_DEFAULT);
 507 }
 508
 509 static int
 510 tegra_ahci_attach(device_t dev)
 511 {
 512         struct tegra_ahci_sc *sc;
 513         struct ahci_controller *ctlr;
 514         phandle_t node;
 515         int rv, rid;
 516
 517         sc = device_get_softc(dev);
 518         sc->dev = dev;
 519         ctlr = &sc->ctlr;
 520         node = ofw_bus_get_node(dev);
 521
 522         ctlr->r_rid = 0;
 523         ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 524             &ctlr->r_rid, RF_ACTIVE);
 525         if (ctlr->r_mem == NULL)
 526                 return (ENXIO);
 527
 528         rid = 1;
 529         sc->sata_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 530             &rid, RF_ACTIVE);
 531         if (sc->sata_mem == NULL) {
 532                 rv = ENXIO;
 533                 goto fail;
 534         }
 535         rv = get_fdt_resources(sc, node);
 536         if (rv != 0) {
 537                 device_printf(sc->dev, "Failed to allocate FDT resource(s)\n");
 538                 goto fail;
 539         }
 540
 541         rv = enable_fdt_resources(sc);
 542         if (rv != 0) {
 543                 device_printf(sc->dev, "Failed to enable FDT resource(s)\n");
 544                 goto fail;
 545         }
 546         rv = tegra_ahci_ctrl_init(sc);
 547         if (rv != 0) {
 548                 device_printf(sc->dev, "Failed to initialize controller)\n");
 549                 goto fail;
 550         }
 551
 552         /* Setup controller defaults. */
 553         ctlr->msi = 0;
 554         ctlr->numirqs = 1;
 555         ctlr->ccc = 0;
 556
 557         /* Reset controller. */
 558         rv = tegra_ahci_ctlr_reset(dev);
 559         if (rv != 0)
 560                 goto fail;
 561         rv = ahci_attach(dev);
 562         return (rv);
 563
 564 fail:
 565         /* XXX FDT  stuff */
 566         if (sc->sata_mem != NULL)
 567                 bus_release_resource(dev, SYS_RES_MEMORY, 1, sc->sata_mem);
 568         if (ctlr->r_mem != NULL)
 569                 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
 570                     ctlr->r_mem);
 571         return (rv);
 572 }
 573
 574 static int
 575 tegra_ahci_detach(device_t dev)
 576 {
 577
 578         ahci_detach(dev);
 579         return (0);
 580 }
 581
 582 static int
 583 tegra_ahci_suspend(device_t dev)
 584 {
 585         struct tegra_ahci_sc *sc = device_get_softc(dev);
 586
 587         bus_generic_suspend(dev);
 588         /* Disable interupts, so the state change(s) doesn't trigger. */
 589         ATA_OUTL(sc->ctlr.r_mem, AHCI_GHC,
 590              ATA_INL(sc->ctlr.r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
 591         return (0);
 592 }
 593
 594 static int
 595 tegra_ahci_resume(device_t dev)
 596 {
 597         int res;
 598
 599         if ((res = tegra_ahci_ctlr_reset(dev)) != 0)
 600                 return (res);
 601         ahci_ctlr_setup(dev);
 602         return (bus_generic_resume(dev));
 603 }
 604
 605 static device_method_t tegra_ahci_methods[] = {
 606         DEVMETHOD(device_probe,         tegra_ahci_probe),
 607         DEVMETHOD(device_attach,        tegra_ahci_attach),
 608         DEVMETHOD(device_detach,        tegra_ahci_detach),
 609         DEVMETHOD(device_suspend,       tegra_ahci_suspend),
 610         DEVMETHOD(device_resume,        tegra_ahci_resume),
 611         DEVMETHOD(bus_print_child,      ahci_print_child),
 612         DEVMETHOD(bus_alloc_resource,   ahci_alloc_resource),
 613         DEVMETHOD(bus_release_resource, ahci_release_resource),
 614         DEVMETHOD(bus_setup_intr,       ahci_setup_intr),
 615         DEVMETHOD(bus_teardown_intr,    ahci_teardown_intr),
 616         DEVMETHOD(bus_child_location_str, ahci_child_location_str),
 617         DEVMETHOD(bus_get_dma_tag,      ahci_get_dma_tag),
 618
 619         DEVMETHOD_END
 620 };
 621
 622 static devclass_t tegra_ahci_devclass;
 623 static DEFINE_CLASS_0(ahci, tegra_ahci_driver, tegra_ahci_methods,
 624     sizeof(struct tegra_ahci_sc));
 625 DRIVER_MODULE(tegra_ahci, simplebus, tegra_ahci_driver, tegra_ahci_devclass,
 626     NULL, NULL);