2 * Copyright (c) 2015 Michal Meloun
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/clock.h>
34 #include <sys/kernel.h>
35 #include <sys/limits.h>
37 #include <sys/mutex.h>
38 #include <sys/module.h>
39 #include <sys/resource.h>
42 #include <machine/bus.h>
43 #include <machine/resource.h>
45 #include <dev/extres/clk/clk.h>
46 #include <dev/extres/hwreset/hwreset.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
50 #include <arm/nvidia/tegra_efuse.h>
52 #define FUSES_START 0x100
53 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (FUSES_START + (_r)))
56 struct tegra_efuse_softc {
58 struct resource *mem_res;
60 struct efuse_soc *soc;
65 struct tegra_efuse_softc *dev_sc;
66 struct tegra_sku_info tegra_sku_info;
67 static char *tegra_rev_name[] = {
68 [TEGRA_REVISION_UNKNOWN] = "unknown",
69 [TEGRA_REVISION_A01] = "A01",
70 [TEGRA_REVISION_A02] = "A02",
71 [TEGRA_REVISION_A03] = "A03",
72 [TEGRA_REVISION_A03p] = "A03 prime",
73 [TEGRA_REVISION_A04] = "A04",
77 void (*init)(struct tegra_efuse_softc *sc,
78 struct tegra_sku_info *sku);
81 static void tegra124_init(struct tegra_efuse_softc *sc,
82 struct tegra_sku_info *sku);
83 struct efuse_soc tegra124_efuse_soc = {
84 .init = tegra124_init,
87 static void tegra210_init(struct tegra_efuse_softc *sc,
88 struct tegra_sku_info *sku);
89 struct efuse_soc tegra210_efuse_soc = {
90 .init = tegra210_init,
93 static struct ofw_compat_data compat_data[] = {
94 {"nvidia,tegra124-efuse", (intptr_t)&tegra124_efuse_soc},
95 {"nvidia,tegra210-efuse", (intptr_t)&tegra210_efuse_soc},
99 /* ---------------------- Tegra 124 specific code & data --------------- */
100 #define TEGRA124_CPU_PROCESS_CORNERS 2
101 #define TEGRA124_GPU_PROCESS_CORNERS 2
102 #define TEGRA124_SOC_PROCESS_CORNERS 2
104 #define TEGRA124_FUSE_SKU_INFO 0x10
105 #define TEGRA124_FUSE_CPU_SPEEDO_0 0x14
106 #define TEGRA124_FUSE_CPU_IDDQ 0x18
107 #define TEGRA124_FUSE_FT_REV 0x28
108 #define TEGRA124_FUSE_CPU_SPEEDO_1 0x2c
109 #define TEGRA124_FUSE_CPU_SPEEDO_2 0x30
110 #define TEGRA124_FUSE_SOC_SPEEDO_0 0x34
111 #define TEGRA124_FUSE_SOC_SPEEDO_1 0x38
112 #define TEGRA124_FUSE_SOC_SPEEDO_2 0x3c
113 #define TEGRA124_FUSE_SOC_IDDQ 0x40
114 #define TEGRA124_FUSE_GPU_IDDQ 0x128
117 TEGRA124_THRESHOLD_INDEX_0,
118 TEGRA124_THRESHOLD_INDEX_1,
119 TEGRA124_THRESHOLD_INDEX_COUNT,
122 static uint32_t tegra124_cpu_process_speedos[][TEGRA124_CPU_PROCESS_CORNERS] =
128 static uint32_t tegra124_gpu_process_speedos[][TEGRA124_GPU_PROCESS_CORNERS] =
134 static uint32_t tegra124_soc_process_speedos[][TEGRA124_SOC_PROCESS_CORNERS] =
142 tegra124_rev_sku_to_speedo_ids(struct tegra_efuse_softc *sc,
143 struct tegra_sku_info *sku, int *threshold)
147 sku->cpu_speedo_id = 0;
148 sku->soc_speedo_id = 0;
149 sku->gpu_speedo_id = 0;
150 *threshold = TEGRA124_THRESHOLD_INDEX_0;
152 switch (sku->sku_id) {
153 case 0x00: /* Eng sku */
156 /* Using the default */
159 sku->cpu_speedo_id = 2;
165 sku->cpu_speedo_id = 2;
166 sku->soc_speedo_id = 0;
167 sku->gpu_speedo_id = 1;
168 *threshold = TEGRA124_THRESHOLD_INDEX_0;
173 sku->cpu_speedo_id = 1;
174 sku->soc_speedo_id = 1;
175 sku->gpu_speedo_id = 1;
176 *threshold = TEGRA124_THRESHOLD_INDEX_1;
181 sku->cpu_speedo_id = 4;
182 sku->soc_speedo_id = 2;
183 sku->gpu_speedo_id = 3;
184 *threshold = TEGRA124_THRESHOLD_INDEX_1;
187 device_printf(sc->dev, " Unknown SKU ID %d\n", sku->sku_id);
193 tegra124_init(struct tegra_efuse_softc *sc, struct tegra_sku_info *sku)
197 sku->sku_id = RD4(sc, TEGRA124_FUSE_SKU_INFO);
198 sku->soc_iddq_value = RD4(sc, TEGRA124_FUSE_SOC_IDDQ);
199 sku->cpu_iddq_value = RD4(sc, TEGRA124_FUSE_CPU_IDDQ);
200 sku->gpu_iddq_value = RD4(sc, TEGRA124_FUSE_GPU_IDDQ);
201 sku->soc_speedo_value = RD4(sc, TEGRA124_FUSE_SOC_SPEEDO_0);
202 sku->cpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_0);
203 sku->gpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_2);
205 if (sku->cpu_speedo_value == 0) {
206 device_printf(sc->dev, "CPU Speedo value is not fused.\n");
210 tegra124_rev_sku_to_speedo_ids(sc, sku, &threshold);
212 for (i = 0; i < TEGRA124_SOC_PROCESS_CORNERS; i++) {
213 if (sku->soc_speedo_value <
214 tegra124_soc_process_speedos[threshold][i])
217 sku->soc_process_id = i;
219 for (i = 0; i < TEGRA124_CPU_PROCESS_CORNERS; i++) {
220 if (sku->cpu_speedo_value <
221 tegra124_cpu_process_speedos[threshold][i])
224 sku->cpu_process_id = i;
226 for (i = 0; i < TEGRA124_GPU_PROCESS_CORNERS; i++) {
227 if (sku->gpu_speedo_value <
228 tegra124_gpu_process_speedos[threshold][i])
231 sku->gpu_process_id = i;
234 /* ----------------- End of Tegra 124 specific code & data --------------- */
236 /* -------------------- Tegra 201 specific code & data ------------------- */
237 #define TEGRA210_CPU_PROCESS_CORNERS 2
238 #define TEGRA210_GPU_PROCESS_CORNERS 2
239 #define TEGRA210_SOC_PROCESS_CORNERS 3
241 #define TEGRA210_FUSE_SKU_INFO 0x010
242 #define TEGRA210_FUSE_CPU_SPEEDO_0 0x014
243 #define TEGRA210_FUSE_CPU_IDDQ 0x018
244 #define TEGRA210_FUSE_FT_REV 0x028
245 #define TEGRA210_FUSE_CPU_SPEEDO_1 0x02c
246 #define TEGRA210_FUSE_CPU_SPEEDO_2 0x030
247 #define TEGRA210_FUSE_SOC_SPEEDO_0 0x034
248 #define TEGRA210_FUSE_SOC_SPEEDO_1 0x038
249 #define TEGRA210_FUSE_SOC_SPEEDO_2 0x03c
250 #define TEGRA210_FUSE_SOC_IDDQ 0x040
251 #define TEGRA210_FUSE_GPU_IDDQ 0x128
252 #define TEGRA210_FUSE_SPARE 0x270
255 TEGRA210_THRESHOLD_INDEX_0,
256 TEGRA210_THRESHOLD_INDEX_1,
257 TEGRA210_THRESHOLD_INDEX_COUNT,
260 static uint32_t tegra210_cpu_process_speedos[][TEGRA210_CPU_PROCESS_CORNERS] =
266 static uint32_t tegra210_gpu_process_speedos[][TEGRA210_GPU_PROCESS_CORNERS] =
268 {UINT_MAX, UINT_MAX},
269 {UINT_MAX, UINT_MAX},
272 static uint32_t tegra210_soc_process_speedos[][TEGRA210_SOC_PROCESS_CORNERS] =
274 {1950, 2100, UINT_MAX},
275 {1950, 2100, UINT_MAX},
279 tegra210_get_speedo_revision(struct tegra_efuse_softc *sc)
286 /* Revision i encoded in spare fields */
287 reg = RD4(sc, TEGRA210_FUSE_SPARE + 2 * 4);
288 val |= (reg & 1) << 0;
289 reg = RD4(sc, TEGRA210_FUSE_SPARE + 3 * 4);
290 val |= (reg & 1) << 1;
291 reg = RD4(sc, TEGRA210_FUSE_SPARE + 4 * 4);
292 val |= (reg & 1) << 2;
299 tegra210_rev_sku_to_speedo_ids(struct tegra_efuse_softc *sc,
300 struct tegra_sku_info *sku, int speedo_rev, int *threshold)
304 sku->cpu_speedo_id = 0;
305 sku->soc_speedo_id = 0;
306 sku->gpu_speedo_id = 0;
307 *threshold = TEGRA210_THRESHOLD_INDEX_0;
309 switch (sku->sku_id) {
310 case 0x00: /* Eng sku */
311 case 0x01: /* Eng sku */
317 sku->gpu_speedo_id = 1;
321 sku->gpu_speedo_id = 1;
322 sku->cpu_speedo_id = 1;
326 device_printf(sc->dev, " Unknown SKU ID %d\n", sku->sku_id);
333 tegra210_init(struct tegra_efuse_softc *sc, struct tegra_sku_info *sku)
335 int i, threshold, speedo_rev;
336 uint32_t cpu_speedo[3], soc_speedo[3];
338 cpu_speedo[0] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_0);
339 cpu_speedo[1] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_1);
340 cpu_speedo[2] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_2);
341 soc_speedo[0] = RD4(sc, TEGRA210_FUSE_SOC_SPEEDO_0);
342 soc_speedo[1] = RD4(sc, TEGRA210_FUSE_SOC_SPEEDO_1);
343 soc_speedo[2] = RD4(sc, TEGRA210_FUSE_SOC_SPEEDO_2);
346 sku->cpu_iddq_value = RD4(sc, TEGRA210_FUSE_CPU_IDDQ);
347 sku->soc_iddq_value = RD4(sc, TEGRA210_FUSE_SOC_IDDQ);
348 sku->gpu_iddq_value = RD4(sc, TEGRA210_FUSE_GPU_IDDQ);
350 speedo_rev = tegra210_get_speedo_revision(sc);
351 device_printf(sc->dev, " Speedo revision: %u\n", speedo_rev);
353 if (speedo_rev >= 3) {
354 sku->cpu_speedo_value = cpu_speedo[0];
355 sku->gpu_speedo_value = cpu_speedo[2];
356 sku->soc_speedo_value = soc_speedo[0];
357 } else if (speedo_rev == 2) {
358 sku->cpu_speedo_value =
359 (-1938 + (1095 * cpu_speedo[0] / 100)) / 10;
360 sku->gpu_speedo_value =
361 (-1662 + (1082 * cpu_speedo[2] / 100)) / 10;
362 sku->soc_speedo_value =
363 ( -705 + (1037 * soc_speedo[0] / 100)) / 10;
365 sku->cpu_speedo_value = 2100;
366 sku->gpu_speedo_value = cpu_speedo[2] - 75;
367 sku->soc_speedo_value = 1900;
370 tegra210_rev_sku_to_speedo_ids(sc, sku, speedo_rev, &threshold);
372 for (i = 0; i < TEGRA210_SOC_PROCESS_CORNERS; i++) {
373 if (sku->soc_speedo_value <
374 tegra210_soc_process_speedos[threshold][i])
377 sku->soc_process_id = i;
379 for (i = 0; i < TEGRA210_CPU_PROCESS_CORNERS; i++) {
380 if (sku->cpu_speedo_value <
381 tegra210_cpu_process_speedos[threshold][i])
384 sku->cpu_process_id = i;
386 for (i = 0; i < TEGRA210_GPU_PROCESS_CORNERS; i++) {
387 if (sku->gpu_speedo_value <
388 tegra210_gpu_process_speedos[threshold][i])
391 sku->gpu_process_id = i;
395 /* ----------------- End of Tegra 210 specific code & data --------------- */
399 tegra_fuse_read_4(int addr) {
401 panic("tegra_fuse_read_4 called too early");
402 return (RD4(dev_sc, addr));
406 tegra_efuse_dump_sku(void)
408 printf(" TEGRA SKU Info:\n");
409 printf(" chip_id: %u\n", tegra_sku_info.chip_id);
410 printf(" sku_id: %u\n", tegra_sku_info.sku_id);
411 printf(" cpu_process_id: %u\n", tegra_sku_info.cpu_process_id);
412 printf(" cpu_speedo_id: %u\n", tegra_sku_info.cpu_speedo_id);
413 printf(" cpu_speedo_value: %u\n", tegra_sku_info.cpu_speedo_value);
414 printf(" cpu_iddq_value: %u\n", tegra_sku_info.cpu_iddq_value);
415 printf(" soc_process_id: %u\n", tegra_sku_info.soc_process_id);
416 printf(" soc_speedo_id: %u\n", tegra_sku_info.soc_speedo_id);
417 printf(" soc_speedo_value: %u\n", tegra_sku_info.soc_speedo_value);
418 printf(" soc_iddq_value: %u\n", tegra_sku_info.soc_iddq_value);
419 printf(" gpu_process_id: %u\n", tegra_sku_info.gpu_process_id);
420 printf(" gpu_speedo_id: %u\n", tegra_sku_info.gpu_speedo_id);
421 printf(" gpu_speedo_value: %u\n", tegra_sku_info.gpu_speedo_value);
422 printf(" gpu_iddq_value: %u\n", tegra_sku_info.gpu_iddq_value);
423 printf(" revision: %s\n", tegra_rev_name[tegra_sku_info.revision]);
427 tegra_efuse_probe(device_t dev)
429 if (!ofw_bus_status_okay(dev))
432 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
435 return (BUS_PROBE_DEFAULT);
439 tegra_efuse_attach(device_t dev)
442 struct tegra_efuse_softc *sc;
444 sc = device_get_softc(dev);
446 sc->soc = (struct efuse_soc *)ofw_bus_search_compatible(dev,
447 compat_data)->ocd_data;
449 /* Get the memory resource for the register mapping. */
451 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
453 if (sc->mem_res == NULL) {
454 device_printf(dev, "Cannot map registers.\n");
460 rv = clk_get_by_ofw_name(dev, 0, "fuse", &sc->clk);
462 device_printf(dev, "Cannot get fuse clock: %d\n", rv);
465 rv = clk_enable(sc->clk);
467 device_printf(dev, "Cannot enable clock: %d\n", rv);
470 rv = hwreset_get_by_ofw_name(sc->dev, 0, "fuse", &sc->reset);
472 device_printf(dev, "Cannot get fuse reset\n");
475 rv = hwreset_deassert(sc->reset);
477 device_printf(sc->dev, "Cannot clear reset\n");
481 sc->soc->init(sc, &tegra_sku_info);
486 tegra_efuse_dump_sku();
487 return (bus_generic_attach(dev));
492 clk_release(sc->clk);
493 if (sc->reset != NULL)
494 hwreset_release(sc->reset);
495 if (sc->mem_res != NULL)
496 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
502 tegra_efuse_detach(device_t dev)
504 struct tegra_efuse_softc *sc;
506 sc = device_get_softc(dev);
509 clk_release(sc->clk);
510 if (sc->reset != NULL)
511 hwreset_release(sc->reset);
512 if (sc->mem_res != NULL)
513 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
515 return (bus_generic_detach(dev));
518 static device_method_t tegra_efuse_methods[] = {
519 /* Device interface */
520 DEVMETHOD(device_probe, tegra_efuse_probe),
521 DEVMETHOD(device_attach, tegra_efuse_attach),
522 DEVMETHOD(device_detach, tegra_efuse_detach),
527 static DEFINE_CLASS_0(efuse, tegra_efuse_driver, tegra_efuse_methods,
528 sizeof(struct tegra_efuse_softc));
529 EARLY_DRIVER_MODULE(tegra_efuse, simplebus, tegra_efuse_driver, NULL, NULL,