2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
33 #include "opt_platform.h"
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <sys/kernel.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
45 #include <machine/bus.h>
46 #include <machine/intr.h>
47 #include <machine/resource.h>
49 #include <dev/fdt/fdt_common.h>
50 #include <dev/gpio/gpiobusvar.h>
51 #include <dev/ofw/openfirm.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
57 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx)
58 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
59 #define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->mtx, \
60 device_get_nameunit(_sc->dev), "tegra_gpio", MTX_DEF)
61 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx);
62 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED);
63 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED);
65 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
66 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
68 #define GPIO_BANK_OFFS 0x100 /* Bank offset */
69 #define GPIO_NUM_BANKS 8 /* Total number per bank */
70 #define GPIO_REGS_IN_BANK 4 /* Total registers in bank */
71 #define GPIO_PINS_IN_REG 8 /* Total pin in register */
73 #define GPIO_BANKNUM(n) ((n) / (GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG))
74 #define GPIO_PORTNUM(n) (((n) / GPIO_PINS_IN_REG) % GPIO_REGS_IN_BANK)
75 #define GPIO_BIT(n) ((n) % GPIO_PINS_IN_REG)
77 #define GPIO_REGNUM(n) (GPIO_BANKNUM(n) * GPIO_BANK_OFFS + \
80 #define NGPIO ((GPIO_NUM_BANKS * GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG) - 8)
82 /* Register offsets */
87 #define GPIO_INT_STA 0x40
88 #define GPIO_INT_ENB 0x50
89 #define GPIO_INT_LVL 0x60
90 #define GPIO_INT_LVL_DELTA (1 << 16)
91 #define GPIO_INT_LVL_EDGE (1 << 8)
92 #define GPIO_INT_LVL_HIGH (1 << 0)
93 #define GPIO_INT_LVL_MASK (GPIO_INT_LVL_DELTA | \
94 GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH)
95 #define GPIO_INT_CLR 0x70
96 #define GPIO_MSK_CNF 0x80
97 #define GPIO_MSK_OE 0x90
98 #define GPIO_MSK_OUT 0xA0
99 #define GPIO_MSK_INT_STA 0xC0
100 #define GPIO_MSK_INT_ENB 0xD0
101 #define GPIO_MSK_INT_LVL 0xE0
103 char *tegra_gpio_port_names[] = {
104 "A", "B", "C", "D", /* Bank 0 */
105 "E", "F", "G", "H", /* Bank 1 */
106 "I", "J", "K", "L", /* Bank 2 */
107 "M", "N", "O", "P", /* Bank 3 */
108 "Q", "R", "S", "T", /* Bank 4 */
109 "U", "V", "W", "X", /* Bank 5 */
110 "Y", "Z", "AA", "BB", /* Bank 6 */
111 "CC", "DD", "EE" /* Bank 7 */
114 struct tegra_gpio_irqsrc {
115 struct intr_irqsrc isrc;
120 struct tegra_gpio_softc;
121 struct tegra_gpio_irq_cookie {
122 struct tegra_gpio_softc *sc;
126 struct tegra_gpio_softc {
130 struct resource *mem_res;
131 struct resource *irq_res[GPIO_NUM_BANKS];
132 void *irq_ih[GPIO_NUM_BANKS];
133 struct tegra_gpio_irq_cookie irq_cookies[GPIO_NUM_BANKS];
135 struct gpio_pin gpio_pins[NGPIO];
136 struct tegra_gpio_irqsrc *isrcs;
139 static struct ofw_compat_data compat_data[] = {
140 {"nvidia,tegra124-gpio", 1},
144 /* --------------------------------------------------------------------------
150 gpio_write_masked(struct tegra_gpio_softc *sc, bus_size_t reg,
151 struct gpio_pin *pin, uint32_t val)
156 bit = GPIO_BIT(pin->gp_pin);
157 tmp = 0x100 << bit; /* mask */
158 tmp |= (val & 1) << bit; /* value */
159 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp);
162 static inline uint32_t
163 gpio_read(struct tegra_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin)
168 bit = GPIO_BIT(pin->gp_pin);
169 val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin));
170 return (val >> bit) & 1;
174 tegra_gpio_pin_configure(struct tegra_gpio_softc *sc, struct gpio_pin *pin,
178 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0)
181 /* Manage input/output */
182 pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
183 if (flags & GPIO_PIN_OUTPUT) {
184 pin->gp_flags |= GPIO_PIN_OUTPUT;
185 gpio_write_masked(sc, GPIO_MSK_OE, pin, 1);
187 pin->gp_flags |= GPIO_PIN_INPUT;
188 gpio_write_masked(sc, GPIO_MSK_OE, pin, 0);
193 tegra_gpio_get_bus(device_t dev)
195 struct tegra_gpio_softc *sc;
197 sc = device_get_softc(dev);
202 tegra_gpio_pin_max(device_t dev, int *maxpin)
210 tegra_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
212 struct tegra_gpio_softc *sc;
214 sc = device_get_softc(dev);
215 if (pin >= sc->gpio_npins)
219 *caps = sc->gpio_pins[pin].gp_caps;
226 tegra_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
228 struct tegra_gpio_softc *sc;
231 sc = device_get_softc(dev);
232 if (pin >= sc->gpio_npins)
236 cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]);
241 *flags = sc->gpio_pins[pin].gp_flags;
248 tegra_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
250 struct tegra_gpio_softc *sc;
252 sc = device_get_softc(dev);
253 if (pin >= sc->gpio_npins)
257 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME);
264 tegra_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
266 struct tegra_gpio_softc *sc;
269 sc = device_get_softc(dev);
270 if (pin >= sc->gpio_npins)
274 cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]);
276 /* XXX - allow this for while ....
280 gpio_write_masked(sc, GPIO_MSK_CNF, &sc->gpio_pins[pin], 1);
282 tegra_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags);
289 tegra_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
291 struct tegra_gpio_softc *sc;
293 sc = device_get_softc(dev);
294 if (pin >= sc->gpio_npins)
297 gpio_write_masked(sc, GPIO_MSK_OUT, &sc->gpio_pins[pin], value);
304 tegra_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
306 struct tegra_gpio_softc *sc;
308 sc = device_get_softc(dev);
309 if (pin >= sc->gpio_npins)
313 *val = gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]);
320 tegra_gpio_pin_toggle(device_t dev, uint32_t pin)
322 struct tegra_gpio_softc *sc;
324 sc = device_get_softc(dev);
325 if (pin >= sc->gpio_npins)
329 gpio_write_masked(sc, GPIO_MSK_OE, &sc->gpio_pins[pin],
330 gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]) ^ 1);
336 /* --------------------------------------------------------------------------
342 intr_write_masked(struct tegra_gpio_softc *sc, bus_addr_t reg,
343 struct tegra_gpio_irqsrc *tgi, uint32_t val)
348 bit = GPIO_BIT(tgi->irq);
349 tmp = 0x100 << bit; /* mask */
350 tmp |= (val & 1) << bit; /* value */
351 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);
355 intr_write_modify(struct tegra_gpio_softc *sc, bus_addr_t reg,
356 struct tegra_gpio_irqsrc *tgi, uint32_t val, uint32_t mask)
361 bit = GPIO_BIT(tgi->irq);
363 tmp = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq));
364 tmp &= ~(mask << bit);
366 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);
371 tegra_gpio_isrc_mask(struct tegra_gpio_softc *sc,
372 struct tegra_gpio_irqsrc *tgi, uint32_t val)
375 intr_write_masked(sc, GPIO_MSK_INT_ENB, tgi, val);
379 tegra_gpio_isrc_eoi(struct tegra_gpio_softc *sc,
380 struct tegra_gpio_irqsrc *tgi)
383 intr_write_masked(sc, GPIO_INT_CLR, tgi, 1);
387 tegra_gpio_isrc_is_level(struct tegra_gpio_irqsrc *tgi)
390 return (tgi->cfgreg & GPIO_INT_LVL_EDGE);
394 tegra_gpio_intr(void *arg)
396 u_int irq, i, j, val, basepin;
397 struct tegra_gpio_softc *sc;
398 struct trapframe *tf;
399 struct tegra_gpio_irqsrc *tgi;
400 struct tegra_gpio_irq_cookie *cookie;
402 cookie = (struct tegra_gpio_irq_cookie *)arg;
404 tf = curthread->td_intr_frame;
406 for (i = 0; i < GPIO_REGS_IN_BANK; i++) {
407 basepin = cookie->bank_num * GPIO_REGS_IN_BANK *
408 GPIO_PINS_IN_REG + i * GPIO_PINS_IN_REG;
410 val = bus_read_4(sc->mem_res, GPIO_INT_STA +
411 GPIO_REGNUM(basepin));
412 val &= bus_read_4(sc->mem_res, GPIO_INT_ENB +
413 GPIO_REGNUM(basepin));
414 /* Interrupt handling */
415 for (j = 0; j < GPIO_PINS_IN_REG; j++) {
416 if ((val & (1 << j)) == 0)
419 tgi = &sc->isrcs[irq];
420 if (!tegra_gpio_isrc_is_level(tgi))
421 tegra_gpio_isrc_eoi(sc, tgi);
422 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) {
423 tegra_gpio_isrc_mask(sc, tgi, 0);
424 if (tegra_gpio_isrc_is_level(tgi))
425 tegra_gpio_isrc_eoi(sc, tgi);
426 device_printf(sc->dev,
427 "Stray irq %u disabled\n", irq);
433 return (FILTER_HANDLED);
437 tegra_gpio_pic_attach(struct tegra_gpio_softc *sc)
443 sc->isrcs = malloc(sizeof(*sc->isrcs) * sc->gpio_npins, M_DEVBUF,
446 name = device_get_nameunit(sc->dev);
447 for (irq = 0; irq < sc->gpio_npins; irq++) {
448 sc->isrcs[irq].irq = irq;
449 sc->isrcs[irq].cfgreg = 0;
450 error = intr_isrc_register(&sc->isrcs[irq].isrc,
451 sc->dev, 0, "%s,%u", name, irq);
453 return (error); /* XXX deregister ISRCs */
455 if (intr_pic_register(sc->dev,
456 OF_xref_from_node(ofw_bus_get_node(sc->dev))) == NULL)
463 tegra_gpio_pic_detach(struct tegra_gpio_softc *sc)
467 * There has not been established any procedure yet
468 * how to detach PIC from living system correctly.
470 device_printf(sc->dev, "%s: not implemented yet\n", __func__);
476 tegra_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
478 struct tegra_gpio_softc *sc;
479 struct tegra_gpio_irqsrc *tgi;
481 sc = device_get_softc(dev);
482 tgi = (struct tegra_gpio_irqsrc *)isrc;
483 tegra_gpio_isrc_mask(sc, tgi, 0);
487 tegra_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
489 struct tegra_gpio_softc *sc;
490 struct tegra_gpio_irqsrc *tgi;
492 sc = device_get_softc(dev);
493 tgi = (struct tegra_gpio_irqsrc *)isrc;
494 tegra_gpio_isrc_mask(sc, tgi, 1);
498 tegra_gpio_pic_map_fdt(struct tegra_gpio_softc *sc, u_int ncells,
499 pcell_t *cells, u_int *irqp, uint32_t *regp)
504 * The first cell is the interrupt number.
505 * The second cell is used to specify flags:
506 * bits[3:0] trigger type and level flags:
507 * 1 = low-to-high edge triggered.
508 * 2 = high-to-low edge triggered.
509 * 4 = active high level-sensitive.
510 * 8 = active low level-sensitive.
512 if (ncells != 2 || cells[0] >= sc->gpio_npins)
516 * All interrupt types could be set for an interrupt at one moment.
517 * At least, the combination of 'low-to-high' and 'high-to-low' edge
518 * triggered interrupt types can make a sense.
521 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH;
522 else if (cells[1] == 2)
523 reg = GPIO_INT_LVL_EDGE;
524 else if (cells[1] == 3)
525 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA;
526 else if (cells[1] == 4)
527 reg = GPIO_INT_LVL_HIGH;
528 else if (cells[1] == 8)
541 tegra_gpio_pic_map_gpio(struct tegra_gpio_softc *sc, u_int gpio_pin_num,
542 u_int gpio_pin_flags, u_int intr_mode, u_int *irqp, uint32_t *regp)
547 if (gpio_pin_num >= sc->gpio_npins)
550 case GPIO_INTR_CONFORM:
551 case GPIO_INTR_LEVEL_LOW:
554 case GPIO_INTR_LEVEL_HIGH:
555 reg = GPIO_INT_LVL_HIGH;
557 case GPIO_INTR_EDGE_RISING:
558 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH;
560 case GPIO_INTR_EDGE_FALLING:
561 reg = GPIO_INT_LVL_EDGE;
563 case GPIO_INTR_EDGE_BOTH:
564 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA;
569 *irqp = gpio_pin_num;
576 tegra_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
577 struct intr_irqsrc **isrcp)
581 struct tegra_gpio_softc *sc;
583 sc = device_get_softc(dev);
585 if (data->type == INTR_MAP_DATA_FDT) {
586 struct intr_map_data_fdt *daf;
588 daf = (struct intr_map_data_fdt *)data;
589 rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq,
591 } else if (data->type == INTR_MAP_DATA_GPIO) {
592 struct intr_map_data_gpio *dag;
594 dag = (struct intr_map_data_gpio *)data;
595 rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num,
596 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, NULL);
601 *isrcp = &sc->isrcs[irq].isrc;
606 tegra_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
608 struct tegra_gpio_softc *sc;
609 struct tegra_gpio_irqsrc *tgi;
611 sc = device_get_softc(dev);
612 tgi = (struct tegra_gpio_irqsrc *)isrc;
613 if (tegra_gpio_isrc_is_level(tgi))
614 tegra_gpio_isrc_eoi(sc, tgi);
618 tegra_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
620 struct tegra_gpio_softc *sc;
621 struct tegra_gpio_irqsrc *tgi;
623 sc = device_get_softc(dev);
624 tgi = (struct tegra_gpio_irqsrc *)isrc;
625 tegra_gpio_isrc_mask(sc, tgi, 1);
629 tegra_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
631 struct tegra_gpio_softc *sc;
632 struct tegra_gpio_irqsrc *tgi;
634 sc = device_get_softc(dev);
635 tgi = (struct tegra_gpio_irqsrc *)isrc;
637 tegra_gpio_isrc_mask(sc, tgi, 0);
638 if (tegra_gpio_isrc_is_level(tgi))
639 tegra_gpio_isrc_eoi(sc, tgi);
643 tegra_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
644 struct resource *res, struct intr_map_data *data)
649 struct tegra_gpio_softc *sc;
650 struct tegra_gpio_irqsrc *tgi;
652 sc = device_get_softc(dev);
653 tgi = (struct tegra_gpio_irqsrc *)isrc;
658 /* Get and check config for an interrupt. */
659 if (data->type == INTR_MAP_DATA_FDT) {
660 struct intr_map_data_fdt *daf;
662 daf = (struct intr_map_data_fdt *)data;
663 rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq,
665 } else if (data->type == INTR_MAP_DATA_GPIO) {
666 struct intr_map_data_gpio *dag;
668 dag = (struct intr_map_data_gpio *)data;
669 rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num,
670 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, &cfgreg);
677 * If this is a setup for another handler,
678 * only check that its configuration match.
680 if (isrc->isrc_handlers != 0)
681 return (tgi->cfgreg == cfgreg ? 0 : EINVAL);
683 tgi->cfgreg = cfgreg;
684 intr_write_modify(sc, GPIO_INT_LVL, tgi, cfgreg, GPIO_INT_LVL_MASK);
685 tegra_gpio_pic_enable_intr(dev, isrc);
691 tegra_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
692 struct resource *res, struct intr_map_data *data)
694 struct tegra_gpio_softc *sc;
695 struct tegra_gpio_irqsrc *tgi;
697 sc = device_get_softc(dev);
698 tgi = (struct tegra_gpio_irqsrc *)isrc;
700 if (isrc->isrc_handlers == 0)
701 tegra_gpio_isrc_mask(sc, tgi, 0);
706 tegra_gpio_probe(device_t dev)
709 if (!ofw_bus_status_okay(dev))
711 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
712 device_set_desc(dev, "Tegra GPIO Controller");
713 return (BUS_PROBE_DEFAULT);
719 /* --------------------------------------------------------------------------
725 tegra_gpio_detach(device_t dev)
727 struct tegra_gpio_softc *sc;
730 sc = device_get_softc(dev);
732 KASSERT(mtx_initialized(&sc->mtx), ("gpio mutex not initialized"));
734 for (i = 0; i < GPIO_NUM_BANKS; i++) {
735 if (sc->irq_ih[i] != NULL)
736 bus_teardown_intr(dev, sc->irq_res[i], sc->irq_ih[i]);
739 if (sc->isrcs != NULL)
740 tegra_gpio_pic_detach(sc);
742 gpiobus_detach_bus(dev);
744 for (i = 0; i < GPIO_NUM_BANKS; i++) {
745 if (sc->irq_res[i] != NULL)
746 bus_release_resource(dev, SYS_RES_IRQ, 0,
749 if (sc->mem_res != NULL)
750 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
751 GPIO_LOCK_DESTROY(sc);
757 tegra_gpio_attach(device_t dev)
759 struct tegra_gpio_softc *sc;
762 sc = device_get_softc(dev);
766 /* Allocate bus_space resources. */
768 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
770 if (sc->mem_res == NULL) {
771 device_printf(dev, "Cannot allocate memory resources\n");
772 tegra_gpio_detach(dev);
776 sc->gpio_npins = NGPIO;
777 for (i = 0; i < sc->gpio_npins; i++) {
778 sc->gpio_pins[i].gp_pin = i;
779 sc->gpio_pins[i].gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
780 GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH |
781 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING |
783 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, "gpio_%s.%d",
784 tegra_gpio_port_names[ i / GPIO_PINS_IN_REG],
785 i % GPIO_PINS_IN_REG);
786 sc->gpio_pins[i].gp_flags =
787 gpio_read(sc, GPIO_OE, &sc->gpio_pins[i]) != 0 ?
788 GPIO_PIN_OUTPUT : GPIO_PIN_INPUT;
791 /* Init interrupt related registes. */
792 for (i = 0; i < sc->gpio_npins; i += GPIO_PINS_IN_REG) {
793 bus_write_4(sc->mem_res, GPIO_INT_ENB + GPIO_REGNUM(i), 0);
794 bus_write_4(sc->mem_res, GPIO_INT_STA + GPIO_REGNUM(i), 0xFF);
795 bus_write_4(sc->mem_res, GPIO_INT_CLR + GPIO_REGNUM(i), 0xFF);
798 /* Allocate interrupts. */
799 for (i = 0; i < GPIO_NUM_BANKS; i++) {
800 sc->irq_cookies[i].sc = sc;
801 sc->irq_cookies[i].bank_num = i;
803 sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ,
805 if (sc->irq_res[i] == NULL) {
806 device_printf(dev, "Cannot allocate IRQ resources\n");
807 tegra_gpio_detach(dev);
810 if ((bus_setup_intr(dev, sc->irq_res[i],
811 INTR_TYPE_MISC | INTR_MPSAFE, tegra_gpio_intr, NULL,
812 &sc->irq_cookies[i], &sc->irq_ih[i]))) {
814 "WARNING: unable to register interrupt handler\n");
815 tegra_gpio_detach(dev);
820 if (tegra_gpio_pic_attach(sc) != 0) {
821 device_printf(dev, "WARNING: unable to attach PIC\n");
822 tegra_gpio_detach(dev);
826 sc->busdev = gpiobus_attach_bus(dev);
827 if (sc->busdev == NULL) {
828 tegra_gpio_detach(dev);
832 return (bus_generic_attach(dev));
836 tegra_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent,
837 int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags)
848 tegra_gpio_get_node(device_t bus, device_t dev)
851 /* We only have one child, the GPIO bus, which needs our own node. */
852 return (ofw_bus_get_node(bus));
855 static device_method_t tegra_gpio_methods[] = {
856 DEVMETHOD(device_probe, tegra_gpio_probe),
857 DEVMETHOD(device_attach, tegra_gpio_attach),
858 DEVMETHOD(device_detach, tegra_gpio_detach),
860 /* Interrupt controller interface */
861 DEVMETHOD(pic_disable_intr, tegra_gpio_pic_disable_intr),
862 DEVMETHOD(pic_enable_intr, tegra_gpio_pic_enable_intr),
863 DEVMETHOD(pic_map_intr, tegra_gpio_pic_map_intr),
864 DEVMETHOD(pic_setup_intr, tegra_gpio_pic_setup_intr),
865 DEVMETHOD(pic_teardown_intr, tegra_gpio_pic_teardown_intr),
866 DEVMETHOD(pic_post_filter, tegra_gpio_pic_post_filter),
867 DEVMETHOD(pic_post_ithread, tegra_gpio_pic_post_ithread),
868 DEVMETHOD(pic_pre_ithread, tegra_gpio_pic_pre_ithread),
871 DEVMETHOD(gpio_get_bus, tegra_gpio_get_bus),
872 DEVMETHOD(gpio_pin_max, tegra_gpio_pin_max),
873 DEVMETHOD(gpio_pin_getname, tegra_gpio_pin_getname),
874 DEVMETHOD(gpio_pin_getflags, tegra_gpio_pin_getflags),
875 DEVMETHOD(gpio_pin_getcaps, tegra_gpio_pin_getcaps),
876 DEVMETHOD(gpio_pin_setflags, tegra_gpio_pin_setflags),
877 DEVMETHOD(gpio_pin_get, tegra_gpio_pin_get),
878 DEVMETHOD(gpio_pin_set, tegra_gpio_pin_set),
879 DEVMETHOD(gpio_pin_toggle, tegra_gpio_pin_toggle),
880 DEVMETHOD(gpio_map_gpios, tegra_map_gpios),
882 /* ofw_bus interface */
883 DEVMETHOD(ofw_bus_get_node, tegra_gpio_get_node),
888 static driver_t tegra_gpio_driver = {
891 sizeof(struct tegra_gpio_softc),
893 static devclass_t tegra_gpio_devclass;
895 EARLY_DRIVER_MODULE(tegra_gpio, simplebus, tegra_gpio_driver,
896 tegra_gpio_devclass, 0, 0, 70);
898 extern devclass_t ofwgpiobus_devclass;
899 extern driver_t ofw_gpiobus_driver;
900 EARLY_DRIVER_MODULE(ofw_gpiobus, tegra_gpio, ofw_gpiobus_driver,
901 ofwgpiobus_devclass, 0, 0, BUS_PASS_BUS);
902 extern devclass_t gpioc_devclass;
903 extern driver_t gpioc_driver;
904 DRIVER_MODULE(gpioc, tegra_gpio, gpioc_driver, gpioc_devclass, 0, 0);