2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * I2C driver for Tegra SoCs.
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/limits.h>
38 #include <sys/module.h>
39 #include <sys/resource.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
46 #include <sys/mutex.h>
48 #include <dev/extres/clk/clk.h>
49 #include <dev/extres/hwreset/hwreset.h>
50 #include <dev/iicbus/iiconf.h>
51 #include <dev/iicbus/iicbus.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
55 #include "iicbus_if.h"
57 #define I2C_CNFG 0x000
58 #define I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT (1 << 15)
59 #define I2C_CNFG_DEBOUNCE_CNT(x) (((x) & 0x07) << 12)
60 #define I2C_CNFG_NEW_MASTER_FSM (1 << 11)
61 #define I2C_CNFG_PACKET_MODE_EN (1 << 10)
62 #define I2C_CNFG_SEND (1 << 9)
63 #define I2C_CNFG_NOACK (1 << 8)
64 #define I2C_CNFG_CMD2 (1 << 7)
65 #define I2C_CNFG_CMD1 (1 << 6)
66 #define I2C_CNFG_START (1 << 5)
67 #define I2C_CNFG_SLV2 (1 << 4)
68 #define I2C_CNFG_LENGTH_SHIFT 1
69 #define I2C_CNFG_LENGTH_MASK 0x7
70 #define I2C_CNFG_A_MOD (1 << 0)
72 #define I2C_CMD_ADDR0 0x004
73 #define I2C_CMD_ADDR1 0x008
74 #define I2C_CMD_DATA1 0x00c
75 #define I2C_CMD_DATA2 0x010
76 #define I2C_STATUS 0x01c
77 #define I2C_SL_CNFG 0x020
78 #define I2C_SL_RCVD 0x024
79 #define I2C_SL_STATUS 0x028
80 #define I2C_SL_ADDR1 0x02c
81 #define I2C_SL_ADDR2 0x030
82 #define I2C_TLOW_SEXT 0x034
83 #define I2C_SL_DELAY_COUNT 0x03c
84 #define I2C_SL_INT_MASK 0x040
85 #define I2C_SL_INT_SOURCE 0x044
86 #define I2C_SL_INT_SET 0x048
87 #define I2C_TX_PACKET_FIFO 0x050
88 #define I2C_RX_FIFO 0x054
89 #define I2C_PACKET_TRANSFER_STATUS 0x058
90 #define I2C_FIFO_CONTROL 0x05c
91 #define I2C_FIFO_CONTROL_SLV_TX_FIFO_TRIG(x) (((x) & 0x07) << 13)
92 #define I2C_FIFO_CONTROL_SLV_RX_FIFO_TRIG(x) (((x) & 0x07) << 10)
93 #define I2C_FIFO_CONTROL_SLV_TX_FIFO_FLUSH (1 << 9)
94 #define I2C_FIFO_CONTROL_SLV_RX_FIFO_FLUSH (1 << 8)
95 #define I2C_FIFO_CONTROL_TX_FIFO_TRIG(x) (((x) & 0x07) << 5)
96 #define I2C_FIFO_CONTROL_RX_FIFO_TRIG(x) (((x) & 0x07) << 2)
97 #define I2C_FIFO_CONTROL_TX_FIFO_FLUSH (1 << 1)
98 #define I2C_FIFO_CONTROL_RX_FIFO_FLUSH (1 << 0)
100 #define I2C_FIFO_STATUS 0x060
101 #define I2C_FIFO_STATUS_SLV_XFER_ERR_REASON (1 << 25)
102 #define I2C_FIFO_STATUS_TX_FIFO_SLV_EMPTY_CNT(x) (((x) >> 20) & 0xF)
103 #define I2C_FIFO_STATUS_RX_FIFO_SLV_FULL_CNT(x) (((x) >> 16) & 0xF)
104 #define I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT(x) (((x) >> 4) & 0xF)
105 #define I2C_FIFO_STATUS_RX_FIFO_FULL_CNT(x) (((x) >> 0) & 0xF)
107 #define I2C_INTERRUPT_MASK_REGISTER 0x064
108 #define I2C_INTERRUPT_STATUS_REGISTER 0x068
109 #define I2C_INT_SLV_ACK_WITHHELD (1 << 28)
110 #define I2C_INT_SLV_RD2WR (1 << 27)
111 #define I2C_INT_SLV_WR2RD (1 << 26)
112 #define I2C_INT_SLV_PKT_XFER_ERR (1 << 25)
113 #define I2C_INT_SLV_TX_BUFFER_REQ (1 << 24)
114 #define I2C_INT_SLV_RX_BUFFER_FILLED (1 << 23)
115 #define I2C_INT_SLV_PACKET_XFER_COMPLETE (1 << 22)
116 #define I2C_INT_SLV_TFIFO_OVF (1 << 21)
117 #define I2C_INT_SLV_RFIFO_UNF (1 << 20)
118 #define I2C_INT_SLV_TFIFO_DATA_REQ (1 << 17)
119 #define I2C_INT_SLV_RFIFO_DATA_REQ (1 << 16)
120 #define I2C_INT_BUS_CLEAR_DONE (1 << 11)
121 #define I2C_INT_TLOW_MEXT_TIMEOUT (1 << 10)
122 #define I2C_INT_TLOW_SEXT_TIMEOUT (1 << 9)
123 #define I2C_INT_TIMEOUT (1 << 8)
124 #define I2C_INT_PACKET_XFER_COMPLETE (1 << 7)
125 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1 << 6)
126 #define I2C_INT_TFIFO_OVR (1 << 5)
127 #define I2C_INT_RFIFO_UNF (1 << 4)
128 #define I2C_INT_NOACK (1 << 3)
129 #define I2C_INT_ARB_LOST (1 << 2)
130 #define I2C_INT_TFIFO_DATA_REQ (1 << 1)
131 #define I2C_INT_RFIFO_DATA_REQ (1 << 0)
132 #define I2C_ERROR_MASK (I2C_INT_ARB_LOST | I2C_INT_NOACK | \
133 I2C_INT_RFIFO_UNF | I2C_INT_TFIFO_OVR)
135 #define I2C_CLK_DIVISOR 0x06c
136 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16
137 #define I2C_CLK_DIVISOR_STD_FAST_MODE_MASK 0xffff
138 #define I2C_CLK_DIVISOR_HSMODE_SHIFT 0
139 #define I2C_CLK_DIVISOR_HSMODE_MASK 0xffff
140 #define I2C_INTERRUPT_SOURCE_REGISTER 0x070
141 #define I2C_INTERRUPT_SET_REGISTER 0x074
142 #define I2C_SLV_TX_PACKET_FIFO 0x07c
143 #define I2C_SLV_PACKET_STATUS 0x080
144 #define I2C_BUS_CLEAR_CONFIG 0x084
145 #define I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD(x) (((x) & 0xFF) << 16)
146 #define I2C_BUS_CLEAR_CONFIG_BC_STOP_COND (1 << 2)
147 #define I2C_BUS_CLEAR_CONFIG_BC_TERMINATE (1 << 1)
148 #define I2C_BUS_CLEAR_CONFIG_BC_ENABLE (1 << 0)
150 #define I2C_BUS_CLEAR_STATUS 0x088
151 #define I2C_BUS_CLEAR_STATUS_BC_STATUS (1 << 0)
153 #define I2C_CONFIG_LOAD 0x08c
154 #define I2C_CONFIG_LOAD_TIMEOUT_CONFIG_LOAD (1 << 2)
155 #define I2C_CONFIG_LOAD_SLV_CONFIG_LOAD (1 << 1)
156 #define I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD (1 << 0)
158 #define I2C_INTERFACE_TIMING_0 0x094
159 #define I2C_INTERFACE_TIMING_1 0x098
160 #define I2C_HS_INTERFACE_TIMING_0 0x09c
161 #define I2C_HS_INTERFACE_TIMING_1 0x0a0
163 /* Protocol header 0 */
164 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
165 #define PACKET_HEADER0_HEADER_SIZE_MASK 0x3
166 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
167 #define PACKET_HEADER0_PACKET_ID_MASK 0xff
168 #define PACKET_HEADER0_CONT_ID_SHIFT 12
169 #define PACKET_HEADER0_CONT_ID_MASK 0xf
170 #define PACKET_HEADER0_PROTOCOL_I2C (1 << 4)
171 #define PACKET_HEADER0_TYPE_SHIFT 0
172 #define PACKET_HEADER0_TYPE_MASK 0x7
175 #define I2C_HEADER_HIGHSPEED_MODE (1 << 22)
176 #define I2C_HEADER_CONT_ON_NAK (1 << 21)
177 #define I2C_HEADER_SEND_START_BYTE (1 << 20)
178 #define I2C_HEADER_READ (1 << 19)
179 #define I2C_HEADER_10BIT_ADDR (1 << 18)
180 #define I2C_HEADER_IE_ENABLE (1 << 17)
181 #define I2C_HEADER_REPEAT_START (1 << 16)
182 #define I2C_HEADER_CONTINUE_XFER (1 << 15)
183 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
184 #define I2C_HEADER_MASTER_ADDR_MASK 0x7
185 #define I2C_HEADER_SLAVE_ADDR_SHIFT 0
186 #define I2C_HEADER_SLAVE_ADDR_MASK 0x3ff
188 #define I2C_CLK_DIVISOR_STD_FAST_MODE 0x19
189 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8
191 #define I2C_REQUEST_TIMEOUT (5 * hz)
193 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
194 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
196 #define LOCK(_sc) mtx_lock(&(_sc)->mtx)
197 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
198 #define SLEEP(_sc, timeout) \
199 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", timeout);
200 #define LOCK_INIT(_sc) \
201 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_i2c", MTX_DEF)
202 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx)
203 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED)
204 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED)
206 static struct ofw_compat_data compat_data[] = {
207 {"nvidia,tegra124-i2c", 1},
210 enum tegra_i2c_xfer_type {
211 XFER_STOP, /* Send stop condition after xfer */
212 XFER_REPEAT_START, /* Send repeated start after xfer */
213 XFER_CONTINUE /* Don't send nothing */
216 struct tegra_i2c_softc {
220 struct resource *mem_res;
221 struct resource *irq_res;
238 tegra_i2c_flush_fifo(struct tegra_i2c_softc *sc)
243 reg = RD4(sc, I2C_FIFO_CONTROL);
244 reg |= I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH;
245 WR4(sc, I2C_FIFO_CONTROL, reg);
248 while (timeout > 0) {
249 reg = RD4(sc, I2C_FIFO_CONTROL);
250 reg &= I2C_FIFO_CONTROL_TX_FIFO_FLUSH |
251 I2C_FIFO_CONTROL_RX_FIFO_FLUSH;
257 device_printf(sc->dev, "FIFO flush timedout\n");
264 tegra_i2c_setup_clk(struct tegra_i2c_softc *sc, int clk_freq)
268 div = ((sc->core_freq / clk_freq) / 10) - 1;
269 if ((sc->core_freq / (10 * (div + 1))) > clk_freq)
273 WR4(sc, I2C_CLK_DIVISOR,
274 (1 << I2C_CLK_DIVISOR_HSMODE_SHIFT) |
275 (div << I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT));
279 tegra_i2c_bus_clear(struct tegra_i2c_softc *sc)
282 uint32_t reg, status;
284 WR4(sc, I2C_BUS_CLEAR_CONFIG,
285 I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD(18) |
286 I2C_BUS_CLEAR_CONFIG_BC_STOP_COND |
287 I2C_BUS_CLEAR_CONFIG_BC_TERMINATE);
289 WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD);
290 for (timeout = 1000; timeout > 0; timeout--) {
291 if (RD4(sc, I2C_CONFIG_LOAD) == 0)
296 device_printf(sc->dev, "config load timeouted\n");
297 reg = RD4(sc, I2C_BUS_CLEAR_CONFIG);
298 reg |= I2C_BUS_CLEAR_CONFIG_BC_ENABLE;
299 WR4(sc, I2C_BUS_CLEAR_CONFIG,reg);
301 for (timeout = 1000; timeout > 0; timeout--) {
302 if ((RD4(sc, I2C_BUS_CLEAR_CONFIG) &
303 I2C_BUS_CLEAR_CONFIG_BC_ENABLE) == 0)
308 device_printf(sc->dev, "bus clear timeouted\n");
310 status = RD4(sc, I2C_BUS_CLEAR_STATUS);
311 if ((status & I2C_BUS_CLEAR_STATUS_BC_STATUS) == 0)
312 device_printf(sc->dev, "bus clear failed\n");
316 tegra_i2c_hw_init(struct tegra_i2c_softc *sc)
320 /* Reset the core. */
321 rv = hwreset_assert(sc->reset);
323 device_printf(sc->dev, "Cannot assert reset\n");
327 rv = hwreset_deassert(sc->reset);
329 device_printf(sc->dev, "Cannot clear reset\n");
333 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
334 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF);
335 WR4(sc, I2C_CNFG, I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
336 I2C_CNFG_DEBOUNCE_CNT(2));
338 tegra_i2c_setup_clk(sc, sc->bus_freq);
340 WR4(sc, I2C_FIFO_CONTROL, I2C_FIFO_CONTROL_TX_FIFO_TRIG(7) |
341 I2C_FIFO_CONTROL_RX_FIFO_TRIG(0));
343 WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD);
344 for (timeout = 1000; timeout > 0; timeout--) {
345 if (RD4(sc, I2C_CONFIG_LOAD) == 0)
350 device_printf(sc->dev, "config load timeouted\n");
352 tegra_i2c_bus_clear(sc);
357 tegra_i2c_tx(struct tegra_i2c_softc *sc)
362 if (sc->msg_idx >= sc->msg->len)
363 panic("Invalid call to tegra_i2c_tx\n");
365 while(sc->msg_idx < sc->msg->len) {
366 reg = RD4(sc, I2C_FIFO_STATUS);
367 if (I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT(reg) == 0)
369 cnt = min(4, sc->msg->len - sc->msg_idx);
371 for (i = 0; i < cnt; i++) {
372 reg |= sc->msg->buf[sc->msg_idx] << (i * 8);
375 WR4(sc, I2C_TX_PACKET_FIFO, reg);
377 if (sc->msg_idx >= sc->msg->len)
379 return (sc->msg->len - sc->msg_idx - 1);
383 tegra_i2c_rx(struct tegra_i2c_softc *sc)
388 if (sc->msg_idx >= sc->msg->len)
389 panic("Invalid call to tegra_i2c_rx\n");
391 while(sc->msg_idx < sc->msg->len) {
392 reg = RD4(sc, I2C_FIFO_STATUS);
393 if (I2C_FIFO_STATUS_RX_FIFO_FULL_CNT(reg) == 0)
395 cnt = min(4, sc->msg->len - sc->msg_idx);
396 reg = RD4(sc, I2C_RX_FIFO);
397 for (i = 0; i < cnt; i++) {
398 sc->msg->buf[sc->msg_idx] = (reg >> (i * 8)) & 0xFF;
403 if (sc->msg_idx >= sc->msg->len)
405 return (sc->msg->len - sc->msg_idx - 1);
409 tegra_i2c_intr(void *arg)
411 struct tegra_i2c_softc *sc;
412 uint32_t status, reg;
415 sc = (struct tegra_i2c_softc *)arg;
418 status = RD4(sc, I2C_INTERRUPT_SOURCE_REGISTER);
419 if (sc->msg == NULL) {
420 /* Unexpected interrupt - disable FIFOs, clear reset. */
421 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);
422 reg &= ~I2C_INT_TFIFO_DATA_REQ;
423 reg &= ~I2C_INT_RFIFO_DATA_REQ;
424 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
425 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, status);
430 if ((status & I2C_ERROR_MASK) != 0) {
431 if (status & I2C_INT_NOACK)
432 sc->bus_err = IIC_ENOACK;
433 if (status & I2C_INT_ARB_LOST)
434 sc->bus_err = IIC_EBUSERR;
435 if ((status & I2C_INT_TFIFO_OVR) ||
436 (status & I2C_INT_RFIFO_UNF))
437 sc->bus_err = IIC_EBUSERR;
439 } else if ((status & I2C_INT_RFIFO_DATA_REQ) &&
440 (sc->msg != NULL) && (sc->msg->flags & IIC_M_RD)) {
441 rv = tegra_i2c_rx(sc);
443 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);
444 reg &= ~I2C_INT_RFIFO_DATA_REQ;
445 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);
447 } else if ((status & I2C_INT_TFIFO_DATA_REQ) &&
448 (sc->msg != NULL) && !(sc->msg->flags & IIC_M_RD)) {
449 rv = tegra_i2c_tx(sc);
451 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);
452 reg &= ~I2C_INT_TFIFO_DATA_REQ;
453 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);
455 } else if ((status & I2C_INT_RFIFO_DATA_REQ) ||
456 (status & I2C_INT_TFIFO_DATA_REQ)) {
457 device_printf(sc->dev, "Unexpected data interrupt: 0x%08X\n",
459 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);
460 reg &= ~I2C_INT_TFIFO_DATA_REQ;
461 reg &= ~I2C_INT_RFIFO_DATA_REQ;
462 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);
464 if (status & I2C_INT_PACKET_XFER_COMPLETE)
466 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, status);
468 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
475 tegra_i2c_start_msg(struct tegra_i2c_softc *sc, struct iic_msg *msg,
476 enum tegra_i2c_xfer_type xtype)
481 tmp = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
482 PACKET_HEADER0_PROTOCOL_I2C |
483 (1 << PACKET_HEADER0_CONT_ID_SHIFT) |
484 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
485 WR4(sc, I2C_TX_PACKET_FIFO, tmp);
489 WR4(sc, I2C_TX_PACKET_FIFO, msg->len - 1);
492 tmp = I2C_HEADER_IE_ENABLE;
493 if (xtype == XFER_CONTINUE)
494 tmp |= I2C_HEADER_CONTINUE_XFER;
495 else if (xtype == XFER_REPEAT_START)
496 tmp |= I2C_HEADER_REPEAT_START;
497 tmp |= msg->slave << I2C_HEADER_SLAVE_ADDR_SHIFT;
498 if (msg->flags & IIC_M_RD) {
499 tmp |= I2C_HEADER_READ;
500 tmp |= 1 << I2C_HEADER_SLAVE_ADDR_SHIFT;
502 tmp &= ~(1 << I2C_HEADER_SLAVE_ADDR_SHIFT);
504 WR4(sc, I2C_TX_PACKET_FIFO, tmp);
506 /* Interrupt mask. */
507 mask = I2C_INT_NOACK | I2C_INT_ARB_LOST | I2C_INT_PACKET_XFER_COMPLETE;
508 if (msg->flags & IIC_M_RD)
509 mask |= I2C_INT_RFIFO_DATA_REQ;
511 mask |= I2C_INT_TFIFO_DATA_REQ;
512 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, mask);
516 tegra_i2c_poll(struct tegra_i2c_softc *sc)
520 for(timeout = 10000; timeout > 0; timeout--) {
534 tegra_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
537 struct tegra_i2c_softc *sc;
538 enum tegra_i2c_xfer_type xtype;
540 sc = device_get_softc(dev);
544 while (sc->bus_inuse == 1)
549 for (i = 0; i < nmsgs; i++) {
554 /* Check for valid parameters. */
555 if (sc->msg == NULL || sc->msg->buf == NULL ||
561 /* Get flags for next transfer. */
562 if (i == (nmsgs - 1)) {
563 if (msgs[i].flags & IIC_M_NOSTOP)
564 xtype = XFER_CONTINUE;
568 if (msgs[i + 1].flags & IIC_M_NOSTART)
569 xtype = XFER_CONTINUE;
571 xtype = XFER_REPEAT_START;
573 tegra_i2c_start_msg(sc, sc->msg, xtype);
575 rv = tegra_i2c_poll(sc);
577 rv = msleep(&sc->done, &sc->mtx, PZERO, "iic",
578 I2C_REQUEST_TIMEOUT);
580 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
581 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF);
589 tegra_i2c_hw_init(sc);
590 tegra_i2c_flush_fifo(sc);
598 /* Wake up the processes that are waiting for the bus. */
607 tegra_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
609 struct tegra_i2c_softc *sc;
612 sc = device_get_softc(dev);
613 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
614 sc = device_get_softc(dev);
616 tegra_i2c_setup_clk(sc, busfreq);
622 tegra_i2c_probe(device_t dev)
624 if (!ofw_bus_status_okay(dev))
627 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
630 return (BUS_PROBE_DEFAULT);
634 tegra_i2c_attach(device_t dev)
638 struct tegra_i2c_softc *sc;
641 sc = device_get_softc(dev);
643 node = ofw_bus_get_node(dev);
647 /* Get the memory resource for the register mapping. */
649 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
651 if (sc->mem_res == NULL) {
652 device_printf(dev, "Cannot map registers.\n");
657 /* Allocate our IRQ resource. */
659 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
661 if (sc->irq_res == NULL) {
662 device_printf(dev, "Cannot allocate interrupt.\n");
668 rv = clk_get_by_ofw_name(dev, 0, "div-clk", &sc->clk);
670 device_printf(dev, "Cannot get i2c clock: %d\n", rv);
673 rv = hwreset_get_by_ofw_name(sc->dev, 0, "i2c", &sc->reset);
675 device_printf(sc->dev, "Cannot get i2c reset\n");
678 rv = OF_getencprop(node, "clock-frequency", &sc->bus_freq,
679 sizeof(sc->bus_freq));
680 if (rv != sizeof(sc->bus_freq)) {
681 sc->bus_freq = 100000;
685 /* Request maximum frequency for I2C block 136MHz (408MHz / 3). */
686 rv = clk_set_freq(sc->clk, 136000000, CLK_SET_ROUND_DOWN);
688 device_printf(dev, "Cannot set clock frequency\n");
691 rv = clk_get_freq(sc->clk, &freq);
693 device_printf(dev, "Cannot get clock frequency\n");
696 sc->core_freq = (uint32_t)freq;
698 rv = clk_enable(sc->clk);
700 device_printf(dev, "Cannot enable clock: %d\n", rv);
705 rv = tegra_i2c_hw_init(sc);
707 device_printf(dev, "tegra_i2c_activate failed\n");
711 /* Setup interrupt. */
712 rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
713 NULL, tegra_i2c_intr, sc, &sc->irq_h);
715 device_printf(dev, "Cannot setup interrupt.\n");
719 /* Attach the iicbus. */
720 sc->iicbus = device_add_child(dev, "iicbus", -1);
721 if (sc->iicbus == NULL) {
722 device_printf(dev, "Could not allocate iicbus instance.\n");
727 /* Probe and attach the iicbus. */
728 return (bus_generic_attach(dev));
731 if (sc->irq_h != NULL)
732 bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
733 if (sc->irq_res != NULL)
734 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
735 if (sc->mem_res != NULL)
736 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
743 tegra_i2c_detach(device_t dev)
745 struct tegra_i2c_softc *sc;
748 sc = device_get_softc(dev);
749 tegra_i2c_hw_init(sc);
750 if (sc->irq_h != NULL)
751 bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
752 if (sc->irq_res != NULL)
753 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
754 if (sc->mem_res != NULL)
755 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
759 rv = device_delete_child(dev, sc->iicbus);
760 return (bus_generic_detach(dev));
764 tegra_i2c_get_node(device_t bus, device_t dev)
767 /* Share controller node with iibus device. */
768 return (ofw_bus_get_node(bus));
771 static device_method_t tegra_i2c_methods[] = {
772 /* Device interface */
773 DEVMETHOD(device_probe, tegra_i2c_probe),
774 DEVMETHOD(device_attach, tegra_i2c_attach),
775 DEVMETHOD(device_detach, tegra_i2c_detach),
778 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
779 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
780 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
781 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
782 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
783 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
784 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
785 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
786 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
789 DEVMETHOD(ofw_bus_get_node, tegra_i2c_get_node),
791 /* iicbus interface */
792 DEVMETHOD(iicbus_callback, iicbus_null_callback),
793 DEVMETHOD(iicbus_reset, tegra_i2c_iicbus_reset),
794 DEVMETHOD(iicbus_transfer, tegra_i2c_transfer),
799 static devclass_t tegra_i2c_devclass;
800 static DEFINE_CLASS_0(iichb, tegra_i2c_driver, tegra_i2c_methods,
801 sizeof(struct tegra_i2c_softc));
802 EARLY_DRIVER_MODULE(tegra_iic, simplebus, tegra_i2c_driver, tegra_i2c_devclass,