sys/arm/nvidia/tegra_i2c.c

   1 /*-
   2  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 /*
  31  * I2C driver for Tegra SoCs.
  32  */
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/bus.h>
  36 #include <sys/kernel.h>
  37 #include <sys/limits.h>
  38 #include <sys/module.h>
  39 #include <sys/resource.h>
  40
  41 #include <machine/bus.h>
  42 #include <machine/resource.h>
  43 #include <sys/rman.h>
  44
  45 #include <sys/lock.h>
  46 #include <sys/mutex.h>
  47
  48 #include <dev/extres/clk/clk.h>
  49 #include <dev/extres/hwreset/hwreset.h>
  50 #include <dev/iicbus/iiconf.h>
  51 #include <dev/iicbus/iicbus.h>
  52 #include <dev/ofw/ofw_bus.h>
  53 #include <dev/ofw/ofw_bus_subr.h>
  54
  55 #include "iicbus_if.h"
  56
  57 #define I2C_CNFG                                0x000
  58 #define  I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT               (1 << 15)
  59 #define  I2C_CNFG_DEBOUNCE_CNT(x)                       (((x) & 0x07) << 12)
  60 #define  I2C_CNFG_NEW_MASTER_FSM                        (1 << 11)
  61 #define  I2C_CNFG_PACKET_MODE_EN                        (1 << 10)
  62 #define  I2C_CNFG_SEND                                  (1 <<  9)
  63 #define  I2C_CNFG_NOACK                                 (1 <<  8)
  64 #define  I2C_CNFG_CMD2                                  (1 <<  7)
  65 #define  I2C_CNFG_CMD1                                  (1 <<  6)
  66 #define  I2C_CNFG_START                                 (1 <<  5)
  67 #define  I2C_CNFG_SLV2                                  (1 <<  4)
  68 #define  I2C_CNFG_LENGTH_SHIFT                          1
  69 #define  I2C_CNFG_LENGTH_MASK                           0x7
  70 #define  I2C_CNFG_A_MOD                                 (1 <<  0)
  71
  72 #define I2C_CMD_ADDR0                           0x004
  73 #define I2C_CMD_ADDR1                           0x008
  74 #define I2C_CMD_DATA1                           0x00c
  75 #define I2C_CMD_DATA2                           0x010
  76 #define I2C_STATUS                              0x01c
  77 #define I2C_SL_CNFG                             0x020
  78 #define I2C_SL_RCVD                             0x024
  79 #define I2C_SL_STATUS                           0x028
  80 #define I2C_SL_ADDR1                            0x02c
  81 #define I2C_SL_ADDR2                            0x030
  82 #define I2C_TLOW_SEXT                           0x034
  83 #define I2C_SL_DELAY_COUNT                      0x03c
  84 #define I2C_SL_INT_MASK                         0x040
  85 #define I2C_SL_INT_SOURCE                       0x044
  86 #define I2C_SL_INT_SET                          0x048
  87 #define I2C_TX_PACKET_FIFO                      0x050
  88 #define I2C_RX_FIFO                             0x054
  89 #define I2C_PACKET_TRANSFER_STATUS              0x058
  90 #define I2C_FIFO_CONTROL                        0x05c
  91 #define  I2C_FIFO_CONTROL_SLV_TX_FIFO_TRIG(x)           (((x) & 0x07) << 13)
  92 #define  I2C_FIFO_CONTROL_SLV_RX_FIFO_TRIG(x)           (((x) & 0x07) << 10)
  93 #define  I2C_FIFO_CONTROL_SLV_TX_FIFO_FLUSH             (1 <<  9)
  94 #define  I2C_FIFO_CONTROL_SLV_RX_FIFO_FLUSH             (1 <<  8)
  95 #define  I2C_FIFO_CONTROL_TX_FIFO_TRIG(x)               (((x) & 0x07) << 5)
  96 #define  I2C_FIFO_CONTROL_RX_FIFO_TRIG(x)               (((x) & 0x07) << 2)
  97 #define  I2C_FIFO_CONTROL_TX_FIFO_FLUSH                 (1 << 1)
  98 #define  I2C_FIFO_CONTROL_RX_FIFO_FLUSH                 (1 << 0)
  99
 100 #define I2C_FIFO_STATUS                         0x060
 101 #define  I2C_FIFO_STATUS_SLV_XFER_ERR_REASON            (1 << 25)
 102 #define  I2C_FIFO_STATUS_TX_FIFO_SLV_EMPTY_CNT(x)       (((x) >> 20) & 0xF)
 103 #define  I2C_FIFO_STATUS_RX_FIFO_SLV_FULL_CNT(x)        (((x) >> 16) & 0xF)
 104 #define  I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT(x)           (((x) >>  4) & 0xF)
 105 #define  I2C_FIFO_STATUS_RX_FIFO_FULL_CNT(x)            (((x) >>  0) & 0xF)
 106
 107 #define I2C_INTERRUPT_MASK_REGISTER             0x064
 108 #define I2C_INTERRUPT_STATUS_REGISTER           0x068
 109 #define  I2C_INT_SLV_ACK_WITHHELD                       (1 << 28)
 110 #define  I2C_INT_SLV_RD2WR                              (1 << 27)
 111 #define  I2C_INT_SLV_WR2RD                              (1 << 26)
 112 #define  I2C_INT_SLV_PKT_XFER_ERR                       (1 << 25)
 113 #define  I2C_INT_SLV_TX_BUFFER_REQ                      (1 << 24)
 114 #define  I2C_INT_SLV_RX_BUFFER_FILLED                   (1 << 23)
 115 #define  I2C_INT_SLV_PACKET_XFER_COMPLETE               (1 << 22)
 116 #define  I2C_INT_SLV_TFIFO_OVF                          (1 << 21)
 117 #define  I2C_INT_SLV_RFIFO_UNF                          (1 << 20)
 118 #define  I2C_INT_SLV_TFIFO_DATA_REQ                     (1 << 17)
 119 #define  I2C_INT_SLV_RFIFO_DATA_REQ                     (1 << 16)
 120 #define  I2C_INT_BUS_CLEAR_DONE                         (1 << 11)
 121 #define  I2C_INT_TLOW_MEXT_TIMEOUT                      (1 << 10)
 122 #define  I2C_INT_TLOW_SEXT_TIMEOUT                      (1 <<  9)
 123 #define  I2C_INT_TIMEOUT                                (1 <<  8)
 124 #define  I2C_INT_PACKET_XFER_COMPLETE                   (1 <<  7)
 125 #define  I2C_INT_ALL_PACKETS_XFER_COMPLETE              (1 <<  6)
 126 #define  I2C_INT_TFIFO_OVR                              (1 <<  5)
 127 #define  I2C_INT_RFIFO_UNF                              (1 <<  4)
 128 #define  I2C_INT_NOACK                                  (1 <<  3)
 129 #define  I2C_INT_ARB_LOST                               (1 <<  2)
 130 #define  I2C_INT_TFIFO_DATA_REQ                         (1 <<  1)
 131 #define  I2C_INT_RFIFO_DATA_REQ                         (1 <<  0)
 132 #define  I2C_ERROR_MASK         (I2C_INT_ARB_LOST | I2C_INT_NOACK |      \
 133                                 I2C_INT_RFIFO_UNF | I2C_INT_TFIFO_OVR)
 134
 135 #define I2C_CLK_DIVISOR                         0x06c
 136 #define  I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT            16
 137 #define  I2C_CLK_DIVISOR_STD_FAST_MODE_MASK             0xffff
 138 #define  I2C_CLK_DIVISOR_HSMODE_SHIFT                   0
 139 #define  I2C_CLK_DIVISOR_HSMODE_MASK                    0xffff
 140 #define I2C_INTERRUPT_SOURCE_REGISTER           0x070
 141 #define I2C_INTERRUPT_SET_REGISTER              0x074
 142 #define I2C_SLV_TX_PACKET_FIFO                  0x07c
 143 #define I2C_SLV_PACKET_STATUS                   0x080
 144 #define I2C_BUS_CLEAR_CONFIG                    0x084
 145 #define  I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD(x)      (((x) & 0xFF) << 16)
 146 #define  I2C_BUS_CLEAR_CONFIG_BC_STOP_COND              (1 << 2)
 147 #define  I2C_BUS_CLEAR_CONFIG_BC_TERMINATE              (1 << 1)
 148 #define  I2C_BUS_CLEAR_CONFIG_BC_ENABLE                 (1 << 0)
 149
 150 #define I2C_BUS_CLEAR_STATUS                    0x088
 151 #define  I2C_BUS_CLEAR_STATUS_BC_STATUS                 (1 << 0)
 152
 153 #define I2C_CONFIG_LOAD                         0x08c
 154 #define  I2C_CONFIG_LOAD_TIMEOUT_CONFIG_LOAD            (1 << 2)
 155 #define  I2C_CONFIG_LOAD_SLV_CONFIG_LOAD                (1 << 1)
 156 #define  I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD               (1 << 0)
 157
 158 #define I2C_INTERFACE_TIMING_0                  0x094
 159 #define I2C_INTERFACE_TIMING_1                  0x098
 160 #define I2C_HS_INTERFACE_TIMING_0               0x09c
 161 #define I2C_HS_INTERFACE_TIMING_1               0x0a0
 162
 163 /* Protocol header 0 */
 164 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
 165 #define PACKET_HEADER0_HEADER_SIZE_MASK         0x3
 166 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
 167 #define PACKET_HEADER0_PACKET_ID_MASK           0xff
 168 #define PACKET_HEADER0_CONT_ID_SHIFT            12
 169 #define PACKET_HEADER0_CONT_ID_MASK             0xf
 170 #define PACKET_HEADER0_PROTOCOL_I2C             (1 << 4)
 171 #define PACKET_HEADER0_TYPE_SHIFT               0
 172 #define PACKET_HEADER0_TYPE_MASK                0x7
 173
 174 /* I2C header */
 175 #define I2C_HEADER_HIGHSPEED_MODE               (1 << 22)
 176 #define I2C_HEADER_CONT_ON_NAK                  (1 << 21)
 177 #define I2C_HEADER_SEND_START_BYTE              (1 << 20)
 178 #define I2C_HEADER_READ                         (1 << 19)
 179 #define I2C_HEADER_10BIT_ADDR                   (1 << 18)
 180 #define I2C_HEADER_IE_ENABLE                    (1 << 17)
 181 #define I2C_HEADER_REPEAT_START                 (1 << 16)
 182 #define I2C_HEADER_CONTINUE_XFER                (1 << 15)
 183 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 184 #define I2C_HEADER_MASTER_ADDR_MASK             0x7
 185 #define I2C_HEADER_SLAVE_ADDR_SHIFT             0
 186 #define I2C_HEADER_SLAVE_ADDR_MASK              0x3ff
 187
 188 #define I2C_CLK_DIVISOR_STD_FAST_MODE           0x19
 189 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
 190
 191 #define I2C_REQUEST_TIMEOUT                     (5 * hz)
 192
 193 #define WR4(_sc, _r, _v)        bus_write_4((_sc)->mem_res, (_r), (_v))
 194 #define RD4(_sc, _r)            bus_read_4((_sc)->mem_res, (_r))
 195
 196 #define LOCK(_sc)               mtx_lock(&(_sc)->mtx)
 197 #define UNLOCK(_sc)             mtx_unlock(&(_sc)->mtx)
 198 #define SLEEP(_sc, timeout)                                             \
 199         mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", timeout);
 200 #define LOCK_INIT(_sc)                                                  \
 201         mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_i2c", MTX_DEF)
 202 #define LOCK_DESTROY(_sc)       mtx_destroy(&_sc->mtx)
 203 #define ASSERT_LOCKED(_sc)      mtx_assert(&_sc->mtx, MA_OWNED)
 204 #define ASSERT_UNLOCKED(_sc)    mtx_assert(&_sc->mtx, MA_NOTOWNED)
 205
 206 static struct ofw_compat_data compat_data[] = {
 207         {"nvidia,tegra124-i2c", 1},
 208         {"nvidia,tegra210-i2c", 1},
 209         {NULL,                  0}
 210 };
 211 enum tegra_i2c_xfer_type {
 212         XFER_STOP,              /* Send stop condition after xfer */
 213         XFER_REPEAT_START,      /* Send repeated start after xfer */
 214         XFER_CONTINUE           /* Don't send nothing */
 215 } ;
 216
 217 struct tegra_i2c_softc {
 218         device_t                dev;
 219         struct mtx              mtx;
 220
 221         struct resource         *mem_res;
 222         struct resource         *irq_res;
 223         void                    *irq_h;
 224
 225         device_t                iicbus;
 226         clk_t                   clk;
 227         hwreset_t               reset;
 228         uint32_t                core_freq;
 229         uint32_t                bus_freq;
 230         int                     bus_inuse;
 231
 232         struct iic_msg          *msg;
 233         int                     msg_idx;
 234         uint32_t                bus_err;
 235         int                     done;
 236 };
 237
 238 static int
 239 tegra_i2c_flush_fifo(struct tegra_i2c_softc *sc)
 240 {
 241         int timeout;
 242         uint32_t reg;
 243
 244         reg = RD4(sc, I2C_FIFO_CONTROL);
 245         reg |= I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH;
 246         WR4(sc, I2C_FIFO_CONTROL, reg);
 247
 248         timeout = 10;
 249         while (timeout > 0) {
 250                 reg = RD4(sc, I2C_FIFO_CONTROL);
 251                 reg &= I2C_FIFO_CONTROL_TX_FIFO_FLUSH |
 252                     I2C_FIFO_CONTROL_RX_FIFO_FLUSH;
 253                 if (reg == 0)
 254                         break;
 255                 DELAY(10);
 256         }
 257         if (timeout <= 0) {
 258                 device_printf(sc->dev, "FIFO flush timedout\n");
 259                 return (ETIMEDOUT);
 260         }
 261         return (0);
 262 }
 263
 264 static void
 265 tegra_i2c_setup_clk(struct tegra_i2c_softc *sc, int clk_freq)
 266 {
 267         int div;
 268
 269         div = ((sc->core_freq  / clk_freq)  / 10) - 1;
 270         if ((sc->core_freq / (10 * (div + 1)))  > clk_freq)
 271                 div++;
 272         if (div > 65535)
 273                 div = 65535;
 274         WR4(sc, I2C_CLK_DIVISOR,
 275             (1 << I2C_CLK_DIVISOR_HSMODE_SHIFT) |
 276             (div << I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT));
 277 }
 278
 279 static void
 280 tegra_i2c_bus_clear(struct tegra_i2c_softc *sc)
 281 {
 282         int timeout;
 283         uint32_t reg, status;
 284
 285         WR4(sc, I2C_BUS_CLEAR_CONFIG,
 286             I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD(18) |
 287             I2C_BUS_CLEAR_CONFIG_BC_STOP_COND |
 288             I2C_BUS_CLEAR_CONFIG_BC_TERMINATE);
 289
 290         WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD);
 291         for (timeout = 1000; timeout > 0; timeout--) {
 292                 if (RD4(sc, I2C_CONFIG_LOAD) == 0)
 293                         break;
 294                 DELAY(10);
 295         }
 296         if (timeout <= 0)
 297                 device_printf(sc->dev, "config load timeouted\n");
 298         reg = RD4(sc, I2C_BUS_CLEAR_CONFIG);
 299         reg |= I2C_BUS_CLEAR_CONFIG_BC_ENABLE;
 300         WR4(sc, I2C_BUS_CLEAR_CONFIG,reg);
 301
 302         for (timeout = 1000; timeout > 0; timeout--) {
 303                 if ((RD4(sc, I2C_BUS_CLEAR_CONFIG) &
 304                     I2C_BUS_CLEAR_CONFIG_BC_ENABLE) == 0)
 305                         break;
 306                 DELAY(10);
 307         }
 308         if (timeout <= 0)
 309                 device_printf(sc->dev, "bus clear timeouted\n");
 310
 311         status = RD4(sc, I2C_BUS_CLEAR_STATUS);
 312         if ((status & I2C_BUS_CLEAR_STATUS_BC_STATUS) == 0)
 313                 device_printf(sc->dev, "bus clear failed\n");
 314 }
 315
 316 static int
 317 tegra_i2c_hw_init(struct tegra_i2c_softc *sc)
 318 {
 319         int rv, timeout;
 320
 321         /* Reset the core. */
 322         rv = hwreset_assert(sc->reset);
 323         if (rv != 0) {
 324                 device_printf(sc->dev, "Cannot assert reset\n");
 325                 return (rv);
 326         }
 327         DELAY(10);
 328         rv = hwreset_deassert(sc->reset);
 329         if (rv != 0) {
 330                 device_printf(sc->dev, "Cannot clear reset\n");
 331                 return (rv);
 332         }
 333
 334         WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
 335         WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF);
 336         WR4(sc, I2C_CNFG, I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 337             I2C_CNFG_DEBOUNCE_CNT(2));
 338
 339         tegra_i2c_setup_clk(sc, sc->bus_freq);
 340
 341         WR4(sc, I2C_FIFO_CONTROL, I2C_FIFO_CONTROL_TX_FIFO_TRIG(7) |
 342             I2C_FIFO_CONTROL_RX_FIFO_TRIG(0));
 343
 344         WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD);
 345         for (timeout = 1000; timeout > 0; timeout--) {
 346                 if (RD4(sc, I2C_CONFIG_LOAD) == 0)
 347                         break;
 348                 DELAY(10);
 349         }
 350         if (timeout <= 0)
 351                 device_printf(sc->dev, "config load timeouted\n");
 352
 353         tegra_i2c_bus_clear(sc);
 354         return (0);
 355 }
 356
 357 static int
 358 tegra_i2c_tx(struct tegra_i2c_softc *sc)
 359 {
 360         uint32_t reg;
 361         int cnt, i;
 362
 363         if (sc->msg_idx >= sc->msg->len)
 364                 panic("Invalid call to tegra_i2c_tx\n");
 365
 366         while(sc->msg_idx < sc->msg->len) {
 367                 reg = RD4(sc, I2C_FIFO_STATUS);
 368                 if (I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT(reg) == 0)
 369                         break;
 370                 cnt = min(4, sc->msg->len - sc->msg_idx);
 371                 reg = 0;
 372                 for (i = 0;  i < cnt; i++) {
 373                         reg |=  sc->msg->buf[sc->msg_idx] << (i * 8);
 374                         sc->msg_idx++;
 375                 }
 376                 WR4(sc, I2C_TX_PACKET_FIFO, reg);
 377         }
 378         if (sc->msg_idx >= sc->msg->len)
 379                 return (0);
 380         return (sc->msg->len - sc->msg_idx - 1);
 381 }
 382
 383 static int
 384 tegra_i2c_rx(struct tegra_i2c_softc *sc)
 385 {
 386         uint32_t reg;
 387         int cnt, i;
 388
 389         if (sc->msg_idx >= sc->msg->len)
 390                 panic("Invalid call to tegra_i2c_rx\n");
 391
 392         while(sc->msg_idx < sc->msg->len) {
 393                 reg = RD4(sc, I2C_FIFO_STATUS);
 394                 if (I2C_FIFO_STATUS_RX_FIFO_FULL_CNT(reg) == 0)
 395                         break;
 396                 cnt = min(4, sc->msg->len - sc->msg_idx);
 397                 reg = RD4(sc, I2C_RX_FIFO);
 398                 for (i = 0;  i < cnt; i++) {
 399                         sc->msg->buf[sc->msg_idx] = (reg >> (i * 8)) & 0xFF;
 400                         sc->msg_idx++;
 401                 }
 402         }
 403
 404         if (sc->msg_idx >= sc->msg->len)
 405                 return (0);
 406         return (sc->msg->len - sc->msg_idx - 1);
 407 }
 408
 409 static void
 410 tegra_i2c_intr(void *arg)
 411 {
 412         struct tegra_i2c_softc *sc;
 413         uint32_t status, reg;
 414         int rv;
 415
 416         sc = (struct tegra_i2c_softc *)arg;
 417
 418         LOCK(sc);
 419         status = RD4(sc, I2C_INTERRUPT_SOURCE_REGISTER);
 420         if (sc->msg == NULL) {
 421                 /* Unexpected interrupt - disable FIFOs, clear reset. */
 422                 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);
 423                 reg &= ~I2C_INT_TFIFO_DATA_REQ;
 424                 reg &= ~I2C_INT_RFIFO_DATA_REQ;
 425                 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
 426                 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, status);
 427                 UNLOCK(sc);
 428                 return;
 429         }
 430
 431         if ((status & I2C_ERROR_MASK) != 0) {
 432                 if (status & I2C_INT_NOACK)
 433                         sc->bus_err = IIC_ENOACK;
 434                 if (status & I2C_INT_ARB_LOST)
 435                         sc->bus_err = IIC_EBUSERR;
 436                 if ((status & I2C_INT_TFIFO_OVR) ||
 437                     (status & I2C_INT_RFIFO_UNF))
 438                         sc->bus_err = IIC_EBUSERR;
 439                 sc->done = 1;
 440         } else if ((status & I2C_INT_RFIFO_DATA_REQ) &&
 441             (sc->msg != NULL) && (sc->msg->flags & IIC_M_RD)) {
 442                 rv = tegra_i2c_rx(sc);
 443                 if (rv == 0) {
 444                         reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);
 445                         reg &= ~I2C_INT_RFIFO_DATA_REQ;
 446                         WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);
 447                 }
 448         } else if ((status & I2C_INT_TFIFO_DATA_REQ) &&
 449             (sc->msg != NULL) && !(sc->msg->flags & IIC_M_RD)) {
 450                 rv = tegra_i2c_tx(sc);
 451                 if (rv == 0) {
 452                         reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);
 453                         reg &= ~I2C_INT_TFIFO_DATA_REQ;
 454                         WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);
 455                 }
 456         } else if ((status & I2C_INT_RFIFO_DATA_REQ) ||
 457                     (status & I2C_INT_TFIFO_DATA_REQ)) {
 458                 device_printf(sc->dev, "Unexpected data interrupt: 0x%08X\n",
 459                     status);
 460                 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);
 461                 reg &= ~I2C_INT_TFIFO_DATA_REQ;
 462                 reg &= ~I2C_INT_RFIFO_DATA_REQ;
 463                 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);
 464         }
 465         if (status & I2C_INT_PACKET_XFER_COMPLETE)
 466                 sc->done = 1;
 467         WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, status);
 468         if (sc->done) {
 469                 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
 470                 wakeup(&(sc->done));
 471         }
 472         UNLOCK(sc);
 473 }
 474
 475 static void
 476 tegra_i2c_start_msg(struct tegra_i2c_softc *sc, struct iic_msg *msg,
 477     enum tegra_i2c_xfer_type xtype)
 478 {
 479         uint32_t tmp, mask;
 480
 481         /* Packet header. */
 482         tmp =  (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 483            PACKET_HEADER0_PROTOCOL_I2C |
 484            (1 << PACKET_HEADER0_CONT_ID_SHIFT) |
 485            (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 486         WR4(sc, I2C_TX_PACKET_FIFO, tmp);
 487
 488         /* Packet size. */
 489         WR4(sc, I2C_TX_PACKET_FIFO, msg->len - 1);
 490
 491         /* I2C header. */
 492         tmp = I2C_HEADER_IE_ENABLE;
 493         if (xtype == XFER_CONTINUE)
 494                 tmp |= I2C_HEADER_CONTINUE_XFER;
 495         else if (xtype == XFER_REPEAT_START)
 496                 tmp |= I2C_HEADER_REPEAT_START;
 497         tmp |= msg->slave << I2C_HEADER_SLAVE_ADDR_SHIFT;
 498         if (msg->flags & IIC_M_RD) {
 499                 tmp |= I2C_HEADER_READ;
 500                 tmp |= 1 << I2C_HEADER_SLAVE_ADDR_SHIFT;
 501         } else
 502                 tmp &= ~(1 << I2C_HEADER_SLAVE_ADDR_SHIFT);
 503
 504         WR4(sc, I2C_TX_PACKET_FIFO, tmp);
 505
 506         /* Interrupt mask. */
 507         mask = I2C_INT_NOACK | I2C_INT_ARB_LOST | I2C_INT_PACKET_XFER_COMPLETE;
 508         if (msg->flags & IIC_M_RD)
 509                 mask |= I2C_INT_RFIFO_DATA_REQ;
 510         else
 511                 mask |= I2C_INT_TFIFO_DATA_REQ;
 512         WR4(sc, I2C_INTERRUPT_MASK_REGISTER, mask);
 513 }
 514
 515 static int
 516 tegra_i2c_poll(struct tegra_i2c_softc *sc)
 517 {
 518         int timeout;
 519
 520         for(timeout = 10000; timeout > 0; timeout--)  {
 521                 UNLOCK(sc);
 522                 tegra_i2c_intr(sc);
 523                 LOCK(sc);
 524                 if (sc->done != 0)
 525                          break;
 526                 DELAY(1);
 527         }
 528         if (timeout <= 0)
 529                 return (ETIMEDOUT);
 530         return (0);
 531 }
 532
 533 static int
 534 tegra_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
 535 {
 536         int rv, i;
 537         struct tegra_i2c_softc *sc;
 538         enum tegra_i2c_xfer_type xtype;
 539
 540         sc = device_get_softc(dev);
 541         LOCK(sc);
 542
 543         /* Get the bus. */
 544         while (sc->bus_inuse == 1)
 545                 SLEEP(sc,  0);
 546         sc->bus_inuse = 1;
 547
 548         rv = 0;
 549         for (i = 0; i < nmsgs; i++) {
 550                 sc->msg = &msgs[i];
 551                 sc->msg_idx = 0;
 552                 sc->bus_err = 0;
 553                 sc->done = 0;
 554                 /* Check for valid parameters. */
 555                 if (sc->msg == NULL || sc->msg->buf == NULL ||
 556                     sc->msg->len == 0) {
 557                         rv = EINVAL;
 558                         break;
 559                 }
 560
 561                 /* Get flags for next transfer. */
 562                 if (i == (nmsgs - 1)) {
 563                         if (msgs[i].flags & IIC_M_NOSTOP)
 564                                 xtype = XFER_CONTINUE;
 565                         else
 566                                 xtype = XFER_STOP;
 567                 } else {
 568                         if (msgs[i + 1].flags & IIC_M_NOSTART)
 569                                 xtype = XFER_CONTINUE;
 570                         else
 571                                 xtype = XFER_REPEAT_START;
 572                 }
 573                 tegra_i2c_start_msg(sc, sc->msg, xtype);
 574                 if (cold)
 575                         rv = tegra_i2c_poll(sc);
 576                 else
 577                         rv = msleep(&sc->done, &sc->mtx, PZERO, "iic",
 578                             I2C_REQUEST_TIMEOUT);
 579
 580                 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
 581                 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF);
 582                 if (rv == 0)
 583                         rv = sc->bus_err;
 584                 if (rv != 0)
 585                         break;
 586         }
 587
 588         if (rv != 0) {
 589                 tegra_i2c_hw_init(sc);
 590                 tegra_i2c_flush_fifo(sc);
 591         }
 592
 593         sc->msg = NULL;
 594         sc->msg_idx = 0;
 595         sc->bus_err = 0;
 596         sc->done = 0;
 597
 598         /* Wake up the processes that are waiting for the bus. */
 599         sc->bus_inuse = 0;
 600         wakeup(sc);
 601         UNLOCK(sc);
 602
 603         return (rv);
 604 }
 605
 606 static int
 607 tegra_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
 608 {
 609         struct tegra_i2c_softc *sc;
 610         int busfreq;
 611
 612         sc = device_get_softc(dev);
 613         busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
 614         sc = device_get_softc(dev);
 615         LOCK(sc);
 616         tegra_i2c_setup_clk(sc, busfreq);
 617         UNLOCK(sc);
 618         return (0);
 619 }
 620
 621 static int
 622 tegra_i2c_probe(device_t dev)
 623 {
 624         if (!ofw_bus_status_okay(dev))
 625                 return (ENXIO);
 626
 627         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
 628                 return (ENXIO);
 629
 630         return (BUS_PROBE_DEFAULT);
 631 }
 632
 633 static int
 634 tegra_i2c_attach(device_t dev)
 635 {
 636         int rv, rid;
 637         phandle_t node;
 638         struct tegra_i2c_softc *sc;
 639         uint64_t freq;
 640
 641         sc = device_get_softc(dev);
 642         sc->dev = dev;
 643         node = ofw_bus_get_node(dev);
 644
 645         LOCK_INIT(sc);
 646
 647         /* Get the memory resource for the register mapping. */
 648         rid = 0;
 649         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 650             RF_ACTIVE);
 651         if (sc->mem_res == NULL) {
 652                 device_printf(dev, "Cannot map registers.\n");
 653                 rv = ENXIO;
 654                 goto fail;
 655         }
 656
 657         /* Allocate our IRQ resource. */
 658         rid = 0;
 659         sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 660             RF_ACTIVE);
 661         if (sc->irq_res == NULL) {
 662                 device_printf(dev, "Cannot allocate interrupt.\n");
 663                 rv = ENXIO;
 664                 goto fail;
 665         }
 666
 667         /* FDT resources. */
 668         rv = clk_get_by_ofw_name(dev, 0, "div-clk", &sc->clk);
 669         if (rv != 0) {
 670                 device_printf(dev, "Cannot get i2c clock: %d\n", rv);
 671                 goto fail;
 672         }
 673         rv = hwreset_get_by_ofw_name(sc->dev, 0, "i2c", &sc->reset);
 674         if (rv != 0) {
 675                 device_printf(sc->dev, "Cannot get i2c reset\n");
 676                 return (ENXIO);
 677         }
 678         rv = OF_getencprop(node, "clock-frequency", &sc->bus_freq,
 679             sizeof(sc->bus_freq));
 680         if (rv != sizeof(sc->bus_freq)) {
 681                 sc->bus_freq = 100000;
 682         }
 683
 684         /* Request maximum frequency for I2C block 136MHz (408MHz / 3). */
 685         rv = clk_set_freq(sc->clk, 136000000, CLK_SET_ROUND_DOWN);
 686         if (rv != 0) {
 687                 device_printf(dev, "Cannot set clock frequency\n");
 688                 goto fail;
 689         }
 690         rv = clk_get_freq(sc->clk, &freq);
 691         if (rv != 0) {
 692                 device_printf(dev, "Cannot get clock frequency\n");
 693                 goto fail;
 694         }
 695         sc->core_freq = (uint32_t)freq;
 696
 697         rv = clk_enable(sc->clk);
 698         if (rv != 0) {
 699                 device_printf(dev, "Cannot enable clock: %d\n", rv);
 700                 goto fail;
 701         }
 702
 703         /* Init hardware. */
 704         rv = tegra_i2c_hw_init(sc);
 705         if (rv) {
 706                 device_printf(dev, "tegra_i2c_activate failed\n");
 707                 goto fail;
 708         }
 709
 710         /* Setup interrupt. */
 711         rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
 712             NULL, tegra_i2c_intr, sc, &sc->irq_h);
 713         if (rv) {
 714                 device_printf(dev, "Cannot setup interrupt.\n");
 715                 goto fail;
 716         }
 717
 718         /* Attach the iicbus. */
 719         sc->iicbus = device_add_child(dev, "iicbus", -1);
 720         if (sc->iicbus == NULL) {
 721                 device_printf(dev, "Could not allocate iicbus instance.\n");
 722                 rv = ENXIO;
 723                 goto fail;
 724         }
 725
 726         /* Probe and attach the iicbus. */
 727         return (bus_generic_attach(dev));
 728
 729 fail:
 730         if (sc->irq_h != NULL)
 731                 bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
 732         if (sc->irq_res != NULL)
 733                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
 734         if (sc->mem_res != NULL)
 735                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
 736         LOCK_DESTROY(sc);
 737
 738         return (rv);
 739 }
 740
 741 static int
 742 tegra_i2c_detach(device_t dev)
 743 {
 744         struct tegra_i2c_softc *sc;
 745
 746         sc = device_get_softc(dev);
 747         tegra_i2c_hw_init(sc);
 748         if (sc->irq_h != NULL)
 749                 bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
 750         if (sc->irq_res != NULL)
 751                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
 752         if (sc->mem_res != NULL)
 753                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
 754
 755         LOCK_DESTROY(sc);
 756         if (sc->iicbus)
 757                 device_delete_child(dev, sc->iicbus);
 758         return (bus_generic_detach(dev));
 759 }
 760
 761 static phandle_t
 762 tegra_i2c_get_node(device_t bus, device_t dev)
 763 {
 764
 765         /* Share controller node with iibus device. */
 766         return (ofw_bus_get_node(bus));
 767 }
 768
 769 static device_method_t tegra_i2c_methods[] = {
 770         /* Device interface */
 771         DEVMETHOD(device_probe,         tegra_i2c_probe),
 772         DEVMETHOD(device_attach,        tegra_i2c_attach),
 773         DEVMETHOD(device_detach,        tegra_i2c_detach),
 774
 775         /* Bus interface */
 776         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
 777         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
 778         DEVMETHOD(bus_alloc_resource,   bus_generic_alloc_resource),
 779         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
 780         DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
 781         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
 782         DEVMETHOD(bus_adjust_resource,  bus_generic_adjust_resource),
 783         DEVMETHOD(bus_set_resource,     bus_generic_rl_set_resource),
 784         DEVMETHOD(bus_get_resource,     bus_generic_rl_get_resource),
 785
 786         /* OFW methods */
 787         DEVMETHOD(ofw_bus_get_node,     tegra_i2c_get_node),
 788
 789         /* iicbus interface */
 790         DEVMETHOD(iicbus_callback,      iicbus_null_callback),
 791         DEVMETHOD(iicbus_reset,         tegra_i2c_iicbus_reset),
 792         DEVMETHOD(iicbus_transfer,      tegra_i2c_transfer),
 793
 794         DEVMETHOD_END
 795 };
 796
 797 static DEFINE_CLASS_0(iichb, tegra_i2c_driver, tegra_i2c_methods,
 798     sizeof(struct tegra_i2c_softc));
 799 EARLY_DRIVER_MODULE(tegra_iic, simplebus, tegra_i2c_driver, NULL, NULL, 73);