2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * Local interrupt controller driver for Tegra SoCs.
33 #include <sys/param.h>
34 #include <sys/module.h>
35 #include <sys/systm.h>
38 #include <sys/kernel.h>
41 #include <machine/fdt.h>
42 #include <machine/intr.h>
43 #include <machine/resource.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
50 #define LIC_VIRQ_CPU 0x00
51 #define LIC_VIRQ_COP 0x04
52 #define LIC_VFRQ_CPU 0x08
53 #define LIC_VFRQ_COP 0x0c
56 #define LIC_FIR_SET 0x18
57 #define LIC_FIR_CLR 0x1c
58 #define LIC_CPU_IER 0x20
59 #define LIC_CPU_IER_SET 0x24
60 #define LIC_CPU_IER_CLR 0x28
61 #define LIC_CPU_IEP_CLASS 0x2C
62 #define LIC_COP_IER 0x30
63 #define LIC_COP_IER_SET 0x34
64 #define LIC_COP_IER_CLR 0x38
65 #define LIC_COP_IEP_CLASS 0x3c
67 #define WR4(_sc, _b, _r, _v) bus_write_4((_sc)->mem_res[_b], (_r), (_v))
68 #define RD4(_sc, _b, _r) bus_read_4((_sc)->mem_res[_b], (_r))
70 static struct resource_spec lic_spec[] = {
71 { SYS_RES_MEMORY, 0, RF_ACTIVE },
72 { SYS_RES_MEMORY, 1, RF_ACTIVE },
73 { SYS_RES_MEMORY, 2, RF_ACTIVE },
74 { SYS_RES_MEMORY, 3, RF_ACTIVE },
75 { SYS_RES_MEMORY, 4, RF_ACTIVE },
79 static struct ofw_compat_data compat_data[] = {
80 {"nvidia,tegra124-ictlr", 1},
86 struct resource *mem_res[nitems(lic_spec)];
91 tegra_lic_activate_intr(device_t dev, struct intr_irqsrc *isrc,
92 struct resource *res, struct intr_map_data *data)
94 struct tegra_lic_sc *sc = device_get_softc(dev);
96 return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data));
100 tegra_lic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
102 struct tegra_lic_sc *sc = device_get_softc(dev);
104 PIC_DISABLE_INTR(sc->parent, isrc);
108 tegra_lic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
110 struct tegra_lic_sc *sc = device_get_softc(dev);
112 PIC_ENABLE_INTR(sc->parent, isrc);
116 tegra_lic_map_intr(device_t dev, struct intr_map_data *data,
117 struct intr_irqsrc **isrcp)
119 struct tegra_lic_sc *sc = device_get_softc(dev);
121 return (PIC_MAP_INTR(sc->parent, data, isrcp));
125 tegra_lic_deactivate_intr(device_t dev, struct intr_irqsrc *isrc,
126 struct resource *res, struct intr_map_data *data)
128 struct tegra_lic_sc *sc = device_get_softc(dev);
130 return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data));
134 tegra_lic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
135 struct resource *res, struct intr_map_data *data)
137 struct tegra_lic_sc *sc = device_get_softc(dev);
139 return (PIC_SETUP_INTR(sc->parent, isrc, res, data));
143 tegra_lic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
144 struct resource *res, struct intr_map_data *data)
146 struct tegra_lic_sc *sc = device_get_softc(dev);
148 return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data));
152 tegra_lic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
154 struct tegra_lic_sc *sc = device_get_softc(dev);
156 PIC_PRE_ITHREAD(sc->parent, isrc);
160 tegra_lic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
162 struct tegra_lic_sc *sc = device_get_softc(dev);
164 PIC_POST_ITHREAD(sc->parent, isrc);
168 tegra_lic_post_filter(device_t dev, struct intr_irqsrc *isrc)
170 struct tegra_lic_sc *sc = device_get_softc(dev);
172 PIC_POST_FILTER(sc->parent, isrc);
177 tegra_lic_bind_intr(device_t dev, struct intr_irqsrc *isrc)
179 struct tegra_lic_sc *sc = device_get_softc(dev);
181 return (PIC_BIND_INTR(sc->parent, isrc));
186 tegra_lic_probe(device_t dev)
188 if (!ofw_bus_status_okay(dev))
191 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
194 return (BUS_PROBE_DEFAULT);
198 tegra_lic_attach(device_t dev)
200 struct tegra_lic_sc *sc;
202 phandle_t parent_xref;
205 sc = device_get_softc(dev);
207 node = ofw_bus_get_node(dev);
209 rv = OF_getencprop(node, "interrupt-parent", &parent_xref,
210 sizeof(parent_xref));
212 device_printf(dev, "Cannot read parent node property\n");
215 sc->parent = OF_device_from_xref(parent_xref);
216 if (sc->parent == NULL) {
217 device_printf(dev, "Cannott find parent controller\n");
221 if (bus_alloc_resources(dev, lic_spec, sc->mem_res)) {
222 device_printf(dev, "Cannott allocate resources\n");
226 /* Disable all interrupts, route all to irq */
227 for (i = 0; i < nitems(lic_spec); i++) {
228 if (sc->mem_res[i] == NULL)
230 WR4(sc, i, LIC_CPU_IER_CLR, 0xFFFFFFFF);
231 WR4(sc, i, LIC_CPU_IEP_CLASS, 0);
234 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) {
235 device_printf(dev, "Cannot register PIC\n");
241 bus_release_resources(dev, lic_spec, sc->mem_res);
246 tegra_lic_detach(device_t dev)
248 struct tegra_lic_sc *sc;
251 sc = device_get_softc(dev);
252 for (i = 0; i < nitems(lic_spec); i++) {
253 if (sc->mem_res[i] == NULL)
255 bus_release_resource(dev, SYS_RES_MEMORY, i,
261 static device_method_t tegra_lic_methods[] = {
262 DEVMETHOD(device_probe, tegra_lic_probe),
263 DEVMETHOD(device_attach, tegra_lic_attach),
264 DEVMETHOD(device_detach, tegra_lic_detach),
266 /* Interrupt controller interface */
267 DEVMETHOD(pic_activate_intr, tegra_lic_activate_intr),
268 DEVMETHOD(pic_disable_intr, tegra_lic_disable_intr),
269 DEVMETHOD(pic_enable_intr, tegra_lic_enable_intr),
270 DEVMETHOD(pic_map_intr, tegra_lic_map_intr),
271 DEVMETHOD(pic_deactivate_intr, tegra_lic_deactivate_intr),
272 DEVMETHOD(pic_setup_intr, tegra_lic_setup_intr),
273 DEVMETHOD(pic_teardown_intr, tegra_lic_teardown_intr),
274 DEVMETHOD(pic_pre_ithread, tegra_lic_pre_ithread),
275 DEVMETHOD(pic_post_ithread, tegra_lic_post_ithread),
276 DEVMETHOD(pic_post_filter, tegra_lic_post_filter),
278 DEVMETHOD(pic_bind_intr, tegra_lic_bind_intr),
283 devclass_t tegra_lic_devclass;
284 static DEFINE_CLASS_0(lic, tegra_lic_driver, tegra_lic_methods,
285 sizeof(struct tegra_lic_sc));
286 EARLY_DRIVER_MODULE(tegra_lic, simplebus, tegra_lic_driver, tegra_lic_devclass,
287 NULL, NULL, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE + 1);