2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 enum tegra_suspend_mode {
33 TEGRA_SUSPEND_NONE = 0,
34 TEGRA_SUSPEND_LP2, /* CPU voltage off */
35 TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */
36 TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */
39 /* PARTIDs for powergate */
40 enum tegra_powergate_id {
41 TEGRA_POWERGATE_CRAIL = 0,
42 TEGRA_POWERGATE_TD = 1,
43 TEGRA_POWERGATE_VE = 2,
44 TEGRA_POWERGATE_PCX = 3,
45 TEGRA_POWERGATE_VDE = 4,
46 TEGRA_POWERGATE_L2C = 5,
47 TEGRA_POWERGATE_MPE = 6,
48 TEGRA_POWERGATE_HEG = 7,
49 TEGRA_POWERGATE_SAX = 8,
50 TEGRA_POWERGATE_CE1 = 9,
51 TEGRA_POWERGATE_CE2 = 10,
52 TEGRA_POWERGATE_CE3 = 11,
53 TEGRA_POWERGATE_CELP = 12,
55 TEGRA_POWERGATE_CE0 = 14,
56 TEGRA_POWERGATE_C0NC = 15,
57 TEGRA_POWERGATE_C1NC = 16,
58 TEGRA_POWERGATE_SOR = 17,
59 TEGRA_POWERGATE_DIS = 18,
60 TEGRA_POWERGATE_DISB = 19,
61 TEGRA_POWERGATE_XUSBA = 20,
62 TEGRA_POWERGATE_XUSBB = 21,
63 TEGRA_POWERGATE_XUSBC = 22,
64 TEGRA_POWERGATE_VIC = 23,
65 TEGRA_POWERGATE_IRAM = 24,
67 TEGRA_POWERGATE_3D = 32
71 /* PARTIDs for power rails */
72 enum tegra_powerrail_id {
73 TEGRA_IO_RAIL_CSIA = 0,
74 TEGRA_IO_RAIL_CSIB = 1,
75 TEGRA_IO_RAIL_DSI = 2,
76 TEGRA_IO_RAIL_MIPI_BIAS = 3,
77 TEGRA_IO_RAIL_PEX_BIAS = 4,
78 TEGRA_IO_RAIL_PEX_CLK1 = 5,
79 TEGRA_IO_RAIL_PEX_CLK2 = 6,
80 TEGRA_IO_RAIL_USB0 = 9,
81 TEGRA_IO_RAIL_USB1 = 10,
82 TEGRA_IO_RAIL_USB2 = 11,
83 TEGRA_IO_RAIL_USB_BIAS = 12,
84 TEGRA_IO_RAIL_NAND = 13,
85 TEGRA_IO_RAIL_UART = 14,
86 TEGRA_IO_RAIL_BB = 15,
87 TEGRA_IO_RAIL_AUDIO = 17,
88 TEGRA_IO_RAIL_HSIC = 19,
89 TEGRA_IO_RAIL_COMP = 22,
90 TEGRA_IO_RAIL_HDMI = 28,
91 TEGRA_IO_RAIL_PEX_CNTRL = 32,
92 TEGRA_IO_RAIL_SDMMC1 = 33,
93 TEGRA_IO_RAIL_SDMMC3 = 34,
94 TEGRA_IO_RAIL_SDMMC4 = 35,
95 TEGRA_IO_RAIL_CAM = 36,
96 TEGRA_IO_RAIL_RES = 37,
97 TEGRA_IO_RAIL_HV = 38,
98 TEGRA_IO_RAIL_DSIB = 39,
99 TEGRA_IO_RAIL_DSIC = 40,
100 TEGRA_IO_RAIL_DSID = 41,
101 TEGRA_IO_RAIL_CSIE = 44,
102 TEGRA_IO_RAIL_LVDS = 57,
103 TEGRA_IO_RAIL_SYS_DDC = 58,
106 int tegra_powergate_is_powered(enum tegra_powergate_id id);
107 int tegra_powergate_power_on(enum tegra_powergate_id id);
108 int tegra_powergate_power_off(enum tegra_powergate_id id);
109 int tegra_powergate_remove_clamping(enum tegra_powergate_id id);
110 int tegra_powergate_sequence_power_up(enum tegra_powergate_id id,
111 clk_t clk, hwreset_t rst);
112 int tegra_io_rail_power_on(int tegra_powerrail_id);
113 int tegra_io_rail_power_off(int tegra_powerrail_id);
115 #endif /*_TEGRA_PMC_H_*/