2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * SDHCI driver glue for NVIDIA Tegra family
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/types.h>
39 #include <sys/kernel.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/resource.h>
46 #include <sys/sysctl.h>
47 #include <sys/taskqueue.h>
49 #include <machine/bus.h>
50 #include <machine/resource.h>
51 #include <machine/intr.h>
53 #include <dev/extres/clk/clk.h>
54 #include <dev/extres/hwreset/hwreset.h>
55 #include <dev/gpio/gpiobusvar.h>
56 #include <dev/mmc/bridge.h>
57 #include <dev/mmc/mmcbrvar.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_bus_subr.h>
60 #include <dev/sdhci/sdhci.h>
61 #include <dev/sdhci/sdhci_fdt_gpio.h>
65 #include "opt_mmccam.h"
67 /* Tegra SDHOST controller vendor register definitions */
68 #define SDMMC_VENDOR_CLOCK_CNTRL 0x100
69 #define VENDOR_CLOCK_CNTRL_CLK_SHIFT 8
70 #define VENDOR_CLOCK_CNTRL_CLK_MASK 0xFF
71 #define SDMMC_VENDOR_SYS_SW_CNTRL 0x104
72 #define SDMMC_VENDOR_CAP_OVERRIDES 0x10C
73 #define SDMMC_VENDOR_BOOT_CNTRL 0x110
74 #define SDMMC_VENDOR_BOOT_ACK_TIMEOUT 0x114
75 #define SDMMC_VENDOR_BOOT_DAT_TIMEOUT 0x118
76 #define SDMMC_VENDOR_DEBOUNCE_COUNT 0x11C
77 #define SDMMC_VENDOR_MISC_CNTRL 0x120
78 #define VENDOR_MISC_CTRL_ENABLE_SDR104 0x8
79 #define VENDOR_MISC_CTRL_ENABLE_SDR50 0x10
80 #define VENDOR_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
81 #define VENDOR_MISC_CTRL_ENABLE_DDR50 0x200
82 #define SDMMC_MAX_CURRENT_OVERRIDE 0x124
83 #define SDMMC_MAX_CURRENT_OVERRIDE_HI 0x128
84 #define SDMMC_VENDOR_CLK_GATE_HYSTERESIS_COUNT 0x1D0
85 #define SDMMC_VENDOR_PHWRESET_VAL0 0x1D4
86 #define SDMMC_VENDOR_PHWRESET_VAL1 0x1D8
87 #define SDMMC_VENDOR_PHWRESET_VAL2 0x1DC
88 #define SDMMC_SDMEMCOMPPADCTRL_0 0x1E0
89 #define SDMMC_AUTO_CAL_CONFIG 0x1E4
90 #define SDMMC_AUTO_CAL_INTERVAL 0x1E8
91 #define SDMMC_AUTO_CAL_STATUS 0x1EC
92 #define SDMMC_SDMMC_MCCIF_FIFOCTRL 0x1F4
93 #define SDMMC_TIMEOUT_WCOAL_SDMMC 0x1F8
95 /* Compatible devices. */
96 static struct ofw_compat_data compat_data[] = {
97 {"nvidia,tegra124-sdhci", 1},
101 struct tegra_sdhci_softc {
103 struct resource * mem_res;
104 struct resource * irq_res;
106 u_int quirks; /* Chip specific quirks */
107 u_int caps; /* If we override SDHCI_CAPABILITIES */
108 uint32_t max_clk; /* Max possible freq */
111 gpio_pin_t gpio_power;
112 struct sdhci_fdt_gpio *gpio;
114 int force_card_present;
115 struct sdhci_slot slot;
119 static inline uint32_t
120 RD4(struct tegra_sdhci_softc *sc, bus_size_t off)
123 return (bus_read_4(sc->mem_res, off));
127 tegra_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
129 struct tegra_sdhci_softc *sc;
131 sc = device_get_softc(dev);
132 return (bus_read_1(sc->mem_res, off));
136 tegra_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
138 struct tegra_sdhci_softc *sc;
140 sc = device_get_softc(dev);
141 return (bus_read_2(sc->mem_res, off));
145 tegra_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
147 struct tegra_sdhci_softc *sc;
150 sc = device_get_softc(dev);
151 val32 = bus_read_4(sc->mem_res, off);
152 /* Force the card-present state if necessary. */
153 if (off == SDHCI_PRESENT_STATE && sc->force_card_present)
154 val32 |= SDHCI_CARD_PRESENT;
159 tegra_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
160 uint32_t *data, bus_size_t count)
162 struct tegra_sdhci_softc *sc;
164 sc = device_get_softc(dev);
165 bus_read_multi_4(sc->mem_res, off, data, count);
169 tegra_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
172 struct tegra_sdhci_softc *sc;
174 sc = device_get_softc(dev);
175 bus_write_1(sc->mem_res, off, val);
179 tegra_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
182 struct tegra_sdhci_softc *sc;
184 sc = device_get_softc(dev);
185 bus_write_2(sc->mem_res, off, val);
189 tegra_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
192 struct tegra_sdhci_softc *sc;
194 sc = device_get_softc(dev);
195 bus_write_4(sc->mem_res, off, val);
199 tegra_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
200 uint32_t *data, bus_size_t count)
202 struct tegra_sdhci_softc *sc;
204 sc = device_get_softc(dev);
205 bus_write_multi_4(sc->mem_res, off, data, count);
209 tegra_sdhci_intr(void *arg)
211 struct tegra_sdhci_softc *sc = arg;
213 sdhci_generic_intr(&sc->slot);
214 RD4(sc, SDHCI_INT_STATUS);
218 tegra_sdhci_get_ro(device_t brdev, device_t reqdev)
220 struct tegra_sdhci_softc *sc = device_get_softc(brdev);
222 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
226 tegra_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
228 struct tegra_sdhci_softc *sc = device_get_softc(dev);
230 return (sdhci_fdt_gpio_get_present(sc->gpio));
234 tegra_sdhci_probe(device_t dev)
236 struct tegra_sdhci_softc *sc;
239 const struct ofw_compat_data *cd;
241 sc = device_get_softc(dev);
242 if (!ofw_bus_status_okay(dev))
245 if (ofw_bus_is_compatible(dev, "nvidia,tegra124-sdhci")) {
246 device_set_desc(dev, "Tegra SDHCI controller");
249 cd = ofw_bus_search_compatible(dev, compat_data);
250 if (cd->ocd_data == 0)
253 node = ofw_bus_get_node(dev);
255 /* Allow dts to patch quirks, slots, and max-frequency. */
256 if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0)
258 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0)
261 return (BUS_PROBE_DEFAULT);
265 tegra_sdhci_attach(device_t dev)
267 struct tegra_sdhci_softc *sc;
270 phandle_t node, prop;
272 sc = device_get_softc(dev);
274 node = ofw_bus_get_node(dev);
277 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
280 device_printf(dev, "cannot allocate memory window\n");
286 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
289 device_printf(dev, "cannot allocate interrupt\n");
294 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
295 NULL, tegra_sdhci_intr, sc, &sc->intr_cookie)) {
296 device_printf(dev, "cannot setup interrupt handler\n");
301 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sdhci", &sc->reset);
303 device_printf(sc->dev, "Cannot get 'sdhci' reset\n");
306 rv = hwreset_deassert(sc->reset);
308 device_printf(dev, "Cannot unreset 'sdhci' reset\n");
312 gpio_pin_get_by_ofw_property(sc->dev, node, "power-gpios", &sc->gpio_power);
314 rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
316 device_printf(dev, "Cannot get clock\n");
319 rv = clk_enable(sc->clk);
321 device_printf(dev, "Cannot enable clock\n");
324 rv = clk_set_freq(sc->clk, 48000000, CLK_SET_ROUND_DOWN);
326 device_printf(dev, "Cannot set clock\n");
328 rv = clk_get_freq(sc->clk, &freq);
330 device_printf(dev, "Cannot get clock frequency\n");
334 device_printf(dev, " Base MMC clock: %lld\n", freq);
336 /* Fill slot information. */
337 sc->max_clk = (int)freq;
338 sc->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
339 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
340 SDHCI_QUIRK_MISSING_CAPS;
342 /* Limit real slot capabilities. */
343 sc->caps = RD4(sc, SDHCI_CAPABILITIES);
344 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) {
345 sc->caps &= ~(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
348 sc->caps |= MMC_CAP_8_BIT_DATA;
351 sc->caps |= MMC_CAP_4_BIT_DATA;
356 device_printf(dev, "Bad bus-width value %u\n", prop);
360 if (OF_hasprop(node, "non-removable"))
361 sc->force_card_present = 1;
363 * Clear clock field, so SDHCI driver uses supplied frequency.
364 * in sc->slot.max_clk
366 sc->caps &= ~SDHCI_CLOCK_V3_BASE_MASK;
368 sc->slot.quirks = sc->quirks;
369 sc->slot.max_clk = sc->max_clk;
370 sc->slot.caps = sc->caps;
372 rv = sdhci_init_slot(dev, &sc->slot, 0);
377 sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot);
379 bus_generic_probe(dev);
380 bus_generic_attach(dev);
382 sdhci_start_slot(&sc->slot);
387 if (sc->gpio != NULL)
388 sdhci_fdt_gpio_teardown(sc->gpio);
389 if (sc->intr_cookie != NULL)
390 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
391 if (sc->gpio_power != NULL)
392 gpio_pin_release(sc->gpio_power);
394 clk_release(sc->clk);
395 if (sc->reset != NULL)
396 hwreset_release(sc->reset);
397 if (sc->irq_res != NULL)
398 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
399 if (sc->mem_res != NULL)
400 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
406 tegra_sdhci_detach(device_t dev)
408 struct tegra_sdhci_softc *sc = device_get_softc(dev);
409 struct sdhci_slot *slot = &sc->slot;
411 bus_generic_detach(dev);
412 sdhci_fdt_gpio_teardown(sc->gpio);
413 clk_release(sc->clk);
414 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
415 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
418 sdhci_cleanup_slot(slot);
419 bus_release_resource(dev, SYS_RES_MEMORY,
420 rman_get_rid(sc->mem_res),
425 static device_method_t tegra_sdhci_methods[] = {
426 /* Device interface */
427 DEVMETHOD(device_probe, tegra_sdhci_probe),
428 DEVMETHOD(device_attach, tegra_sdhci_attach),
429 DEVMETHOD(device_detach, tegra_sdhci_detach),
432 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
433 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
435 /* MMC bridge interface */
436 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
437 DEVMETHOD(mmcbr_request, sdhci_generic_request),
438 DEVMETHOD(mmcbr_get_ro, tegra_sdhci_get_ro),
439 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
440 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
442 /* SDHCI registers accessors */
443 DEVMETHOD(sdhci_read_1, tegra_sdhci_read_1),
444 DEVMETHOD(sdhci_read_2, tegra_sdhci_read_2),
445 DEVMETHOD(sdhci_read_4, tegra_sdhci_read_4),
446 DEVMETHOD(sdhci_read_multi_4, tegra_sdhci_read_multi_4),
447 DEVMETHOD(sdhci_write_1, tegra_sdhci_write_1),
448 DEVMETHOD(sdhci_write_2, tegra_sdhci_write_2),
449 DEVMETHOD(sdhci_write_4, tegra_sdhci_write_4),
450 DEVMETHOD(sdhci_write_multi_4, tegra_sdhci_write_multi_4),
451 DEVMETHOD(sdhci_get_card_present, tegra_sdhci_get_card_present),
456 static devclass_t tegra_sdhci_devclass;
457 static DEFINE_CLASS_0(sdhci, tegra_sdhci_driver, tegra_sdhci_methods,
458 sizeof(struct tegra_sdhci_softc));
459 DRIVER_MODULE(sdhci_tegra, simplebus, tegra_sdhci_driver, tegra_sdhci_devclass,
461 SDHCI_DEPEND(sdhci_tegra);
463 MMC_DECLARE_BRIDGE(sdhci);