2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include "opt_platform.h"
30 #include <sys/cdefs.h>
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/reboot.h>
35 #include <sys/devmap.h>
40 #include <machine/cpu.h>
41 #include <machine/bus.h>
42 #include <machine/intr.h>
43 #include <machine/machdep.h>
44 #include <machine/platformvar.h>
45 #include <machine/smp.h>
47 #include <dev/fdt/fdt_common.h>
48 #include <dev/ofw/openfirm.h>
49 #include <dev/ofw/ofw_cpu.h>
51 #include <arm/qualcomm/qcom_cpu_kpssv2_reg.h>
52 #include <arm/qualcomm/qcom_cpu_kpssv2.h>
54 #include "platform_if.h"
57 * Since DELAY() hangs this early, we need some way to
58 * delay things to settle.
63 int lcount = usec * 100000;
65 for (volatile int i = 0; i < lcount; i++)
70 * This is the KPSSv2 (eg IPQ4018) regulator path for CPU
71 * and shared L2 cache power-on.
74 qcom_cpu_kpssv2_regulator_start(u_int id, phandle_t node)
76 phandle_t acc_phandle, l2_phandle, saw_phandle;
77 bus_space_tag_t acc_tag, saw_tag;
78 bus_space_handle_t acc_handle, saw_handle;
79 bus_size_t acc_sz, saw_sz;
85 * We don't need to power up CPU 0! This will power it
86 * down first and ... then everything hangs.
92 * Walk the qcom,acc and next-level-cache entries to find their
93 * child phandles and thus regulators.
95 * The qcom,acc is a phandle to a node.
97 * The next-level-cache actually is a phandle through to a qcom,saw
100 sret = OF_getencprop(node, "qcom,acc", (void *) &acc_phandle,
101 sizeof(acc_phandle));
102 if (sret != sizeof(acc_phandle))
103 panic("***couldn't get phandle for qcom,acc");
104 acc_phandle = OF_node_from_xref(acc_phandle);
106 sret = OF_getencprop(node, "next-level-cache", (void *) &l2_phandle,
108 if (sret != sizeof(l2_phandle))
109 panic("***couldn't get phandle for next-level-cache");
110 l2_phandle = OF_node_from_xref(l2_phandle);
112 sret = OF_getencprop(l2_phandle, "qcom,saw", (void *) &saw_phandle,
113 sizeof(saw_phandle));
114 if (sret != sizeof(saw_phandle))
115 panic("***couldn't get phandle for qcom,saw");
116 l2_phandle = OF_node_from_xref(l2_phandle);
119 * Now that we have the phandles referencing the correct locations,
120 * do some KVA mappings so we can go access the registers.
122 ret = OF_decode_addr(acc_phandle, 0, &acc_tag, &acc_handle, &acc_sz);
124 panic("*** couldn't map qcom,acc space (%d)", ret);
125 ret = OF_decode_addr(saw_phandle, 0, &saw_tag, &saw_handle, &saw_sz);
127 panic("*** couldn't map next-level-cache -> "
128 "qcom,saw space (%d)", ret);
131 * Power sequencing to ensure the cores are off, then power them on
132 * and bring them out of reset.
137 * LDO: bypassed, powered off
139 reg_val = (64 << QCOM_APC_PWR_GATE_CTL_BHS_CNT_SHIFT)
140 | (0x3f << QCOM_APC_PWR_GATE_CTL_LDO_PWR_DWN_SHIFT)
141 | QCOM_APC_PWR_GATE_CTL_BHS_EN;
142 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val);
148 * Start up BHS segments.
150 reg_val |= 0x3f << QCOM_APC_PWR_GATE_CTL_BHS_SEG_SHIFT;
151 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val);
157 * Switch on the LDO bypass; BHS will now supply power.
159 reg_val |= 0x3f << QCOM_APC_PWR_GATE_CTL_LDO_BYP_SHIFT;
160 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val);
163 * Shared L2 regulator control.
165 bus_space_write_4(saw_tag, saw_handle, QCOM_APCS_SAW2_2_VCTL, 0x10003);
171 * Put the core in reset.
173 reg_val = QCOM_APCS_CPU_PWR_CTL_COREPOR_RST
174 | QCOM_APCS_CPU_PWR_CTL_CLAMP;
175 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val);
180 * Remove power-down clamp.
182 reg_val &= ~QCOM_APCS_CPU_PWR_CTL_CLAMP;
183 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val);
188 * Clear core power reset.
190 reg_val &= ~QCOM_APCS_CPU_PWR_CTL_COREPOR_RST;
191 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val);
195 * The power is ready, the core is out of reset, signal the core
198 reg_val |= QCOM_APCS_CPU_PWR_CTL_CORE_PWRD_UP;
199 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val);
203 * Finished with these KVA mappings, so release them.
205 bus_space_unmap(acc_tag, acc_handle, acc_sz);
206 bus_space_unmap(saw_tag, saw_handle, saw_sz);