2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include "opt_platform.h"
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/reboot.h>
37 #include <sys/devmap.h>
42 #include <machine/cpu.h>
43 #include <machine/bus.h>
44 #include <machine/intr.h>
45 #include <machine/machdep.h>
46 #include <machine/platformvar.h>
47 #include <machine/smp.h>
49 #include <dev/fdt/fdt_common.h>
50 #include <dev/ofw/openfirm.h>
51 #include <dev/ofw/ofw_cpu.h>
53 #include <arm/qualcomm/qcom_cpu_kpssv2_reg.h>
54 #include <arm/qualcomm/qcom_cpu_kpssv2.h>
56 #include "platform_if.h"
59 * Since DELAY() hangs this early, we need some way to
60 * delay things to settle.
65 int lcount = usec * 100000;
67 for (volatile int i = 0; i < lcount; i++)
72 * This is the KPSSv2 (eg IPQ4018) regulator path for CPU
73 * and shared L2 cache power-on.
76 qcom_cpu_kpssv2_regulator_start(u_int id, phandle_t node)
78 phandle_t acc_phandle, l2_phandle, saw_phandle;
79 bus_space_tag_t acc_tag, saw_tag;
80 bus_space_handle_t acc_handle, saw_handle;
81 bus_size_t acc_sz, saw_sz;
87 * We don't need to power up CPU 0! This will power it
88 * down first and ... then everything hangs.
94 * Walk the qcom,acc and next-level-cache entries to find their
95 * child phandles and thus regulators.
97 * The qcom,acc is a phandle to a node.
99 * The next-level-cache actually is a phandle through to a qcom,saw
102 sret = OF_getencprop(node, "qcom,acc", (void *) &acc_phandle,
103 sizeof(acc_phandle));
104 if (sret != sizeof(acc_phandle))
105 panic("***couldn't get phandle for qcom,acc");
106 acc_phandle = OF_node_from_xref(acc_phandle);
108 sret = OF_getencprop(node, "next-level-cache", (void *) &l2_phandle,
110 if (sret != sizeof(l2_phandle))
111 panic("***couldn't get phandle for next-level-cache");
112 l2_phandle = OF_node_from_xref(l2_phandle);
114 sret = OF_getencprop(l2_phandle, "qcom,saw", (void *) &saw_phandle,
115 sizeof(saw_phandle));
116 if (sret != sizeof(saw_phandle))
117 panic("***couldn't get phandle for qcom,saw");
118 l2_phandle = OF_node_from_xref(l2_phandle);
121 * Now that we have the phandles referencing the correct locations,
122 * do some KVA mappings so we can go access the registers.
124 ret = OF_decode_addr(acc_phandle, 0, &acc_tag, &acc_handle, &acc_sz);
126 panic("*** couldn't map qcom,acc space (%d)", ret);
127 ret = OF_decode_addr(saw_phandle, 0, &saw_tag, &saw_handle, &saw_sz);
129 panic("*** couldn't map next-level-cache -> "
130 "qcom,saw space (%d)", ret);
133 * Power sequencing to ensure the cores are off, then power them on
134 * and bring them out of reset.
139 * LDO: bypassed, powered off
141 reg_val = (64 << QCOM_APC_PWR_GATE_CTL_BHS_CNT_SHIFT)
142 | (0x3f << QCOM_APC_PWR_GATE_CTL_LDO_PWR_DWN_SHIFT)
143 | QCOM_APC_PWR_GATE_CTL_BHS_EN;
144 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val);
150 * Start up BHS segments.
152 reg_val |= 0x3f << QCOM_APC_PWR_GATE_CTL_BHS_SEG_SHIFT;
153 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val);
159 * Switch on the LDO bypass; BHS will now supply power.
161 reg_val |= 0x3f << QCOM_APC_PWR_GATE_CTL_LDO_BYP_SHIFT;
162 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val);
165 * Shared L2 regulator control.
167 bus_space_write_4(saw_tag, saw_handle, QCOM_APCS_SAW2_2_VCTL, 0x10003);
173 * Put the core in reset.
175 reg_val = QCOM_APCS_CPU_PWR_CTL_COREPOR_RST
176 | QCOM_APCS_CPU_PWR_CTL_CLAMP;
177 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val);
182 * Remove power-down clamp.
184 reg_val &= ~QCOM_APCS_CPU_PWR_CTL_CLAMP;
185 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val);
190 * Clear core power reset.
192 reg_val &= ~QCOM_APCS_CPU_PWR_CTL_COREPOR_RST;
193 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val);
197 * The power is ready, the core is out of reset, signal the core
200 reg_val |= QCOM_APCS_CPU_PWR_CTL_CORE_PWRD_UP;
201 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val);
205 * Finished with these KVA mappings, so release them.
207 bus_space_unmap(acc_tag, acc_handle, acc_sz);
208 bus_space_unmap(saw_tag, saw_handle, saw_sz);