2 * Copyright (c) 2016 Hiroki Mori. All rights reserved.
4 * Oleksandr Tymoshenko <gonzo@freebsd.org>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWFV IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE FV DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWFV, EVEN IF ADVISED OF
25 * THE POSSIBILITY OF SUCH DAMAGE.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * FV Ethernet interface driver
36 * copy from mips/idt/if_kr.c and netbsd code
38 #include <sys/param.h>
39 #include <sys/endian.h>
40 #include <sys/systm.h>
41 #include <sys/sockio.h>
43 #include <sys/malloc.h>
44 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/socket.h>
49 #include <sys/taskqueue.h>
52 #include <net/if_arp.h>
53 #include <net/ethernet.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/if_types.h>
57 #include <net/if_var.h>
61 #include <dev/ofw/ofw_bus.h>
62 #include <dev/ofw/ofw_bus_subr.h>
64 #include <machine/bus.h>
65 #include <machine/resource.h>
69 #include <dev/mii/mii.h>
70 #include <dev/mii/miivar.h>
72 /* Todo: move to options.arm */
76 #include <dev/mdio/mdio.h>
77 #include <dev/etherswitch/miiproxy.h>
81 MODULE_DEPEND(are, ether, 1, 1, 1);
82 MODULE_DEPEND(are, miibus, 1, 1, 1);
84 MODULE_DEPEND(are, mdio, 1, 1, 1);
87 #include "miibus_if.h"
89 #include <arm/ralink/if_fvreg.h>
92 void dump_txdesc(struct fv_softc *, int);
93 void dump_status_reg(struct fv_softc *);
96 static int fv_attach(device_t);
97 static int fv_detach(device_t);
98 static int fv_ifmedia_upd(struct ifnet *);
99 static void fv_ifmedia_sts(struct ifnet *, struct ifmediareq *);
100 static int fv_ioctl(struct ifnet *, u_long, caddr_t);
101 static void fv_init(void *);
102 static void fv_init_locked(struct fv_softc *);
103 static void fv_link_task(void *, int);
104 static int fv_miibus_readreg(device_t, int, int);
105 static void fv_miibus_statchg(device_t);
106 static int fv_miibus_writereg(device_t, int, int, int);
107 static int fv_probe(device_t);
108 static void fv_reset(struct fv_softc *);
109 static int fv_resume(device_t);
110 static int fv_rx_ring_init(struct fv_softc *);
111 static int fv_tx_ring_init(struct fv_softc *);
112 static int fv_shutdown(device_t);
113 static void fv_start(struct ifnet *);
114 static void fv_start_locked(struct ifnet *);
115 static void fv_stop(struct fv_softc *);
116 static int fv_suspend(device_t);
118 static void fv_rx(struct fv_softc *);
119 static void fv_tx(struct fv_softc *);
120 static void fv_intr(void *);
121 static void fv_tick(void *);
123 static void fv_dmamap_cb(void *, bus_dma_segment_t *, int, int);
124 static int fv_dma_alloc(struct fv_softc *);
125 static void fv_dma_free(struct fv_softc *);
126 static int fv_newbuf(struct fv_softc *, int);
127 static __inline void fv_fixup_rx(struct mbuf *);
129 static void fv_hinted_child(device_t bus, const char *dname, int dunit);
131 static void fv_setfilt(struct fv_softc *sc);
133 static device_method_t fv_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, fv_probe),
136 DEVMETHOD(device_attach, fv_attach),
137 DEVMETHOD(device_detach, fv_detach),
138 DEVMETHOD(device_suspend, fv_suspend),
139 DEVMETHOD(device_resume, fv_resume),
140 DEVMETHOD(device_shutdown, fv_shutdown),
143 DEVMETHOD(miibus_readreg, fv_miibus_readreg),
144 DEVMETHOD(miibus_writereg, fv_miibus_writereg),
145 #if !defined(FV_MDIO)
146 DEVMETHOD(miibus_statchg, fv_miibus_statchg),
150 DEVMETHOD(bus_add_child, device_add_child_ordered),
151 DEVMETHOD(bus_hinted_child, fv_hinted_child),
156 static driver_t fv_driver = {
159 sizeof(struct fv_softc)
162 static devclass_t fv_devclass;
164 DRIVER_MODULE(fv, simplebus, fv_driver, fv_devclass, 0, 0);
166 DRIVER_MODULE(miibus, fv, miibus_driver, miibus_devclass, 0, 0);
169 static struct mtx miibus_mtx;
170 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "are mii lock", MTX_DEF);
173 static int fvmdio_probe(device_t);
174 static int fvmdio_attach(device_t);
175 static int fvmdio_detach(device_t);
178 * Declare an additional, separate driver for accessing the MDIO bus.
180 static device_method_t fvmdio_methods[] = {
181 /* Device interface */
182 DEVMETHOD(device_probe, fvmdio_probe),
183 DEVMETHOD(device_attach, fvmdio_attach),
184 DEVMETHOD(device_detach, fvmdio_detach),
187 DEVMETHOD(bus_add_child, device_add_child_ordered),
190 DEVMETHOD(mdio_readreg, fv_miibus_readreg),
191 DEVMETHOD(mdio_writereg, fv_miibus_writereg),
194 DEFINE_CLASS_0(fvmdio, fvmdio_driver, fvmdio_methods,
195 sizeof(struct fv_softc));
196 static devclass_t fvmdio_devclass;
198 DRIVER_MODULE(miiproxy, fv, miiproxy_driver, miiproxy_devclass, 0, 0);
199 DRIVER_MODULE(fvmdio, simplebus, fvmdio_driver, fvmdio_devclass, 0, 0);
200 DRIVER_MODULE(mdio, fvmdio, mdio_driver, mdio_devclass, 0, 0);
203 /* setup frame code refer dc code */
206 fv_setfilt(struct fv_softc *sc)
208 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
209 struct fv_desc *sframe;
212 struct ifmultiaddr *ifma;
218 i = sc->fv_cdata.fv_tx_prod;
219 FV_INC(sc->fv_cdata.fv_tx_prod, FV_TX_RING_CNT);
220 sc->fv_cdata.fv_tx_cnt++;
221 sframe = &sc->fv_rdata.fv_tx_ring[i];
222 sp = (uint16_t *)sc->fv_cdata.fv_sf_buff;
223 memset(sp, 0xff, FV_SFRAME_LEN);
225 sframe->fv_addr = sc->fv_rdata.fv_sf_paddr;
226 sframe->fv_devcs = ADCTL_Tx_SETUP | FV_DMASIZE(FV_SFRAME_LEN);
230 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
231 if (ifma->ifma_addr->sa_family != AF_LINK)
233 ma = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
234 sp[i] = sp[i+1] = (ma[1] << 8 | ma[0]);
236 sp[i] = sp[i+1] = (ma[3] << 8 | ma[2]);
238 sp[i] = sp[i+1] = (ma[5] << 8 | ma[4]);
241 if_maddr_runlock(ifp);
243 bcopy(IF_LLADDR(sc->fv_ifp), eaddr, ETHER_ADDR_LEN);
244 sp[90] = sp[91] = eaddr[0];
245 sp[92] = sp[93] = eaddr[1];
246 sp[94] = sp[95] = eaddr[2];
248 sframe->fv_stat = ADSTAT_OWN;
249 bus_dmamap_sync(sc->fv_cdata.fv_tx_ring_tag,
250 sc->fv_cdata.fv_tx_ring_map, BUS_DMASYNC_PREWRITE);
251 bus_dmamap_sync(sc->fv_cdata.fv_sf_tag,
252 sc->fv_cdata.fv_sf_buff_map, BUS_DMASYNC_PREWRITE);
253 CSR_WRITE_4(sc, CSR_TXPOLL, 0xFFFFFFFF);
258 fv_probe(device_t dev)
261 if (!ofw_bus_status_okay(dev))
264 if (!ofw_bus_is_compatible(dev, "fv,ethernet"))
267 device_set_desc(dev, "FV Ethernet interface");
268 return (BUS_PROBE_DEFAULT);
272 fv_attach(device_t dev)
280 sc = device_get_softc(dev);
281 unit = device_get_unit(dev);
283 sc->fv_ofw = ofw_bus_get_node(dev);
285 i = OF_getprop(sc->fv_ofw, "local-mac-address", (void *)&sc->fv_eaddr, 6);
287 /* hardcode macaddress */
288 sc->fv_eaddr[0] = 0x00;
289 sc->fv_eaddr[1] = 0x0C;
290 sc->fv_eaddr[2] = 0x42;
291 sc->fv_eaddr[3] = 0x09;
292 sc->fv_eaddr[4] = 0x5E;
293 sc->fv_eaddr[5] = 0x6B;
296 mtx_init(&sc->fv_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
298 callout_init_mtx(&sc->fv_stat_callout, &sc->fv_mtx, 0);
299 TASK_INIT(&sc->fv_link_task, 0, fv_link_task, sc);
301 /* Map control/status registers. */
303 sc->fv_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->fv_rid,
304 RF_ACTIVE | RF_SHAREABLE);
306 if (sc->fv_res == NULL) {
307 device_printf(dev, "couldn't map memory\n");
312 sc->fv_btag = rman_get_bustag(sc->fv_res);
313 sc->fv_bhandle = rman_get_bushandle(sc->fv_res);
315 /* Allocate interrupts */
317 sc->fv_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
318 RF_SHAREABLE | RF_ACTIVE);
320 if (sc->fv_irq == NULL) {
321 device_printf(dev, "couldn't map interrupt\n");
326 /* Allocate ifnet structure. */
327 ifp = sc->fv_ifp = if_alloc(IFT_ETHER);
330 device_printf(dev, "couldn't allocate ifnet structure\n");
335 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
336 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
337 ifp->if_ioctl = fv_ioctl;
338 ifp->if_start = fv_start;
339 ifp->if_init = fv_init;
341 /* ifqmaxlen is sysctl value in net/if.c */
342 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
343 ifp->if_snd.ifq_maxlen = ifqmaxlen;
344 IFQ_SET_READY(&ifp->if_snd);
346 ifp->if_capenable = ifp->if_capabilities;
348 if (fv_dma_alloc(sc) != 0) {
353 /* TODO: calculate prescale */
355 CSR_WRITE_4(sc, FV_ETHMCP, (165000000 / (1250000 + 1)) & ~1);
357 CSR_WRITE_4(sc, FV_MIIMCFG, FV_MIIMCFG_R);
359 CSR_WRITE_4(sc, FV_MIIMCFG, 0);
361 CSR_WRITE_4(sc, CSR_BUSMODE, BUSMODE_SWR);
365 sc->fv_miiproxy = mii_attach_proxy(sc->fv_dev);
370 error = mii_attach(dev, &sc->fv_miibus, ifp, fv_ifmedia_upd,
371 fv_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
373 device_printf(dev, "attaching PHYs failed\n");
377 ifmedia_init(&sc->fv_ifmedia, 0, fv_ifmedia_upd, fv_ifmedia_sts);
379 ifmedia_add(&sc->fv_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
380 ifmedia_set(&sc->fv_ifmedia, IFM_ETHER | IFM_AUTO);
383 /* Call MI attach routine. */
384 ether_ifattach(ifp, sc->fv_eaddr);
386 /* Hook interrupt last to avoid having to lock softc */
387 error = bus_setup_intr(dev, sc->fv_irq, INTR_TYPE_NET | INTR_MPSAFE,
388 NULL, fv_intr, sc, &sc->fv_intrhand);
391 device_printf(dev, "couldn't set up irq\n");
404 fv_detach(device_t dev)
406 struct fv_softc *sc = device_get_softc(dev);
407 struct ifnet *ifp = sc->fv_ifp;
409 KASSERT(mtx_initialized(&sc->fv_mtx), ("vr mutex not initialized"));
411 /* These should only be active if attach succeeded */
412 if (device_is_attached(dev)) {
417 taskqueue_drain(taskqueue_swi, &sc->fv_link_task);
422 device_delete_child(dev, sc->fv_miibus);
424 bus_generic_detach(dev);
427 bus_teardown_intr(dev, sc->fv_irq, sc->fv_intrhand);
429 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->fv_irq);
432 bus_release_resource(dev, SYS_RES_MEMORY, sc->fv_rid,
440 mtx_destroy(&sc->fv_mtx);
447 fv_suspend(device_t dev)
450 panic("%s", __func__);
455 fv_resume(device_t dev)
458 panic("%s", __func__);
463 fv_shutdown(device_t dev)
467 sc = device_get_softc(dev);
477 fv_miibus_readbits(struct fv_softc *sc, int count)
484 CSR_WRITE_4(sc, CSR_MIIMNG, MII_RD);
486 CSR_WRITE_4(sc, CSR_MIIMNG, MII_RD | MII_CLK);
488 if (CSR_READ_4(sc, CSR_MIIMNG) & MII_DIN)
496 fv_miibus_writebits(struct fv_softc *sc, int data, int count)
501 bit = ((data) >> count) & 0x1 ? MII_DOUT : 0;
502 CSR_WRITE_4(sc, CSR_MIIMNG, bit | MII_WR);
504 CSR_WRITE_4(sc, CSR_MIIMNG, bit | MII_WR | MII_CLK);
512 fv_miibus_turnaround(struct fv_softc *sc, int cmd)
514 if (cmd == MII_WRCMD) {
515 fv_miibus_writebits(sc, 0x02, 2);
517 fv_miibus_readbits(sc, 1);
522 fv_miibus_readreg(device_t dev, int phy, int reg)
524 struct fv_softc * sc = device_get_softc(dev);
527 mtx_lock(&miibus_mtx);
528 fv_miibus_writebits(sc, MII_PREAMBLE, 32);
529 fv_miibus_writebits(sc, MII_RDCMD, 4);
530 fv_miibus_writebits(sc, phy, 5);
531 fv_miibus_writebits(sc, reg, 5);
532 fv_miibus_turnaround(sc, MII_RDCMD);
533 result = fv_miibus_readbits(sc, 16);
534 fv_miibus_turnaround(sc, MII_RDCMD);
535 mtx_unlock(&miibus_mtx);
541 fv_miibus_writereg(device_t dev, int phy, int reg, int data)
543 struct fv_softc * sc = device_get_softc(dev);
545 mtx_lock(&miibus_mtx);
546 fv_miibus_writebits(sc, MII_PREAMBLE, 32);
547 fv_miibus_writebits(sc, MII_WRCMD, 4);
548 fv_miibus_writebits(sc, phy, 5);
549 fv_miibus_writebits(sc, reg, 5);
550 fv_miibus_turnaround(sc, MII_WRCMD);
551 fv_miibus_writebits(sc, data, 16);
552 mtx_unlock(&miibus_mtx);
557 #if !defined(FV_MDIO)
559 fv_miibus_statchg(device_t dev)
563 sc = device_get_softc(dev);
564 taskqueue_enqueue(taskqueue_swi, &sc->fv_link_task);
569 fv_link_task(void *arg, int pending)
573 struct mii_data *mii;
575 /* int lfdx, mfdx; */
577 sc = (struct fv_softc *)arg;
580 mii = device_get_softc(sc->fv_miibus);
582 if (mii == NULL || ifp == NULL ||
583 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
588 if (mii->mii_media_status & IFM_ACTIVE) {
589 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
590 sc->fv_link_status = 1;
592 sc->fv_link_status = 0;
599 fv_reset(struct fv_softc *sc)
603 CSR_WRITE_4(sc, CSR_BUSMODE, BUSMODE_SWR);
606 * The chip doesn't take itself out of reset automatically.
607 * We need to do so after 2us.
610 CSR_WRITE_4(sc, CSR_BUSMODE, 0);
612 for (i = 0; i < 1000; i++) {
614 * Wait a bit for the reset to complete before peeking
618 if ((CSR_READ_4(sc, CSR_BUSMODE) & BUSMODE_SWR) == 0)
622 if (CSR_READ_4(sc, CSR_BUSMODE) & BUSMODE_SWR)
623 device_printf(sc->fv_dev, "reset time out\n");
631 struct fv_softc *sc = xsc;
639 fv_init_locked(struct fv_softc *sc)
641 struct ifnet *ifp = sc->fv_ifp;
643 struct mii_data *mii;
649 mii = device_get_softc(sc->fv_miibus);
655 /* Init circular RX list. */
656 if (fv_rx_ring_init(sc) != 0) {
657 device_printf(sc->fv_dev,
658 "initialization failed: no memory for rx buffers\n");
663 /* Init tx descriptors. */
667 * Initialize the BUSMODE register.
669 CSR_WRITE_4(sc, CSR_BUSMODE,
670 /* XXX: not sure if this is a good thing or not... */
671 BUSMODE_BAR | BUSMODE_PBL_32LW);
674 * Initialize the interrupt mask and enable interrupts.
676 /* normal interrupts */
677 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS;
679 /* abnormal interrupts */
680 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF |
681 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS;
683 sc->sc_rxint_mask = STATUS_RI|STATUS_RU;
684 sc->sc_txint_mask = STATUS_TI|STATUS_UNF|STATUS_TJT;
686 sc->sc_rxint_mask &= sc->sc_inten;
687 sc->sc_txint_mask &= sc->sc_inten;
689 CSR_WRITE_4(sc, CSR_INTEN, sc->sc_inten);
690 CSR_WRITE_4(sc, CSR_STATUS, 0xffffffff);
693 * Give the transmit and receive rings to the chip.
695 CSR_WRITE_4(sc, CSR_TXLIST, FV_TX_RING_ADDR(sc, 0));
696 CSR_WRITE_4(sc, CSR_RXLIST, FV_RX_RING_ADDR(sc, 0));
699 * Set the station address.
705 * Write out the opmode.
707 CSR_WRITE_4(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST |
708 OPMODE_TR_128 | OPMODE_FDX | OPMODE_SPEED);
710 * Start the receive process.
712 CSR_WRITE_4(sc, CSR_RXPOLL, RXPOLL_RPD);
714 sc->fv_link_status = 1;
719 ifp->if_drv_flags |= IFF_DRV_RUNNING;
720 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
722 callout_reset(&sc->fv_stat_callout, hz, fv_tick, sc);
726 fv_start(struct ifnet *ifp)
733 fv_start_locked(ifp);
738 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
739 * pointers to the fragment pointers.
740 * Use Implicit Chain implementation.
743 fv_encap(struct fv_softc *sc, struct mbuf **m_head)
745 struct fv_txdesc *txd;
746 struct fv_desc *desc;
748 bus_dma_segment_t txsegs[FV_MAXFRAGS];
749 int error, i, nsegs, prod, si;
756 * Some VIA Rhine wants packet buffers to be longword
757 * aligned, but very often our mbufs aren't. Rather than
758 * waste time trying to decide when to copy and when not
759 * to copy, just do it all the time.
761 m = m_defrag(*m_head, M_NOWAIT);
763 device_printf(sc->fv_dev, "fv_encap m_defrag error\n");
771 * The Rhine chip doesn't auto-pad, so we have to make
772 * sure to pad short frames out to the minimum frame length
775 if ((*m_head)->m_pkthdr.len < FV_MIN_FRAMELEN) {
777 padlen = FV_MIN_FRAMELEN - m->m_pkthdr.len;
778 if (M_WRITABLE(m) == 0) {
779 /* Get a writable copy. */
780 m = m_dup(*m_head, M_NOWAIT);
783 device_printf(sc->fv_dev, "fv_encap m_dup error\n");
789 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
790 m = m_defrag(m, M_NOWAIT);
792 device_printf(sc->fv_dev, "fv_encap m_defrag error\n");
799 * Manually pad short frames, and zero the pad space
800 * to avoid leaking data.
802 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
803 m->m_pkthdr.len += padlen;
804 m->m_len = m->m_pkthdr.len;
808 prod = sc->fv_cdata.fv_tx_prod;
809 txd = &sc->fv_cdata.fv_txdesc[prod];
810 error = bus_dmamap_load_mbuf_sg(sc->fv_cdata.fv_tx_tag, txd->tx_dmamap,
811 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
812 if (error == EFBIG) {
813 device_printf(sc->fv_dev, "fv_encap EFBIG error\n");
814 m = m_defrag(*m_head, M_NOWAIT);
821 error = bus_dmamap_load_mbuf_sg(sc->fv_cdata.fv_tx_tag,
822 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
829 } else if (error != 0)
837 /* Check number of available descriptors. */
838 if (sc->fv_cdata.fv_tx_cnt + nsegs >= (FV_TX_RING_CNT - 1)) {
839 bus_dmamap_unload(sc->fv_cdata.fv_tx_tag, txd->tx_dmamap);
844 bus_dmamap_sync(sc->fv_cdata.fv_tx_tag, txd->tx_dmamap,
845 BUS_DMASYNC_PREWRITE);
850 * Make a list of descriptors for this packet.
853 for (i = 0; i < nsegs; i++) {
854 desc = &sc->fv_rdata.fv_tx_ring[prod];
855 desc->fv_stat = ADSTAT_OWN;
856 desc->fv_devcs = txsegs[i].ds_len;
857 /* end of descriptor */
858 if (prod == FV_TX_RING_CNT - 1)
859 desc->fv_devcs |= ADCTL_ER;
860 desc->fv_addr = txsegs[i].ds_addr;
862 ++sc->fv_cdata.fv_tx_cnt;
863 FV_INC(prod, FV_TX_RING_CNT);
867 * Set mark last fragment with Last/Intr flag
870 desc->fv_devcs |= ADCTL_Tx_IC;
871 desc->fv_devcs |= ADCTL_Tx_LS;
874 /* Update producer index. */
875 sc->fv_cdata.fv_tx_prod = prod;
877 /* Sync descriptors. */
878 bus_dmamap_sync(sc->fv_cdata.fv_tx_ring_tag,
879 sc->fv_cdata.fv_tx_ring_map,
880 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
882 txstat = (CSR_READ_4(sc, CSR_STATUS) >> 20) & 7;
883 if (txstat == 0 || txstat == 6) {
884 /* Transmit Process Stat is stop or suspended */
885 desc = &sc->fv_rdata.fv_tx_ring[si];
886 desc->fv_devcs |= ADCTL_Tx_FS;
889 /* Get previous descriptor */
890 si = (si + FV_TX_RING_CNT - 1) % FV_TX_RING_CNT;
891 desc = &sc->fv_rdata.fv_tx_ring[si];
892 /* join remain data and flugs */
893 desc->fv_devcs &= ~ADCTL_Tx_IC;
894 desc->fv_devcs &= ~ADCTL_Tx_LS;
902 fv_start_locked(struct ifnet *ifp)
913 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
914 IFF_DRV_RUNNING || sc->fv_link_status == 0 )
917 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
918 sc->fv_cdata.fv_tx_cnt < FV_TX_RING_CNT - 2; ) {
919 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
923 * Pack the data into the transmit ring. If we
924 * don't have room, set the OACTIVE flag and wait
925 * for the NIC to drain the ring.
927 if (fv_encap(sc, &m_head)) {
930 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
931 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
937 * If there's a BPF listener, bounce a copy of this frame
940 ETHER_BPF_MTAP(ifp, m_head);
944 txstat = (CSR_READ_4(sc, CSR_STATUS) >> 20) & 7;
945 if (txstat == 0 || txstat == 6)
946 CSR_WRITE_4(sc, CSR_TXPOLL, TXPOLL_TPD);
951 fv_stop(struct fv_softc *sc)
958 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
959 callout_stop(&sc->fv_stat_callout);
961 /* Disable interrupts. */
962 CSR_WRITE_4(sc, CSR_INTEN, 0);
964 /* Stop the transmit and receive processes. */
965 CSR_WRITE_4(sc, CSR_OPMODE, 0);
966 CSR_WRITE_4(sc, CSR_RXLIST, 0);
967 CSR_WRITE_4(sc, CSR_TXLIST, 0);
973 fv_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
975 struct fv_softc *sc = ifp->if_softc;
976 struct ifreq *ifr = (struct ifreq *) data;
978 struct mii_data *mii;
986 if (ifp->if_flags & IFF_UP) {
987 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
988 if ((ifp->if_flags ^ sc->fv_if_flags) &
990 csr = CSR_READ_4(sc, CSR_OPMODE);
991 CSR_WRITE_4(sc, CSR_OPMODE, csr |
992 OPMODE_PM | OPMODE_PR);
994 if ((ifp->if_flags ^ sc->fv_if_flags) &
996 csr = CSR_READ_4(sc, CSR_OPMODE);
997 CSR_WRITE_4(sc, CSR_OPMODE, csr |
1001 if (sc->fv_detach == 0)
1005 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1008 sc->fv_if_flags = ifp->if_flags;
1024 mii = device_get_softc(sc->fv_miibus);
1025 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1027 error = ifmedia_ioctl(ifp, ifr, &sc->fv_ifmedia, command);
1033 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1034 if ((mask & IFCAP_HWCSUM) != 0) {
1035 ifp->if_capenable ^= IFCAP_HWCSUM;
1036 if ((IFCAP_HWCSUM & ifp->if_capenable) &&
1037 (IFCAP_HWCSUM & ifp->if_capabilities))
1038 ifp->if_hwassist = FV_CSUM_FEATURES;
1040 ifp->if_hwassist = 0;
1042 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1043 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1044 if (IFCAP_VLAN_HWTAGGING & ifp->if_capenable &&
1045 IFCAP_VLAN_HWTAGGING & ifp->if_capabilities &&
1046 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1052 VLAN_CAPABILITIES(ifp);
1056 error = ether_ioctl(ifp, command, data);
1064 * Set media options.
1067 fv_ifmedia_upd(struct ifnet *ifp)
1070 struct fv_softc *sc;
1071 struct mii_data *mii;
1072 struct mii_softc *miisc;
1077 mii = device_get_softc(sc->fv_miibus);
1078 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1080 error = mii_mediachg(mii);
1090 * Report current media status.
1093 fv_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1096 struct fv_softc *sc = ifp->if_softc;
1097 struct mii_data *mii;
1099 mii = device_get_softc(sc->fv_miibus);
1102 ifmr->ifm_active = mii->mii_media_active;
1103 ifmr->ifm_status = mii->mii_media_status;
1106 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
1110 struct fv_dmamap_arg {
1111 bus_addr_t fv_busaddr;
1115 fv_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1117 struct fv_dmamap_arg *ctx;
1122 ctx->fv_busaddr = segs[0].ds_addr;
1126 fv_dma_alloc(struct fv_softc *sc)
1128 struct fv_dmamap_arg ctx;
1129 struct fv_txdesc *txd;
1130 struct fv_rxdesc *rxd;
1133 /* Create parent DMA tag. */
1134 error = bus_dma_tag_create(
1135 bus_get_dma_tag(sc->fv_dev), /* parent */
1136 1, 0, /* alignment, boundary */
1137 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1138 BUS_SPACE_MAXADDR, /* highaddr */
1139 NULL, NULL, /* filter, filterarg */
1140 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1142 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1144 NULL, NULL, /* lockfunc, lockarg */
1145 &sc->fv_cdata.fv_parent_tag);
1147 device_printf(sc->fv_dev, "failed to create parent DMA tag\n");
1150 /* Create tag for Tx ring. */
1151 error = bus_dma_tag_create(
1152 sc->fv_cdata.fv_parent_tag, /* parent */
1153 FV_RING_ALIGN, 0, /* alignment, boundary */
1154 BUS_SPACE_MAXADDR, /* lowaddr */
1155 BUS_SPACE_MAXADDR, /* highaddr */
1156 NULL, NULL, /* filter, filterarg */
1157 FV_TX_RING_SIZE, /* maxsize */
1159 FV_TX_RING_SIZE, /* maxsegsize */
1161 NULL, NULL, /* lockfunc, lockarg */
1162 &sc->fv_cdata.fv_tx_ring_tag);
1164 device_printf(sc->fv_dev, "failed to create Tx ring DMA tag\n");
1168 /* Create tag for Rx ring. */
1169 error = bus_dma_tag_create(
1170 sc->fv_cdata.fv_parent_tag, /* parent */
1171 FV_RING_ALIGN, 0, /* alignment, boundary */
1172 BUS_SPACE_MAXADDR, /* lowaddr */
1173 BUS_SPACE_MAXADDR, /* highaddr */
1174 NULL, NULL, /* filter, filterarg */
1175 FV_RX_RING_SIZE, /* maxsize */
1177 FV_RX_RING_SIZE, /* maxsegsize */
1179 NULL, NULL, /* lockfunc, lockarg */
1180 &sc->fv_cdata.fv_rx_ring_tag);
1182 device_printf(sc->fv_dev, "failed to create Rx ring DMA tag\n");
1186 /* Create tag for Tx buffers. */
1187 error = bus_dma_tag_create(
1188 sc->fv_cdata.fv_parent_tag, /* parent */
1189 1, 0, /* alignment, boundary */
1190 BUS_SPACE_MAXADDR, /* lowaddr */
1191 BUS_SPACE_MAXADDR, /* highaddr */
1192 NULL, NULL, /* filter, filterarg */
1193 MCLBYTES * FV_MAXFRAGS, /* maxsize */
1194 FV_MAXFRAGS, /* nsegments */
1195 MCLBYTES, /* maxsegsize */
1197 NULL, NULL, /* lockfunc, lockarg */
1198 &sc->fv_cdata.fv_tx_tag);
1200 device_printf(sc->fv_dev, "failed to create Tx DMA tag\n");
1204 /* Create tag for Rx buffers. */
1205 error = bus_dma_tag_create(
1206 sc->fv_cdata.fv_parent_tag, /* parent */
1207 FV_RX_ALIGN, 0, /* alignment, boundary */
1208 BUS_SPACE_MAXADDR, /* lowaddr */
1209 BUS_SPACE_MAXADDR, /* highaddr */
1210 NULL, NULL, /* filter, filterarg */
1211 MCLBYTES, /* maxsize */
1213 MCLBYTES, /* maxsegsize */
1215 NULL, NULL, /* lockfunc, lockarg */
1216 &sc->fv_cdata.fv_rx_tag);
1218 device_printf(sc->fv_dev, "failed to create Rx DMA tag\n");
1222 /* Create tag for setup frame buffers. */
1223 error = bus_dma_tag_create(
1224 sc->fv_cdata.fv_parent_tag, /* parent */
1225 sizeof(uint32_t), 0, /* alignment, boundary */
1226 BUS_SPACE_MAXADDR, /* lowaddr */
1227 BUS_SPACE_MAXADDR, /* highaddr */
1228 NULL, NULL, /* filter, filterarg */
1229 FV_SFRAME_LEN + FV_MIN_FRAMELEN, /* maxsize */
1231 FV_SFRAME_LEN + FV_MIN_FRAMELEN, /* maxsegsize */
1233 NULL, NULL, /* lockfunc, lockarg */
1234 &sc->fv_cdata.fv_sf_tag);
1236 device_printf(sc->fv_dev, "failed to create setup frame DMA tag\n");
1240 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1241 error = bus_dmamem_alloc(sc->fv_cdata.fv_tx_ring_tag,
1242 (void **)&sc->fv_rdata.fv_tx_ring, BUS_DMA_WAITOK |
1243 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fv_cdata.fv_tx_ring_map);
1245 device_printf(sc->fv_dev,
1246 "failed to allocate DMA'able memory for Tx ring\n");
1251 error = bus_dmamap_load(sc->fv_cdata.fv_tx_ring_tag,
1252 sc->fv_cdata.fv_tx_ring_map, sc->fv_rdata.fv_tx_ring,
1253 FV_TX_RING_SIZE, fv_dmamap_cb, &ctx, 0);
1254 if (error != 0 || ctx.fv_busaddr == 0) {
1255 device_printf(sc->fv_dev,
1256 "failed to load DMA'able memory for Tx ring\n");
1259 sc->fv_rdata.fv_tx_ring_paddr = ctx.fv_busaddr;
1261 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1262 error = bus_dmamem_alloc(sc->fv_cdata.fv_rx_ring_tag,
1263 (void **)&sc->fv_rdata.fv_rx_ring, BUS_DMA_WAITOK |
1264 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fv_cdata.fv_rx_ring_map);
1266 device_printf(sc->fv_dev,
1267 "failed to allocate DMA'able memory for Rx ring\n");
1272 error = bus_dmamap_load(sc->fv_cdata.fv_rx_ring_tag,
1273 sc->fv_cdata.fv_rx_ring_map, sc->fv_rdata.fv_rx_ring,
1274 FV_RX_RING_SIZE, fv_dmamap_cb, &ctx, 0);
1275 if (error != 0 || ctx.fv_busaddr == 0) {
1276 device_printf(sc->fv_dev,
1277 "failed to load DMA'able memory for Rx ring\n");
1280 sc->fv_rdata.fv_rx_ring_paddr = ctx.fv_busaddr;
1282 /* Allocate DMA'able memory and load the DMA map for setup frame. */
1283 error = bus_dmamem_alloc(sc->fv_cdata.fv_sf_tag,
1284 (void **)&sc->fv_cdata.fv_sf_buff, BUS_DMA_WAITOK |
1285 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fv_cdata.fv_sf_buff_map);
1287 device_printf(sc->fv_dev,
1288 "failed to allocate DMA'able memory for setup frame\n");
1293 error = bus_dmamap_load(sc->fv_cdata.fv_sf_tag,
1294 sc->fv_cdata.fv_sf_buff_map, sc->fv_cdata.fv_sf_buff,
1295 FV_SFRAME_LEN, fv_dmamap_cb, &ctx, 0);
1296 if (error != 0 || ctx.fv_busaddr == 0) {
1297 device_printf(sc->fv_dev,
1298 "failed to load DMA'able memory for setup frame\n");
1301 sc->fv_rdata.fv_sf_paddr = ctx.fv_busaddr;
1303 /* Create DMA maps for Tx buffers. */
1304 for (i = 0; i < FV_TX_RING_CNT; i++) {
1305 txd = &sc->fv_cdata.fv_txdesc[i];
1307 txd->tx_dmamap = NULL;
1308 error = bus_dmamap_create(sc->fv_cdata.fv_tx_tag, 0,
1311 device_printf(sc->fv_dev,
1312 "failed to create Tx dmamap\n");
1316 /* Create DMA maps for Rx buffers. */
1317 if ((error = bus_dmamap_create(sc->fv_cdata.fv_rx_tag, 0,
1318 &sc->fv_cdata.fv_rx_sparemap)) != 0) {
1319 device_printf(sc->fv_dev,
1320 "failed to create spare Rx dmamap\n");
1323 for (i = 0; i < FV_RX_RING_CNT; i++) {
1324 rxd = &sc->fv_cdata.fv_rxdesc[i];
1326 rxd->rx_dmamap = NULL;
1327 error = bus_dmamap_create(sc->fv_cdata.fv_rx_tag, 0,
1330 device_printf(sc->fv_dev,
1331 "failed to create Rx dmamap\n");
1341 fv_dma_free(struct fv_softc *sc)
1343 struct fv_txdesc *txd;
1344 struct fv_rxdesc *rxd;
1348 if (sc->fv_cdata.fv_tx_ring_tag) {
1349 if (sc->fv_rdata.fv_tx_ring_paddr)
1350 bus_dmamap_unload(sc->fv_cdata.fv_tx_ring_tag,
1351 sc->fv_cdata.fv_tx_ring_map);
1352 if (sc->fv_rdata.fv_tx_ring)
1353 bus_dmamem_free(sc->fv_cdata.fv_tx_ring_tag,
1354 sc->fv_rdata.fv_tx_ring,
1355 sc->fv_cdata.fv_tx_ring_map);
1356 sc->fv_rdata.fv_tx_ring = NULL;
1357 sc->fv_rdata.fv_tx_ring_paddr = 0;
1358 bus_dma_tag_destroy(sc->fv_cdata.fv_tx_ring_tag);
1359 sc->fv_cdata.fv_tx_ring_tag = NULL;
1362 if (sc->fv_cdata.fv_rx_ring_tag) {
1363 if (sc->fv_rdata.fv_rx_ring_paddr)
1364 bus_dmamap_unload(sc->fv_cdata.fv_rx_ring_tag,
1365 sc->fv_cdata.fv_rx_ring_map);
1366 if (sc->fv_rdata.fv_rx_ring)
1367 bus_dmamem_free(sc->fv_cdata.fv_rx_ring_tag,
1368 sc->fv_rdata.fv_rx_ring,
1369 sc->fv_cdata.fv_rx_ring_map);
1370 sc->fv_rdata.fv_rx_ring = NULL;
1371 sc->fv_rdata.fv_rx_ring_paddr = 0;
1372 bus_dma_tag_destroy(sc->fv_cdata.fv_rx_ring_tag);
1373 sc->fv_cdata.fv_rx_ring_tag = NULL;
1376 if (sc->fv_cdata.fv_tx_tag) {
1377 for (i = 0; i < FV_TX_RING_CNT; i++) {
1378 txd = &sc->fv_cdata.fv_txdesc[i];
1379 if (txd->tx_dmamap) {
1380 bus_dmamap_destroy(sc->fv_cdata.fv_tx_tag,
1382 txd->tx_dmamap = NULL;
1385 bus_dma_tag_destroy(sc->fv_cdata.fv_tx_tag);
1386 sc->fv_cdata.fv_tx_tag = NULL;
1389 if (sc->fv_cdata.fv_rx_tag) {
1390 for (i = 0; i < FV_RX_RING_CNT; i++) {
1391 rxd = &sc->fv_cdata.fv_rxdesc[i];
1392 if (rxd->rx_dmamap) {
1393 bus_dmamap_destroy(sc->fv_cdata.fv_rx_tag,
1395 rxd->rx_dmamap = NULL;
1398 if (sc->fv_cdata.fv_rx_sparemap) {
1399 bus_dmamap_destroy(sc->fv_cdata.fv_rx_tag,
1400 sc->fv_cdata.fv_rx_sparemap);
1401 sc->fv_cdata.fv_rx_sparemap = 0;
1403 bus_dma_tag_destroy(sc->fv_cdata.fv_rx_tag);
1404 sc->fv_cdata.fv_rx_tag = NULL;
1407 if (sc->fv_cdata.fv_parent_tag) {
1408 bus_dma_tag_destroy(sc->fv_cdata.fv_parent_tag);
1409 sc->fv_cdata.fv_parent_tag = NULL;
1414 * Initialize the transmit descriptors.
1417 fv_tx_ring_init(struct fv_softc *sc)
1419 struct fv_ring_data *rd;
1420 struct fv_txdesc *txd;
1424 sc->fv_cdata.fv_tx_prod = 0;
1425 sc->fv_cdata.fv_tx_cons = 0;
1426 sc->fv_cdata.fv_tx_cnt = 0;
1427 sc->fv_cdata.fv_tx_pkts = 0;
1430 bzero(rd->fv_tx_ring, FV_TX_RING_SIZE);
1431 for (i = 0; i < FV_TX_RING_CNT; i++) {
1432 if (i == FV_TX_RING_CNT - 1)
1433 addr = FV_TX_RING_ADDR(sc, 0);
1435 addr = FV_TX_RING_ADDR(sc, i + 1);
1436 rd->fv_tx_ring[i].fv_stat = 0;
1437 rd->fv_tx_ring[i].fv_devcs = 0;
1438 rd->fv_tx_ring[i].fv_addr = 0;
1439 rd->fv_tx_ring[i].fv_link = addr;
1440 txd = &sc->fv_cdata.fv_txdesc[i];
1444 bus_dmamap_sync(sc->fv_cdata.fv_tx_ring_tag,
1445 sc->fv_cdata.fv_tx_ring_map,
1446 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1452 * Initialize the RX descriptors and allocate mbufs for them. Note that
1453 * we arrange the descriptors in a closed ring, so that the last descriptor
1454 * points back to the first.
1457 fv_rx_ring_init(struct fv_softc *sc)
1459 struct fv_ring_data *rd;
1460 struct fv_rxdesc *rxd;
1463 sc->fv_cdata.fv_rx_cons = 0;
1466 bzero(rd->fv_rx_ring, FV_RX_RING_SIZE);
1467 for (i = 0; i < FV_RX_RING_CNT; i++) {
1468 rxd = &sc->fv_cdata.fv_rxdesc[i];
1470 rxd->desc = &rd->fv_rx_ring[i];
1471 rd->fv_rx_ring[i].fv_stat = ADSTAT_OWN;
1472 rd->fv_rx_ring[i].fv_devcs = 0;
1473 if (i == FV_RX_RING_CNT - 1)
1474 rd->fv_rx_ring[i].fv_devcs |= ADCTL_ER;
1475 rd->fv_rx_ring[i].fv_addr = 0;
1476 if (fv_newbuf(sc, i) != 0)
1480 bus_dmamap_sync(sc->fv_cdata.fv_rx_ring_tag,
1481 sc->fv_cdata.fv_rx_ring_map,
1482 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1488 * Initialize an RX descriptor and attach an MBUF cluster.
1491 fv_newbuf(struct fv_softc *sc, int idx)
1493 struct fv_desc *desc;
1494 struct fv_rxdesc *rxd;
1496 bus_dma_segment_t segs[1];
1500 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1503 m->m_len = m->m_pkthdr.len = MCLBYTES;
1505 /* tcp header boundary alignment margin */
1508 if (bus_dmamap_load_mbuf_sg(sc->fv_cdata.fv_rx_tag,
1509 sc->fv_cdata.fv_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1513 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1515 rxd = &sc->fv_cdata.fv_rxdesc[idx];
1516 if (rxd->rx_m != NULL) {
1517 /* This code make bug. Make scranble on buffer data.
1518 bus_dmamap_sync(sc->fv_cdata.fv_rx_tag, rxd->rx_dmamap,
1519 BUS_DMASYNC_POSTREAD);
1521 bus_dmamap_unload(sc->fv_cdata.fv_rx_tag, rxd->rx_dmamap);
1523 map = rxd->rx_dmamap;
1524 rxd->rx_dmamap = sc->fv_cdata.fv_rx_sparemap;
1525 sc->fv_cdata.fv_rx_sparemap = map;
1526 bus_dmamap_sync(sc->fv_cdata.fv_rx_tag, rxd->rx_dmamap,
1527 BUS_DMASYNC_PREREAD);
1530 desc->fv_addr = segs[0].ds_addr;
1531 desc->fv_devcs |= FV_DMASIZE(segs[0].ds_len);
1532 rxd->saved_ca = desc->fv_addr ;
1533 rxd->saved_ctl = desc->fv_stat ;
1538 static __inline void
1539 fv_fixup_rx(struct mbuf *m)
1542 uint16_t *src, *dst;
1544 src = mtod(m, uint16_t *);
1547 for (i = 0; i < m->m_len / sizeof(uint16_t); i++) {
1551 if (m->m_len % sizeof(uint16_t))
1552 *(uint8_t *)dst = *(uint8_t *)src;
1554 m->m_data -= ETHER_ALIGN;
1559 fv_tx(struct fv_softc *sc)
1561 struct fv_txdesc *txd;
1562 struct fv_desc *cur_tx;
1564 uint32_t ctl, devcs;
1565 int cons, prod, prev_cons;
1569 cons = sc->fv_cdata.fv_tx_cons;
1570 prod = sc->fv_cdata.fv_tx_prod;
1574 bus_dmamap_sync(sc->fv_cdata.fv_tx_ring_tag,
1575 sc->fv_cdata.fv_tx_ring_map,
1576 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1580 * Go through our tx list and free mbufs for those
1581 * frames that have been transmitted.
1584 for (; cons != prod; FV_INC(cons, FV_TX_RING_CNT)) {
1585 cur_tx = &sc->fv_rdata.fv_tx_ring[cons];
1586 ctl = cur_tx->fv_stat;
1587 devcs = cur_tx->fv_devcs;
1588 /* Check if descriptor has "finished" flag */
1589 if (FV_DMASIZE(devcs) == 0)
1592 sc->fv_cdata.fv_tx_cnt--;
1593 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1595 txd = &sc->fv_cdata.fv_txdesc[cons];
1597 if ((ctl & ADSTAT_Tx_ES) == 0)
1598 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1599 else if (ctl & ADSTAT_Tx_UF) { /* only underflow not check collision */
1600 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1603 bus_dmamap_sync(sc->fv_cdata.fv_tx_tag, txd->tx_dmamap,
1604 BUS_DMASYNC_POSTWRITE);
1605 bus_dmamap_unload(sc->fv_cdata.fv_tx_tag, txd->tx_dmamap);
1607 /* Free only if it's first descriptor in list */
1612 /* reset descriptor */
1613 cur_tx->fv_stat = 0;
1614 cur_tx->fv_devcs = 0;
1615 cur_tx->fv_addr = 0;
1618 sc->fv_cdata.fv_tx_cons = cons;
1620 bus_dmamap_sync(sc->fv_cdata.fv_tx_ring_tag,
1621 sc->fv_cdata.fv_tx_ring_map, BUS_DMASYNC_PREWRITE);
1626 fv_rx(struct fv_softc *sc)
1628 struct fv_rxdesc *rxd;
1629 struct ifnet *ifp = sc->fv_ifp;
1630 int cons, prog, packet_len, error;
1631 struct fv_desc *cur_rx;
1636 cons = sc->fv_cdata.fv_rx_cons;
1638 bus_dmamap_sync(sc->fv_cdata.fv_rx_ring_tag,
1639 sc->fv_cdata.fv_rx_ring_map,
1640 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1642 for (prog = 0; prog < FV_RX_RING_CNT; FV_INC(cons, FV_RX_RING_CNT)) {
1643 cur_rx = &sc->fv_rdata.fv_rx_ring[cons];
1644 rxd = &sc->fv_cdata.fv_rxdesc[cons];
1647 if ((cur_rx->fv_stat & ADSTAT_OWN) == ADSTAT_OWN)
1652 if (cur_rx->fv_stat & (ADSTAT_ES | ADSTAT_Rx_TL)) {
1653 device_printf(sc->fv_dev,
1654 "Receive Descriptor error %x\n", cur_rx->fv_stat);
1655 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1658 packet_len = ADSTAT_Rx_LENGTH(cur_rx->fv_stat);
1661 /* Assume it's error */
1664 if (packet_len < 64)
1665 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1666 else if ((cur_rx->fv_stat & ADSTAT_Rx_DE) == 0) {
1668 bus_dmamap_sync(sc->fv_cdata.fv_rx_tag, rxd->rx_dmamap,
1669 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1671 /* Skip 4 bytes of CRC */
1672 m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
1675 m->m_pkthdr.rcvif = ifp;
1676 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1679 (*ifp->if_input)(ifp, m);
1684 /* Restore CONTROL and CA values, reset DEVCS */
1685 cur_rx->fv_stat = rxd->saved_ctl;
1686 cur_rx->fv_addr = rxd->saved_ca;
1687 cur_rx->fv_devcs = 0;
1690 /* Reinit descriptor */
1691 cur_rx->fv_stat = ADSTAT_OWN;
1692 cur_rx->fv_devcs = 0;
1693 if (cons == FV_RX_RING_CNT - 1)
1694 cur_rx->fv_devcs |= ADCTL_ER;
1695 cur_rx->fv_addr = 0;
1696 if (fv_newbuf(sc, cons) != 0) {
1697 device_printf(sc->fv_dev,
1698 "Failed to allocate buffer\n");
1703 bus_dmamap_sync(sc->fv_cdata.fv_rx_ring_tag,
1704 sc->fv_cdata.fv_rx_ring_map,
1705 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1710 sc->fv_cdata.fv_rx_cons = cons;
1712 bus_dmamap_sync(sc->fv_cdata.fv_rx_ring_tag,
1713 sc->fv_cdata.fv_rx_ring_map,
1714 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1721 struct fv_softc *sc = arg;
1723 struct ifnet *ifp = sc->fv_ifp;
1727 status = CSR_READ_4(sc, CSR_STATUS);
1728 /* mask out interrupts */
1729 while((status & sc->sc_inten) != 0) {
1731 CSR_WRITE_4(sc, CSR_STATUS, status);
1733 if (status & STATUS_UNF) {
1734 device_printf(sc->fv_dev, "Transmit Underflow\n");
1736 if (status & sc->sc_rxint_mask) {
1739 if (status & sc->sc_txint_mask) {
1742 if (status & STATUS_AIS) {
1743 device_printf(sc->fv_dev, "Abnormal Interrupt %x\n",
1746 CSR_WRITE_4(sc, CSR_FULLDUP, FULLDUP_CS |
1747 (1 << FULLDUP_TT_SHIFT) | (3 << FULLDUP_NTP_SHIFT) |
1748 (2 << FULLDUP_RT_SHIFT) | (2 << FULLDUP_NRP_SHIFT));
1751 status = CSR_READ_4(sc, CSR_STATUS);
1754 /* Try to get more packets going. */
1755 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1756 fv_start_locked(ifp);
1764 struct fv_softc *sc = xsc;
1766 struct mii_data *mii;
1770 mii = device_get_softc(sc->fv_miibus);
1773 callout_reset(&sc->fv_stat_callout, hz, fv_tick, sc);
1777 fv_hinted_child(device_t bus, const char *dname, int dunit)
1779 BUS_ADD_CHILD(bus, 0, dname, dunit);
1780 device_printf(bus, "hinted child %s%d\n", dname, dunit);
1785 fvmdio_probe(device_t dev)
1787 if (!ofw_bus_status_okay(dev))
1790 if (!ofw_bus_is_compatible(dev, "fv,mdio"))
1793 device_set_desc(dev, "FV built-in ethernet interface, MDIO controller");
1798 fvmdio_attach(device_t dev)
1800 struct fv_softc *sc;
1803 sc = device_get_softc(dev);
1806 sc->fv_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1807 &sc->fv_rid, RF_ACTIVE | RF_SHAREABLE);
1808 if (sc->fv_res == NULL) {
1809 device_printf(dev, "couldn't map memory\n");
1814 sc->fv_btag = rman_get_bustag(sc->fv_res);
1815 sc->fv_bhandle = rman_get_bushandle(sc->fv_res);
1817 bus_generic_probe(dev);
1818 bus_enumerate_hinted_children(dev);
1819 error = bus_generic_attach(dev);
1825 fvmdio_detach(device_t dev)
1833 dump_txdesc(struct fv_softc *sc, int pos)
1835 struct fv_desc *desc;
1837 desc = &sc->fv_rdata.fv_tx_ring[pos];
1838 device_printf(sc->fv_dev, "CSR_TXLIST %08x\n", CSR_READ_4(sc, CSR_TXLIST));
1839 device_printf(sc->fv_dev, "%d TDES0:%08x TDES1:%08x TDES2:%08x TDES3:%08x\n",
1840 pos, desc->fv_stat, desc->fv_devcs, desc->fv_addr, desc->fv_link);
1844 dump_status_reg(struct fv_softc *sc)
1848 /* mask out interrupts */
1850 status = CSR_READ_4(sc, CSR_STATUS);
1851 device_printf(sc->fv_dev, "CSR5 Status Register EB:%d TS:%d RS:%d NIS:%d AIS:%d ER:%d SE:%d LNF:%d TM:%d RWT:%d RPS:%d RU:%d RI:%d UNF:%d LNP/ANC:%d TJT:%d TU:%d TPS:%d TI:%d\n",
1852 (status >> 23 ) & 7,
1853 (status >> 20 ) & 7,
1854 (status >> 17 ) & 7,
1855 (status >> 16 ) & 1,
1856 (status >> 15 ) & 1,
1857 (status >> 14 ) & 1,
1858 (status >> 13 ) & 1,
1859 (status >> 12 ) & 1,
1860 (status >> 11 ) & 1,
1870 (status >> 0 ) & 1);