sys/arm/ralink/rt1310_intc.c

   1 /*-
   2  * Copyright (c) 2010 Jakub Wojciech Klama <jceel@FreeBSD.org>
   3  * Copyright (c) 2015 Hiroki Mori
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include "opt_platform.h"
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/types.h>
  38 #include <sys/kernel.h>
  39 #include <sys/malloc.h>
  40 #include <sys/module.h>
  41 #include <sys/proc.h>
  42 #include <sys/rman.h>
  43 #include <vm/vm.h>
  44 #include <vm/vm_kern.h>
  45 #include <vm/pmap.h>
  46 #include <vm/vm_page.h>
  47 #include <vm/vm_extern.h>
  48
  49 #define _ARM32_BUS_DMA_PRIVATE
  50 #include <machine/bus.h>
  51 #include <machine/intr.h>
  52
  53 #include <dev/fdt/fdt_common.h>
  54 #include <dev/ofw/openfirm.h>
  55
  56 #include <dev/ofw/ofw_bus.h>
  57 #include <dev/ofw/ofw_bus_subr.h>
  58
  59 #include <arm/ralink/rt1310reg.h>
  60
  61 #define INTC_NIRQS      32
  62
  63 #ifdef INTRNG
  64 #include "pic_if.h"
  65
  66 struct rt1310_irqsrc {
  67         struct intr_irqsrc      ri_isrc;
  68         u_int                   ri_irq;
  69 };
  70 #endif
  71
  72 struct rt1310_intc_softc {
  73         device_t dev;
  74         struct resource *       ri_res;
  75         bus_space_tag_t         ri_bst;
  76         bus_space_handle_t      ri_bsh;
  77 #ifdef INTRNG
  78         struct rt1310_irqsrc    ri_isrcs[INTC_NIRQS];
  79 #endif
  80 };
  81
  82 static int rt1310_intc_probe(device_t);
  83 static int rt1310_intc_attach(device_t);
  84 #ifndef INTRNG
  85 static void rt1310_intc_eoi(void *);
  86 #else
  87 static int rt1310_pic_attach(struct rt1310_intc_softc *sc);
  88 #endif
  89
  90 static struct rt1310_intc_softc *intc_softc = NULL;
  91
  92 #define intc_read_4(_sc, _reg)          \
  93     bus_space_read_4((_sc)->ri_bst, (_sc)->ri_bsh, (_reg))
  94 #define intc_write_4(_sc, _reg, _val)           \
  95     bus_space_write_4((_sc)->ri_bst, (_sc)->ri_bsh, (_reg), (_val))
  96
  97 struct rt1310_irqdef {
  98         u_int                   ri_trig;
  99         u_int                   ri_prio;
 100 };
 101
 102 struct rt1310_irqdef irqdef[INTC_NIRQS] = {
 103         {RT_INTC_TRIG_HIGH_LVL, 2},     /* 0 */
 104         {RT_INTC_TRIG_HIGH_LVL, 2},
 105         {RT_INTC_TRIG_HIGH_LVL, 2},
 106         {RT_INTC_TRIG_HIGH_LVL, 1},
 107         {RT_INTC_TRIG_HIGH_LVL, 2},
 108         {RT_INTC_TRIG_HIGH_LVL, 1},
 109         {RT_INTC_TRIG_HIGH_LVL, 1},
 110         {RT_INTC_TRIG_HIGH_LVL, 1},
 111         {RT_INTC_TRIG_HIGH_LVL, 1},     /* 8 */
 112         {RT_INTC_TRIG_HIGH_LVL, 1},
 113         {RT_INTC_TRIG_HIGH_LVL, 2},
 114         {RT_INTC_TRIG_LOW_LVL, 2},
 115         {RT_INTC_TRIG_LOW_LVL, 2},
 116         {RT_INTC_TRIG_LOW_LVL, 4},
 117         {RT_INTC_TRIG_HIGH_LVL, 2},
 118         {RT_INTC_TRIG_HIGH_LVL, 2},
 119         {RT_INTC_TRIG_HIGH_LVL, 2},     /* 16 */
 120         {RT_INTC_TRIG_HIGH_LVL, 2},
 121         {RT_INTC_TRIG_LOW_LVL, 2},
 122         {RT_INTC_TRIG_LOW_LVL, 2},
 123         {RT_INTC_TRIG_LOW_LVL, 2},
 124         {RT_INTC_TRIG_LOW_LVL, 2},
 125         {RT_INTC_TRIG_NEG_EDGE, 2},
 126         {RT_INTC_TRIG_HIGH_LVL, 3},
 127         {RT_INTC_TRIG_HIGH_LVL, 2},     /* 24 */
 128         {RT_INTC_TRIG_POS_EDGE, 2},
 129         {RT_INTC_TRIG_POS_EDGE, 2},
 130         {RT_INTC_TRIG_HIGH_LVL, 2},
 131         {RT_INTC_TRIG_HIGH_LVL, 2},
 132         {RT_INTC_TRIG_POS_EDGE, 2},
 133         {RT_INTC_TRIG_POS_EDGE, 3},
 134         {RT_INTC_TRIG_POS_EDGE, 3},
 135 };
 136
 137 static int
 138 rt1310_intc_probe(device_t dev)
 139 {
 140         if (!ofw_bus_status_okay(dev))
 141                 return (ENXIO);
 142
 143         if (!ofw_bus_is_compatible(dev, "rt,pic"))
 144                 return (ENXIO);
 145
 146 #ifdef INTRNG
 147         device_set_desc(dev, "RT1310 INTRNG Interrupt Controller");
 148 #else
 149         device_set_desc(dev, "RT1310 Interrupt Controller");
 150 #endif
 151         return (BUS_PROBE_DEFAULT);
 152 }
 153
 154 static int
 155 rt1310_intc_attach(device_t dev)
 156 {
 157         struct rt1310_intc_softc *sc = device_get_softc(dev);
 158         int rid = 0;
 159         int i;
 160
 161         if (intc_softc)
 162                 return (ENXIO);
 163
 164         sc->dev = dev;
 165
 166         sc->ri_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 167             RF_ACTIVE);
 168         if (!sc->ri_res) {
 169                 device_printf(dev, "could not alloc resources\n");
 170                 return (ENXIO);
 171         }
 172
 173         sc->ri_bst = rman_get_bustag(sc->ri_res);
 174         sc->ri_bsh = rman_get_bushandle(sc->ri_res);
 175         intc_softc = sc;
 176 #ifndef INTRNG
 177         arm_post_filter = rt1310_intc_eoi;
 178 #else
 179         rt1310_pic_attach(sc);
 180 #endif
 181
 182         intc_write_4(sc, RT_INTC_IECR, 0);
 183         intc_write_4(sc, RT_INTC_ICCR, ~0);
 184
 185         for (i = 0; i <= INTC_NIRQS; ++i) {
 186                 intc_write_4(sc, RT_INTC_SCR0+i*4,
 187                         (irqdef[i].ri_trig << RT_INTC_TRIG_SHIF) |
 188                         irqdef[i].ri_prio);
 189                 intc_write_4(sc, RT_INTC_SVR0+i*4, i);
 190         }
 191
 192         /* Clear interrupt status registers and disable all interrupts */
 193         intc_write_4(sc, RT_INTC_ICCR, ~0);
 194         intc_write_4(sc, RT_INTC_IMR, 0);
 195         return (0);
 196 }
 197
 198 #ifndef INTRNG
 199 int
 200 arm_get_next_irq(int last)
 201 {
 202         struct rt1310_intc_softc *sc = intc_softc;
 203         uint32_t value;
 204         int i;
 205         value = intc_read_4(sc, RT_INTC_IPR);
 206         for (i = 0; i < 32; i++) {
 207                 if (value & (1 << i))
 208                         return (i);
 209         }
 210
 211         return (-1);
 212 }
 213
 214 void
 215 arm_mask_irq(uintptr_t nb)
 216 {
 217         struct rt1310_intc_softc *sc = intc_softc;
 218         uint32_t value;
 219
 220         /* Make sure that interrupt isn't active already */
 221         rt1310_intc_eoi((void *)nb);
 222
 223         /* Clear bit in ER register */
 224         value = intc_read_4(sc, RT_INTC_IECR);
 225         value &= ~(1 << nb);
 226         intc_write_4(sc, RT_INTC_IECR, value);
 227         intc_write_4(sc, RT_INTC_IMR, value);
 228
 229         intc_write_4(sc, RT_INTC_ICCR, 1 << nb);
 230 }
 231
 232 void
 233 arm_unmask_irq(uintptr_t nb)
 234 {
 235         struct rt1310_intc_softc *sc = intc_softc;
 236         uint32_t value;
 237
 238         value = intc_read_4(sc, RT_INTC_IECR);
 239
 240         value |= (1 << nb);
 241
 242         intc_write_4(sc, RT_INTC_IMR, value);
 243         intc_write_4(sc, RT_INTC_IECR, value);
 244 }
 245
 246 static void
 247 rt1310_intc_eoi(void *data)
 248 {
 249         struct rt1310_intc_softc *sc = intc_softc;
 250         int nb = (int)data;
 251
 252         intc_write_4(sc, RT_INTC_ICCR, 1 << nb);
 253         if (nb == 0) {
 254                 uint32_t value;
 255                 value = intc_read_4(sc, RT_INTC_IECR);
 256                 value &= ~(1 << nb);
 257                 intc_write_4(sc, RT_INTC_IECR, value);
 258                 intc_write_4(sc, RT_INTC_IMR, value);
 259         }
 260 }
 261
 262 #else
 263
 264 static void
 265 rt1310_enable_intr(device_t dev, struct intr_irqsrc *isrc)
 266 {
 267         u_int irq;
 268         unsigned int value;
 269         struct rt1310_intc_softc *sc;
 270
 271         sc = intc_softc;
 272         irq = ((struct rt1310_irqsrc *)isrc)->ri_irq;
 273
 274         value = intc_read_4(sc, RT_INTC_IECR);
 275
 276         value |= (1 << irq);
 277
 278         intc_write_4(sc, RT_INTC_IMR, value);
 279         intc_write_4(sc, RT_INTC_IECR, value);
 280 }
 281
 282 static void
 283 rt1310_disable_intr(device_t dev, struct intr_irqsrc *isrc)
 284 {
 285         u_int irq;
 286         unsigned int value;
 287         struct rt1310_intc_softc *sc;
 288
 289         sc = intc_softc;
 290         irq = ((struct rt1310_irqsrc *)isrc)->ri_irq;
 291
 292         /* Clear bit in ER register */
 293         value = intc_read_4(sc, RT_INTC_IECR);
 294         value &= ~(1 << irq);
 295         intc_write_4(sc, RT_INTC_IECR, value);
 296         intc_write_4(sc, RT_INTC_IMR, value);
 297
 298         intc_write_4(sc, RT_INTC_ICCR, 1 << irq);
 299 }
 300
 301 static int
 302 rt1310_map_intr(device_t dev, struct intr_map_data *data,
 303     struct intr_irqsrc **isrcp)
 304 {
 305         struct intr_map_data_fdt *daf;
 306         struct rt1310_intc_softc *sc;
 307
 308         if (data->type != INTR_MAP_DATA_FDT)
 309                 return (ENOTSUP);
 310
 311         daf = (struct intr_map_data_fdt *)data;
 312
 313         if (daf->ncells != 1 || daf->cells[0] >= INTC_NIRQS)
 314                 return (EINVAL);
 315
 316         sc = device_get_softc(dev);
 317         *isrcp = &sc->ri_isrcs[daf->cells[0]].ri_isrc;
 318         return (0);
 319 }
 320
 321 static void
 322 rt1310_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
 323 {
 324         arm_irq_memory_barrier(0);
 325         rt1310_disable_intr(dev, isrc);
 326 }
 327
 328 static void
 329 rt1310_post_ithread(device_t dev, struct intr_irqsrc *isrc)
 330 {
 331         arm_irq_memory_barrier(0);
 332         rt1310_enable_intr(dev, isrc);
 333 }
 334
 335 static void
 336 rt1310_post_filter(device_t dev, struct intr_irqsrc *isrc)
 337 {
 338         u_int irq;
 339         struct rt1310_intc_softc *sc;
 340
 341         arm_irq_memory_barrier(0);
 342         sc = intc_softc;
 343         irq = ((struct rt1310_irqsrc *)isrc)->ri_irq;
 344
 345         intc_write_4(sc, RT_INTC_ICCR, 1 << irq);
 346 }
 347
 348 static int
 349 rt1310_intr(void *arg)
 350 {
 351         uint32_t irq;
 352         struct rt1310_intc_softc *sc = arg;
 353
 354         irq = ffs(intc_read_4(sc, RT_INTC_IPR)) - 1;
 355
 356         if (intr_isrc_dispatch(&sc->ri_isrcs[irq].ri_isrc,
 357             curthread->td_intr_frame) != 0) {
 358                 intc_write_4(sc, RT_INTC_ICCR, 1 << irq);
 359                 device_printf(sc->dev, "Stray irq %u disabled\n", irq);
 360         }
 361
 362         arm_irq_memory_barrier(0);
 363
 364         return (FILTER_HANDLED);
 365 }
 366
 367 static int
 368 rt1310_pic_attach(struct rt1310_intc_softc *sc)
 369 {
 370         struct intr_pic *pic;
 371         int error;
 372         uint32_t irq;
 373         const char *name;
 374         intptr_t xref;
 375
 376         name = device_get_nameunit(sc->dev);
 377         for (irq = 0; irq < INTC_NIRQS; irq++) {
 378                 sc->ri_isrcs[irq].ri_irq = irq;
 379
 380                 error = intr_isrc_register(&sc->ri_isrcs[irq].ri_isrc,
 381                     sc->dev, 0, "%s,%u", name, irq);
 382                 if (error != 0)
 383                         return (error);
 384         }
 385
 386         xref = OF_xref_from_node(ofw_bus_get_node(sc->dev));
 387         pic = intr_pic_register(sc->dev, xref);
 388         if (pic == NULL)
 389                 return (ENXIO);
 390
 391         return (intr_pic_claim_root(sc->dev, xref, rt1310_intr, sc, 0));
 392 }
 393 #endif
 394
 395 struct fdt_fixup_entry fdt_fixup_table[] = {
 396         { NULL, NULL }
 397 };
 398
 399 #ifndef INTRNG
 400 static int
 401 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
 402     int *pol)
 403 {
 404         if (!fdt_is_compatible(node, "lpc,pic"))
 405                 return (ENXIO);
 406
 407         *interrupt = fdt32_to_cpu(intr[0]);
 408         *trig = INTR_TRIGGER_CONFORM;
 409         *pol = INTR_POLARITY_CONFORM;
 410         return (0);
 411 }
 412
 413 fdt_pic_decode_t fdt_pic_table[] = {
 414         &fdt_pic_decode_ic,
 415         NULL
 416 };
 417 #endif
 418
 419 static device_method_t rt1310_intc_methods[] = {
 420         DEVMETHOD(device_probe,         rt1310_intc_probe),
 421         DEVMETHOD(device_attach,        rt1310_intc_attach),
 422 #ifdef INTRNG
 423         DEVMETHOD(pic_disable_intr,     rt1310_disable_intr),
 424         DEVMETHOD(pic_enable_intr,      rt1310_enable_intr),
 425         DEVMETHOD(pic_map_intr,         rt1310_map_intr),
 426         DEVMETHOD(pic_post_filter,      rt1310_post_filter),
 427         DEVMETHOD(pic_post_ithread,     rt1310_post_ithread),
 428         DEVMETHOD(pic_pre_ithread,      rt1310_pre_ithread),
 429 #endif
 430         { 0, 0 }
 431 };
 432
 433 static driver_t rt1310_intc_driver = {
 434         "pic",
 435         rt1310_intc_methods,
 436         sizeof(struct rt1310_intc_softc),
 437 };
 438
 439 static devclass_t rt1310_intc_devclass;
 440
 441 EARLY_DRIVER_MODULE(pic, simplebus, rt1310_intc_driver, rt1310_intc_devclass, 0, 0, BUS_PASS_INTERRUPT);