2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Samsung Exynos 5 Inter-Integrated Circuit (I2C)
29 * Chapter 13, Exynos 5 Dual User's Manual Public Rev 1.00
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/malloc.h>
42 #include <sys/timeet.h>
43 #include <sys/timetc.h>
45 #include <dev/iicbus/iiconf.h>
46 #include <dev/iicbus/iicbus.h>
48 #include "iicbus_if.h"
50 #include <dev/ofw/openfirm.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
54 #include <machine/bus.h>
55 #include <machine/cpu.h>
56 #include <machine/intr.h>
58 #include <arm/samsung/exynos/exynos5_common.h>
60 #define I2CCON 0x00 /* Control register */
61 #define ACKGEN (1 << 7) /* Acknowledge Enable */
63 * Source Clock of I2C-bus Transmit Clock Prescaler
65 * 0 = I2CCLK = fPCLK/16
66 * 1 = I2CCLK = fPCLK/512
68 #define I2CCLK (1 << 6)
69 #define IRQ_EN (1 << 5) /* Tx/Rx Interrupt Enable/Disable */
70 #define IPEND (1 << 4) /* Tx/Rx Interrupt Pending Flag */
71 #define CLKVAL_M 0xf /* Transmit Clock Prescaler Mask */
73 #define I2CSTAT 0x04 /* Control/status register */
74 #define I2CMODE_M 0x3 /* Master/Slave Tx/Rx Mode Select */
76 #define I2CMODE_SR 0x0 /* Slave Receive Mode */
77 #define I2CMODE_ST 0x1 /* Slave Transmit Mode */
78 #define I2CMODE_MR 0x2 /* Master Receive Mode */
79 #define I2CMODE_MT 0x3 /* Master Transmit Mode */
80 #define I2CSTAT_BSY (1 << 5) /* Busy Signal Status bit */
81 #define I2C_START_STOP (1 << 5) /* Busy Signal Status bit */
82 #define RXTX_EN (1 << 4) /* Data Output Enable/Disable */
83 #define ARBST (1 << 3) /* Arbitration status flag */
84 #define ADDAS (1 << 2) /* Address-as-slave Status Flag */
85 #define ADDZERO (1 << 1) /* Address Zero Status Flag */
86 #define ACKRECVD (1 << 0) /* Last-received Bit Status Flag */
87 #define I2CADD 0x08 /* Address register */
88 #define I2CDS 0x0C /* Transmit/receive data shift */
89 #define I2CLC 0x10 /* Multi-master line control */
90 #define FILTER_EN (1 << 2) /* Filter Enable bit */
91 #define SDAOUT_DELAY_M 0x3 /* SDA Line Delay Length */
92 #define SDAOUT_DELAY_S 0
95 #define DPRINTF(fmt, args...) \
98 #define DPRINTF(fmt, args...)
101 static int i2c_start(device_t, u_char, int);
102 static int i2c_stop(device_t);
103 static int i2c_reset(device_t, u_char, u_char, u_char *);
104 static int i2c_read(device_t, char *, int, int *, int, int);
105 static int i2c_write(device_t, const char *, int, int *, int);
108 struct resource *res[2];
110 bus_space_handle_t bsh;
118 static struct resource_spec i2c_spec[] = {
119 { SYS_RES_MEMORY, 0, RF_ACTIVE },
120 { SYS_RES_IRQ, 0, RF_ACTIVE },
125 i2c_probe(device_t dev)
128 if (!ofw_bus_status_okay(dev))
131 if (!ofw_bus_is_compatible(dev, "exynos,i2c"))
134 device_set_desc(dev, "Samsung Exynos 5 I2C controller");
135 return (BUS_PROBE_DEFAULT);
139 clear_ipend(struct i2c_softc *sc)
143 reg = READ1(sc, I2CCON);
145 WRITE1(sc, I2CCON, reg);
151 i2c_attach(device_t dev)
153 struct i2c_softc *sc;
156 sc = device_get_softc(dev);
159 mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF);
161 if (bus_alloc_resources(dev, i2c_spec, sc->res)) {
162 device_printf(dev, "could not allocate resources\n");
166 /* Memory interface */
167 sc->bst = rman_get_bustag(sc->res[0]);
168 sc->bsh = rman_get_bushandle(sc->res[0]);
170 sc->iicbus = device_add_child(dev, "iicbus", -1);
171 if (sc->iicbus == NULL) {
172 device_printf(dev, "could not add iicbus child");
173 mtx_destroy(&sc->mutex);
177 WRITE1(sc, I2CSTAT, 0);
178 WRITE1(sc, I2CADD, 0x00);
182 reg |= (I2CMODE_MT << I2CMODE_S);
183 WRITE1(sc, I2CSTAT, reg);
185 bus_generic_attach(dev);
191 wait_for_iif(struct i2c_softc *sc)
198 reg = READ1(sc, I2CCON);
205 return (IIC_ETIMEOUT);
209 wait_for_nibb(struct i2c_softc *sc)
215 if ((READ1(sc, I2CSTAT) & I2CSTAT_BSY) == 0)
220 return (IIC_ETIMEOUT);
224 is_ack(struct i2c_softc *sc)
228 stat = READ1(sc, I2CSTAT);
238 i2c_start(device_t dev, u_char slave, int timeout)
240 struct i2c_softc *sc;
244 sc = device_get_softc(dev);
246 DPRINTF("i2c start\n");
248 mtx_lock(&sc->mutex);
251 DPRINTF("I2CCON == 0x%08x\n", READ1(sc, I2CCON));
252 DPRINTF("I2CSTAT == 0x%08x\n", READ1(sc, I2CSTAT));
263 error = wait_for_nibb(sc);
265 mtx_unlock(&sc->mutex);
266 DPRINTF("cant i2c start: IIC_EBUSERR\n");
267 return (IIC_EBUSERR);
270 reg = READ1(sc, I2CCON);
271 reg |= (IRQ_EN | ACKGEN);
272 WRITE1(sc, I2CCON, reg);
274 WRITE1(sc, I2CDS, slave);
278 reg |= I2C_START_STOP;
279 reg |= (I2CMODE_MT << I2CMODE_S);
280 WRITE1(sc, I2CSTAT, reg);
282 error = wait_for_iif(sc);
284 DPRINTF("cant i2c start: iif error\n");
286 mtx_unlock(&sc->mutex);
291 DPRINTF("cant i2c start: no ack\n");
293 mtx_unlock(&sc->mutex);
297 mtx_unlock(&sc->mutex);
302 i2c_stop(device_t dev)
304 struct i2c_softc *sc;
308 sc = device_get_softc(dev);
310 DPRINTF("i2c stop\n");
312 mtx_lock(&sc->mutex);
314 reg = READ1(sc, I2CSTAT);
315 int mode = (reg >> I2CMODE_S) & I2CMODE_M;
318 reg |= (mode << I2CMODE_S);
319 WRITE1(sc, I2CSTAT, reg);
323 error = wait_for_nibb(sc);
325 DPRINTF("cant i2c stop: nibb error\n");
329 mtx_unlock(&sc->mutex);
334 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
336 struct i2c_softc *sc;
338 sc = device_get_softc(dev);
340 DPRINTF("i2c reset\n");
342 mtx_lock(&sc->mutex);
346 mtx_unlock(&sc->mutex);
352 i2c_read(device_t dev, char *buf, int len,
353 int *read, int last, int delay)
355 struct i2c_softc *sc;
360 sc = device_get_softc(dev);
362 DPRINTF("i2c read\n");
365 reg |= (I2CMODE_MR << I2CMODE_S);
366 reg |= I2C_START_STOP;
367 WRITE1(sc, I2CSTAT, reg);
370 mtx_lock(&sc->mutex);
374 error = wait_for_iif(sc);
376 DPRINTF("cant i2c read: iif error\n");
377 mtx_unlock(&sc->mutex);
383 while (*read < len) {
385 /* Do not ack last read */
386 if (*read == (len - 1)) {
387 reg = READ1(sc, I2CCON);
389 WRITE1(sc, I2CCON, reg);
394 error = wait_for_iif(sc);
396 DPRINTF("cant i2c read: iif error\n");
397 mtx_unlock(&sc->mutex);
401 d = READ1(sc, I2CDS);
402 DPRINTF("0x%02x ", d);
408 mtx_unlock(&sc->mutex);
413 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
415 struct i2c_softc *sc;
418 sc = device_get_softc(dev);
420 DPRINTF("i2c write\n");
424 mtx_lock(&sc->mutex);
427 while (*sent < len) {
429 DPRINTF("0x%02x ", d);
431 WRITE1(sc, I2CDS, d);
436 error = wait_for_iif(sc);
438 DPRINTF("cant i2c write: iif error\n");
439 mtx_unlock(&sc->mutex);
444 DPRINTF("cant i2c write: no ack\n");
445 mtx_unlock(&sc->mutex);
453 mtx_unlock(&sc->mutex);
457 static device_method_t i2c_methods[] = {
458 DEVMETHOD(device_probe, i2c_probe),
459 DEVMETHOD(device_attach, i2c_attach),
461 DEVMETHOD(iicbus_callback, iicbus_null_callback),
462 DEVMETHOD(iicbus_start, i2c_start),
463 DEVMETHOD(iicbus_stop, i2c_stop),
464 DEVMETHOD(iicbus_reset, i2c_reset),
465 DEVMETHOD(iicbus_read, i2c_read),
466 DEVMETHOD(iicbus_write, i2c_write),
467 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
472 static driver_t i2c_driver = {
475 sizeof(struct i2c_softc),
478 static devclass_t i2c_devclass;
480 DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0);
481 DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0);